1//===-- ARMSystemRegister.td - ARM Register defs -------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10include "llvm/TableGen/SearchableTable.td"
11
12//===----------------------------------------------------------------------===//
13//  Declarations that describe the ARM system-registers
14//===----------------------------------------------------------------------===//
15
16// M-Class System Registers.
17// 'Mask' bits create unique keys for searches.
18//
19class MClassSysReg<bits<1> UniqMask1,
20                   bits<1> UniqMask2,
21                   bits<1> UniqMask3,
22                   bits<12> Enc12,
23                   string name> : SearchableTable {
24  let SearchableFields = ["Name", "M1Encoding12", "M2M3Encoding8", "Encoding"];
25  string Name;
26  bits<13> M1Encoding12;
27  bits<10> M2M3Encoding8;
28  bits<12> Encoding;
29
30  let Name = name;
31  let EnumValueField = "M1Encoding12";
32  let EnumValueField = "M2M3Encoding8";
33  let EnumValueField = "Encoding";
34
35  let M1Encoding12{12}    = UniqMask1;
36  let M1Encoding12{11-00} = Enc12;
37  let Encoding            = Enc12;
38
39  let M2M3Encoding8{9}    = UniqMask2;
40  let M2M3Encoding8{8}    = UniqMask3;
41  let M2M3Encoding8{7-0}  = Enc12{7-0};
42  code Requires           = [{ {} }];
43}
44
45// [|i|e|x]apsr_nzcvq has alias [|i|e|x]apsr.
46//                 Mask1 Mask2 Mask3 Enc12, Name
47let Requires = [{ {ARM::FeatureDSP} }] in {
48def : MClassSysReg<0,    0,    0,    0x400, "apsr_g">;
49def : MClassSysReg<0,    1,    1,    0xc00, "apsr_nzcvqg">;
50def : MClassSysReg<0,    0,    0,    0x401, "iapsr_g">;
51def : MClassSysReg<0,    1,    1,    0xc01, "iapsr_nzcvqg">;
52def : MClassSysReg<0,    0,    0,    0x402, "eapsr_g">;
53def : MClassSysReg<0,    1,    1,    0xc02, "eapsr_nzcvqg">;
54def : MClassSysReg<0,    0,    0,    0x403, "xpsr_g">;
55def : MClassSysReg<0,    1,    1,    0xc03, "xpsr_nzcvqg">;
56}
57
58def : MClassSysReg<0,    0,    1,    0x800, "apsr">;
59def : MClassSysReg<1,    1,    0,    0x800, "apsr_nzcvq">;
60def : MClassSysReg<0,    0,    1,    0x801, "iapsr">;
61def : MClassSysReg<1,    1,    0,    0x801, "iapsr_nzcvq">;
62def : MClassSysReg<0,    0,    1,    0x802, "eapsr">;
63def : MClassSysReg<1,    1,    0,    0x802, "eapsr_nzcvq">;
64def : MClassSysReg<0,    0,    1,    0x803, "xpsr">;
65def : MClassSysReg<1,    1,    0,    0x803, "xpsr_nzcvq">;
66
67def : MClassSysReg<0,    0,    1,    0x805, "ipsr">;
68def : MClassSysReg<0,    0,    1,    0x806, "epsr">;
69def : MClassSysReg<0,    0,    1,    0x807, "iepsr">;
70def : MClassSysReg<0,    0,    1,    0x808, "msp">;
71def : MClassSysReg<0,    0,    1,    0x809, "psp">;
72
73let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
74def : MClassSysReg<0,    0,    1,    0x80a, "msplim">;
75def : MClassSysReg<0,    0,    1,    0x80b, "psplim">;
76}
77
78def : MClassSysReg<0,    0,    1,    0x810, "primask">;
79
80let Requires = [{ {ARM::HasV7Ops} }] in {
81def : MClassSysReg<0,    0,    1,    0x811, "basepri">;
82def : MClassSysReg<0,    0,    1,    0x812, "basepri_max">;
83def : MClassSysReg<0,    0,    1,    0x813, "faultmask">;
84}
85
86def : MClassSysReg<0,    0,    1,    0x814, "control">;
87
88let Requires = [{ {ARM::Feature8MSecExt} }] in {
89def : MClassSysReg<0,    0,    1,    0x888, "msp_ns">;
90def : MClassSysReg<0,    0,    1,    0x889, "psp_ns">;
91}
92
93let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
94def : MClassSysReg<0,    0,    1,    0x88a, "msplim_ns">;
95def : MClassSysReg<0,    0,    1,    0x88b, "psplim_ns">;
96}
97
98def : MClassSysReg<0,    0,    1,    0x890, "primask_ns">;
99
100let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV7Ops} }] in {
101def : MClassSysReg<0,    0,    1,    0x891, "basepri_ns">;
102def : MClassSysReg<0,    0,    1,    0x893, "faultmask_ns">;
103}
104
105let Requires = [{ {ARM::Feature8MSecExt} }] in {
106def : MClassSysReg<0,    0,    1,    0x894, "control_ns">;
107def : MClassSysReg<0,    0,    1,    0x898, "sp_ns">;
108}
109
110
111// Banked Registers
112//
113class BankedReg<string name,  bits<8> enc>
114               : SearchableTable {
115  string Name;
116  bits<8> Encoding;
117  let Name = name;
118  let Encoding = enc;
119  let SearchableFields = ["Name", "Encoding"];
120}
121
122// The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
123// and bit 5 is R.
124def : BankedReg<"r8_usr",   0x00>;
125def : BankedReg<"r9_usr",   0x01>;
126def : BankedReg<"r10_usr",  0x02>;
127def : BankedReg<"r11_usr",  0x03>;
128def : BankedReg<"r12_usr",  0x04>;
129def : BankedReg<"sp_usr",   0x05>;
130def : BankedReg<"lr_usr",   0x06>;
131def : BankedReg<"r8_fiq",   0x08>;
132def : BankedReg<"r9_fiq",   0x09>;
133def : BankedReg<"r10_fiq",  0x0a>;
134def : BankedReg<"r11_fiq",  0x0b>;
135def : BankedReg<"r12_fiq",  0x0c>;
136def : BankedReg<"sp_fiq",   0x0d>;
137def : BankedReg<"lr_fiq",   0x0e>;
138def : BankedReg<"lr_irq",   0x10>;
139def : BankedReg<"sp_irq",   0x11>;
140def : BankedReg<"lr_svc",   0x12>;
141def : BankedReg<"sp_svc",   0x13>;
142def : BankedReg<"lr_abt",   0x14>;
143def : BankedReg<"sp_abt",   0x15>;
144def : BankedReg<"lr_und",   0x16>;
145def : BankedReg<"sp_und",   0x17>;
146def : BankedReg<"lr_mon",   0x1c>;
147def : BankedReg<"sp_mon",   0x1d>;
148def : BankedReg<"elr_hyp",  0x1e>;
149def : BankedReg<"sp_hyp",   0x1f>;
150def : BankedReg<"spsr_fiq", 0x2e>;
151def : BankedReg<"spsr_irq", 0x30>;
152def : BankedReg<"spsr_svc", 0x32>;
153def : BankedReg<"spsr_abt", 0x34>;
154def : BankedReg<"spsr_und", 0x36>;
155def : BankedReg<"spsr_mon", 0x3c>;
156def : BankedReg<"spsr_hyp", 0x3e>;
157