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Searched refs:HasV8MBaselineOps (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenSystemRegister.inc275 { "msplim", 0x80A, 0x10A, 0x80A, {ARM::HasV8MBaselineOps} }, // 21
276 { "psplim", 0x80B, 0x10B, 0x80B, {ARM::HasV8MBaselineOps} }, // 22
284 { "msplim_ns", 0x88A, 0x18A, 0x88A, {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }, // 30
285 { "psplim_ns", 0x88B, 0x18B, 0x88B, {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }, // 31
DARMGenSubtargetInfo.inc127 HasV8MBaselineOps = 111,
220 …se", "ARMv8mBaseline architecture", { ARM::ARMv8mBaseline }, { ARM::HasV8MBaselineOps, ARM::Featur…
304 …{ "v6t2", "Support ARM v6t2 instructions", { ARM::HasV6T2Ops }, { ARM::HasV8MBaselineOps, ARM::Has…
312 …{ "v8m", "Support ARM v8M Baseline instructions", { ARM::HasV8MBaselineOps }, { ARM::HasV6MOps } },
16606 if (Bits[ARM::HasV8MBaselineOps]) HasV8MBaselineOps = true;
DARMGenDisassemblerTables.inc11275 return (Bits[ARM::ModeThumb] && Bits[ARM::HasV8MBaselineOps]);
11321 return (Bits[ARM::FeatureHWDivThumb] && Bits[ARM::ModeThumb] && Bits[ARM::HasV8MBaselineOps]);
DARMGenMCCodeEmitter.inc11193 if ((FB[ARM::HasV8MBaselineOps]))
DARMGenAsmMatcher.inc7643 if ((FB[ARM::HasV8MBaselineOps]))
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMSystemRegister.td73 let Requires = [{ {ARM::HasV8MBaselineOps} }] in {
93 let Requires = [{ {ARM::Feature8MSecExt, ARM::HasV8MBaselineOps} }] in {
DARMSubtarget.h156 bool HasV8MBaselineOps = false; variable
532 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } in hasV8MBaselineOps()
DARM.td401 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
411 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
674 [HasV8MBaselineOps,
DARMInstrInfo.td233 AssemblerPredicate<"HasV8MBaselineOps",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.cpp179 bool HasV8MBaselineOps = STI.getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode() local
191 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op; in getRelaxedOpcode()
538 !STI->getFeatureBits()[ARM::HasV8MBaselineOps] && in adjustFixupValue()
638 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { in adjustFixupValue()
DARMTargetStreamer.cpp136 else if (STI.hasFeature(ARM::HasV8MBaselineOps)) in getArchForCPU()
154 return (STI.hasFeature(ARM::HasV8MBaselineOps) && in isV8M()
/external/llvm/lib/Target/ARM/
DARMSubtarget.h98 bool HasV8MBaselineOps = false; variable
404 bool hasV8MBaselineOps() const { return HasV8MBaselineOps; } in hasV8MBaselineOps()
DARM.td283 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
291 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
474 [HasV8MBaselineOps,
DARMInstrInfo.td201 AssemblerPredicate<"HasV8MBaselineOps",
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMAsmBackend.cpp176 bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps]; in getRelaxedOpcode() local
188 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op; in getRelaxedOpcode()
589 !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) { in adjustFixupValue()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp279 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; in hasV8MBaseline()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp474 return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps]; in hasV8MBaseline()