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Searched refs:IDFetch (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp40 InstKindLimit[IDFetch] = ST.getTexVTXClauseSize(); in initialize()
67 (!Available[IDFetch].empty() || !Available[IDOther].empty()); in pickNode()
69 if (CurInstKind == IDAlu && !Available[IDFetch].empty()) { in pickNode()
76 (FetchInstCount + Available[IDFetch].size()); in pickNode()
92 unsigned NearRegisterRequirement = 2 * Available[IDFetch].size(); in pickNode()
115 SU = pickOther(IDFetch); in pickNode()
117 NextInstKind = IDFetch; in pickNode()
178 if (CurInstKind != IDFetch) { in schedNode()
179 MoveUnits(Pending[IDFetch], Available[IDFetch]); in schedNode()
299 return IDFetch; in getInstKind()
DR600MachineScheduler.h35 IDFetch, enumerator
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp41 InstKindLimit[IDFetch] = ST.getTexVTXClauseSize(); in initialize()
68 (!Available[IDFetch].empty() || !Available[IDOther].empty()); in pickNode()
70 if (CurInstKind == IDAlu && !Available[IDFetch].empty()) { in pickNode()
77 (FetchInstCount + Available[IDFetch].size()); in pickNode()
93 unsigned NearRegisterRequirement = 2 * Available[IDFetch].size(); in pickNode()
116 SU = pickOther(IDFetch); in pickNode()
118 NextInstKind = IDFetch; in pickNode()
176 if (CurInstKind != IDFetch) { in schedNode()
177 MoveUnits(Pending[IDFetch], Available[IDFetch]); in schedNode()
298 return IDFetch; in getInstKind()
DR600MachineScheduler.h36 IDFetch, enumerator