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Searched refs:ILVEV (Results 1 – 20 of 20) sorted by relevance

/external/llvm/lib/Target/Mips/
DMipsISelLowering.h184 ILVEV, // Interleave even elements enumerator
DMipsSEISelLowering.cpp1917 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2581 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt); in lowerVECTOR_SHUFFLE_ILVEV()
DMipsISelLowering.cpp214 case MipsISD::ILVEV: return "MipsISD::ILVEV"; in getTargetNodeName()
DMipsMSAInstrInfo.td50 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsISelLowering.h230 ILVEV, // Interleave even elements enumerator
DMipsScheduleP5600.td394 def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>;
DMipsSEISelLowering.cpp1899 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2672 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt); in lowerVECTOR_SHUFFLE_ILVEV()
DMipsScheduleGeneric.td997 def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>;
DMipsISelLowering.cpp292 case MipsISD::ILVEV: return "MipsISD::ILVEV"; in getTargetNodeName()
DMipsMSAInstrInfo.td42 def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
/external/v8/src/mips/
Dconstants-mips.h884 ILVEV = ((6U << 23) + 20), enumerator
Ddisasm-mips.cc2413 case ILVEV: in DecodeTypeMsa3R()
Dsimulator-mips.cc5142 case ILVEV: in Msa3RInstrHelper_shuffle()
5264 case ILVEV: in DecodeTypeMsa3R()
Dassembler-mips.cc3490 V(ilvev, ILVEV) \
/external/v8/src/mips64/
Dconstants-mips64.h918 ILVEV = ((6U << 23) + 20), enumerator
Ddisasm-mips64.cc2727 case ILVEV: in DecodeTypeMsa3R()
Dsimulator-mips64.cc5366 case ILVEV: in Msa3RInstrHelper_shuffle()
5488 case ILVEV: in DecodeTypeMsa3R()
Dassembler-mips64.cc3808 V(ilvev, ILVEV) \
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenFastISel.inc2952 // FastEmit functions for MipsISD::ILVEV.
3424 case MipsISD::ILVEV: return fastEmit_MipsISD_ILVEV_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
DMipsGenDAGISel.inc29596 /* 55608*/ /*SwitchOpcode*/ 52, TARGET_VAL(MipsISD::ILVEV),// ->55663