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Searched refs:IMPL (Results 1 – 8 of 8) sorted by relevance

/external/clang/test/Index/
Dannotate-toplevel-in-objccontainer.m26 // RUN: | FileCheck -check-prefix=CHECK-IMPL %s
27 // CHECK-IMPL: Identifier: "meth1" [14:8 - 14:13] ObjCInstanceMethodDecl=meth1:14:8 (Definition)
28 // CHECK-IMPL: Identifier: "meth2" [15:8 - 15:13] ObjCInstanceMethodDecl=meth2:15:8 (Definition)
Dget-cursor.m143 // RUN: c-index-test -cursor-at=%s:37:17 %s | FileCheck -check-prefix=CHECK-IN-IMPL %s
144 // CHECK-IN-IMPL: VarDecl=i:37:17
/external/clang/test/PCH/
Dmethod-redecls.m2 // RUN: %clang_cc1 -x objective-c %s -emit-pch -o %t -D IMPL
12 #ifdef IMPL
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/WholeProgramDevirt/
Dimport.ll1 …ad-summary=%S/Inputs/import-single-impl.yaml < %s | FileCheck --check-prefixes=CHECK,SINGLE-IMPL %s
34 ; SINGLE-IMPL: call i32 bitcast (void ()* @singleimpl1 to i32 (i8*, i32)*)
59 ; SINGLE-IMPL: br i1 true,
64 ; SINGLE-IMPL: call i1 bitcast (void ()* @singleimpl2 to i1 (i8*, i32)*)
107 ; SINGLE-IMPL-DAG: declare void @singleimpl1()
108 ; SINGLE-IMPL-DAG: declare void @singleimpl2()
/external/llvm/include/llvm/TableGen/
DSearchableTable.td28 // Inside the IMPL guard will be a primary data table "{InstanceClass}sList" and
/external/clang/include/clang/Analysis/
DCFG.h572 template <typename IMPL, bool IsPred>
575 IMPL I, E;
579 explicit FilteredCFGBlockIterator(const IMPL &i, const IMPL &e, in FilteredCFGBlockIterator()
/external/v8/src/base/
Dlogging.h241 #define DEFINE_SIGNED_MISMATCH_COMP(CHECK, NAME, IMPL) \ argument
245 return IMPL; \
/external/syzkaller/pkg/ifuzz/gen/
Dall-enc-instructions.txt33 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
43 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
53 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87POP:r:SUPP REG2=XED_REG_X8…
63 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
73 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
83 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
93 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
103 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
113 OPERANDS : REG0=XED_REG_ST0:rw:IMPL:f80 REG1=X87():r:f80 REG2=XED_REG_X87STATUS:w:SUPP
123 OPERANDS : REG0=XED_REG_ST0:r:IMPL:f80 MEM0:r:mem32real REG1=XED_REG_X87STATUS:w:SUPP
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