| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 156 INTRINSIC_VOID, enumerator
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| D | SelectionDAGNodes.h | 1087 N->getOpcode() == ISD::INTRINSIC_VOID ||
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 161 INTRINSIC_VOID, enumerator
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| D | SelectionDAGNodes.h | 484 NodeType == ISD::INTRINSIC_VOID) && ((SubclassData >> 13) & 1);
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 166 INTRINSIC_VOID, enumerator
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| D | SelectionDAGNodes.h | 648 NodeType == ISD::INTRINSIC_VOID) &&
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/GlobalISel/ |
| D | SelectionDAGCompat.td | 81 // ISD::INTRINSIC_VOID can also be handled with G_INTRINSIC_W_SIDE_EFFECTS.
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 117 case ISD::INTRINSIC_VOID: in getOperationName()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 140 case ISD::INTRINSIC_VOID: in getOperationName()
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| D | TargetLowering.cpp | 1668 Op.getOpcode() == ISD::INTRINSIC_VOID) && in computeKnownBitsForTargetNode()
1696 Op.getOpcode() == ISD::INTRINSIC_VOID) && in ComputeNumSignBitsForTargetNode()
1708 Op.getOpcode() == ISD::INTRINSIC_VOID) && in SimplifyDemandedVectorEltsForTargetNode()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 847 case ISD::INTRINSIC_VOID: { in trySelect()
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| D | MipsSEISelLowering.cpp | 148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in MipsSETargetLowering()
375 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 474 setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom); in PPCTargetLowering()
475 setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom); in PPCTargetLowering()
476 setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom); in PPCTargetLowering()
477 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in PPCTargetLowering()
1073 setTargetDAGCombine(ISD::INTRINSIC_VOID); in PPCTargetLowering()
9195 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, in LowerEXTRACT_VECTOR_ELT()
9394 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, in LowerVectorStore()
9561 case ISD::INTRINSIC_VOID: in LowerOperation()
10989 if (N->getOpcode() == ISD::INTRINSIC_VOID) { in isConsecutiveLS()
12350 case ISD::INTRINSIC_VOID: { in expandVSXStoreForLE()
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 175 setTargetDAGCombine(ISD::INTRINSIC_VOID); in XCoreTargetLowering()
1608 case ISD::INTRINSIC_VOID: in PerformDAGCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 172 setTargetDAGCombine(ISD::INTRINSIC_VOID); in XCoreTargetLowering()
1590 case ISD::INTRINSIC_VOID: in PerformDAGCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 902 case ISD::INTRINSIC_VOID: { in trySelect()
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| D | MipsSEISelLowering.cpp | 215 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in MipsSETargetLowering()
461 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | R600ISelLowering.cpp | 270 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in R600TargetLowering()
500 case ISD::INTRINSIC_VOID: { in LowerOperation()
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| D | SIISelLowering.cpp | 217 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in SITargetLowering()
218 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2i16, Custom); in SITargetLowering()
219 setOperationAction(ISD::INTRINSIC_VOID, MVT::v2f16, Custom); in SITargetLowering()
220 setOperationAction(ISD::INTRINSIC_VOID, MVT::v4f16, Custom); in SITargetLowering()
808 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
3615 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
3950 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID || in LowerBRCOND()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 869 setTargetDAGCombine(ISD::INTRINSIC_VOID); in PPCTargetLowering()
7929 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, in LowerEXTRACT_VECTOR_ELT()
8135 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID, in LowerVectorStore()
9625 if (N->getOpcode() == ISD::INTRINSIC_VOID) { in isConsecutiveLS()
10518 case ISD::INTRINSIC_VOID: { in expandVSXStoreForLE()
10978 case ISD::INTRINSIC_VOID: { in PerformDAGCombine()
11825 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
11860 Info.opc = ISD::INTRINSIC_VOID; in getTgtMemIntrinsic()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 2081 case ISD::INTRINSIC_VOID: in ComputeMaskedBits()
2281 Op.getOpcode() == ISD::INTRINSIC_VOID) { in ComputeNumSignBits()
4073 assert((Opcode == ISD::INTRINSIC_VOID || in getMemIntrinsicNode()
5924 case ISD::INTRINSIC_VOID: in getOperationName()
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| D | TargetLowering.cpp | 1851 Op.getOpcode() == ISD::INTRINSIC_VOID) && in computeMaskedBitsForTargetNode()
1865 Op.getOpcode() == ISD::INTRINSIC_VOID) && in ComputeNumSignBitsForTargetNode()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1297 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in HexagonTargetLowering()
2827 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIISelLowering.cpp | 1255 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
1402 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL, in LowerBRCOND()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1799 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); in HexagonTargetLowering()
2799 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); in LowerOperation()
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