| /external/llvm/lib/Transforms/Utils/ |
| D | LoopUtils.cpp | 194 InstDesc ReduxDesc(false, nullptr); in AddReductionVar()
318 InstDesc IgnoredVal(false, nullptr); in AddReductionVar()
372 RecurrenceDescriptor::InstDesc
373 RecurrenceDescriptor::isMinMaxSelectCmpPattern(Instruction *I, InstDesc &Prev) { in isMinMaxSelectCmpPattern()
384 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
385 return InstDesc(Select, Prev.getMinMaxKind()); in isMinMaxSelectCmpPattern()
390 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
393 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
395 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
402 return InstDesc(Select, MRK_UIntMin); in isMinMaxSelectCmpPattern()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Utils/ |
| D | LoopUtils.cpp | 226 InstDesc ReduxDesc(false, nullptr); in AddReductionVar()
356 InstDesc IgnoredVal(false, nullptr); in AddReductionVar()
445 RecurrenceDescriptor::InstDesc
446 RecurrenceDescriptor::isMinMaxSelectCmpPattern(Instruction *I, InstDesc &Prev) { in isMinMaxSelectCmpPattern()
457 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
458 return InstDesc(Select, Prev.getMinMaxKind()); in isMinMaxSelectCmpPattern()
463 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
466 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
468 return InstDesc(false, I); in isMinMaxSelectCmpPattern()
475 return InstDesc(Select, MRK_UIntMin); in isMinMaxSelectCmpPattern()
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| /external/llvm/include/llvm/Transforms/Utils/ |
| D | LoopUtils.h | 104 class InstDesc {
107 InstDesc(bool IsRecur, Instruction *I, Instruction *UAI = nullptr)
111 InstDesc(Instruction *I, MinMaxRecurrenceKind K, Instruction *UAI = nullptr)
142 static InstDesc isRecurrenceInstr(Instruction *I, RecurrenceKind Kind,
143 InstDesc &Prev, bool HasFunNoNaNAttr);
155 static InstDesc isMinMaxSelectCmpPattern(Instruction *I, InstDesc &Prev);
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Transforms/Utils/ |
| D | LoopUtils.h | 102 class InstDesc {
104 InstDesc(bool IsRecur, Instruction *I, Instruction *UAI = nullptr)
108 InstDesc(Instruction *I, MinMaxRecurrenceKind K, Instruction *UAI = nullptr)
139 static InstDesc isRecurrenceInstr(Instruction *I, RecurrenceKind Kind,
140 InstDesc &Prev, bool HasFunNoNaNAttr);
152 static InstDesc isMinMaxSelectCmpPattern(Instruction *I, InstDesc &Prev);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SIMDInstrOpt.cpp | 161 bool shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc,
219 shouldReplaceInst(MachineFunction *MF, const MCInstrDesc *InstDesc, in shouldReplaceInst() argument
224 auto InstID = std::make_pair(InstDesc->getOpcode(), Subtarget); in shouldReplaceInst()
228 unsigned SCIdx = InstDesc->getSchedClass(); in shouldReplaceInst()
256 if (SchedModel.computeInstrLatency(InstDesc->getOpcode()) > ReplCost) in shouldReplaceInst()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 2005 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
2006 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in isOperandLegal()
2027 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) { in isOperandLegal()
2708 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitUnaryOp() local
2723 BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitUnaryOp()
2730 BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitUnaryOp()
2762 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitBinaryOp() local
2784 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
2794 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
2827 const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64); in splitScalar64BitBCNT() local
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.cpp | 3202 const MCInstrDesc &InstDesc = MI.getDesc(); in isOperandLegal() local
3203 const MCOperandInfo &OpInfo = InstDesc.OpInfo[OpIdx]; in isOperandLegal()
3221 usesConstantBus(MRI, Op, InstDesc.OpInfo[i])) { in isOperandLegal()
3224 } else if (InstDesc.OpInfo[i].OperandType == AMDGPU::OPERAND_KIMM32) { in isOperandLegal()
4188 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitUnaryOp() local
4203 BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
4209 BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1); in splitScalar64BitUnaryOp()
4308 const MCInstrDesc &InstDesc = get(Opcode); in splitScalar64BitBinaryOp() local
4330 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0) in splitScalar64BitBinaryOp()
4340 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1) in splitScalar64BitBinaryOp()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/AsmParser/ |
| D | AMDGPUAsmParser.cpp | 1399 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode()); in addLiteralImmOperand() local
1402 assert(AMDGPU::isSISrcOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1405 assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum)); in addLiteralImmOperand()
1406 const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum); in addLiteralImmOperand()
1411 uint8_t OpTy = InstDesc.OpInfo[OpNum].OperandType; in addLiteralImmOperand()
1426 if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand in addLiteralImmOperand()
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