/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMScheduleA9.td | 42 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 43 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>, 44 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 45 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 46 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 48 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 49 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, 50 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 51 InstrStage<1, [A9_ALU0, A9_ALU1]>, [all …]
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D | ARMScheduleA8.td | 31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>, 38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, [all …]
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D | ARMScheduleV6.td | 25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 34 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 36 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 37 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 40 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
D | PPCSchedule440.td | 108 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>, 109 InstrStage<1, [P440_IRACC, P440_LRACC]>, 110 InstrStage<1, [P440_IEXE1, P440_JEXE1]>, 111 InstrStage<1, [P440_IEXE2, P440_JEXE2]>, 112 InstrStage<1, [P440_IWB, P440_JWB]>], 116 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>, 117 InstrStage<1, [P440_IRACC, P440_LRACC]>, 118 InstrStage<1, [P440_IEXE1, P440_JEXE1]>, 119 InstrStage<1, [P440_IEXE2, P440_JEXE2]>, 120 InstrStage<1, [P440_IWB, P440_JWB]>], [all …]
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D | PPCScheduleP7.td | 83 InstrItinData<IIC_IntSimple , [InstrStage<1, [P7_DU1, P7_DU2, 85 InstrStage<1, [P7_FX1, P7_FX2, 88 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P7_DU1, P7_DU2, 90 InstrStage<1, [P7_FX1, P7_FX2]>], 92 InstrItinData<IIC_IntISEL, [InstrStage<1, [P7_DU1], 0>, 93 InstrStage<1, [P7_FX1, P7_FX2], 0>, 94 InstrStage<1, [P7_BRU]>], 96 InstrItinData<IIC_IntCompare , [InstrStage<1, [P7_DU1, P7_DU2, 98 InstrStage<1, [P7_FX1, P7_FX2]>], 101 InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>, [all …]
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D | PPCScheduleP8.td | 58 InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 60 InstrStage<1, [P8_FXU1, P8_FXU2, 64 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 66 InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1, 69 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>, 70 InstrStage<1, [P8_FXU1, P8_FXU2], 0>, 71 InstrStage<1, [P8_BRU]>], 73 InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 75 InstrStage<1, [P8_FXU1, P8_FXU2]>], 77 InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, [all …]
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D | PPCScheduleE5500.td | 51 InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 52 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 56 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 57 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 61 InstrItinData<IIC_IntISEL, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 62 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 67 InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 68 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 72 InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 73 InstrStage<1, [E5500_CFX_0], 0>, [all …]
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D | PPCScheduleG5.td | 29 InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 30 InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 31 InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>, 32 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>, 33 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>, 34 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>, 35 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>, 36 InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 37 InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>, 38 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>, [all …]
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/external/llvm/lib/Target/PowerPC/ |
D | PPCSchedule440.td | 108 InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>, 109 InstrStage<1, [P440_IRACC, P440_LRACC]>, 110 InstrStage<1, [P440_IEXE1, P440_JEXE1]>, 111 InstrStage<1, [P440_IEXE2, P440_JEXE2]>, 112 InstrStage<1, [P440_IWB, P440_JWB]>], 116 InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>, 117 InstrStage<1, [P440_IRACC, P440_LRACC]>, 118 InstrStage<1, [P440_IEXE1, P440_JEXE1]>, 119 InstrStage<1, [P440_IEXE2, P440_JEXE2]>, 120 InstrStage<1, [P440_IWB, P440_JWB]>], [all …]
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D | PPCScheduleP7.td | 83 InstrItinData<IIC_IntSimple , [InstrStage<1, [P7_DU1, P7_DU2, 85 InstrStage<1, [P7_FX1, P7_FX2, 88 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P7_DU1, P7_DU2, 90 InstrStage<1, [P7_FX1, P7_FX2]>], 92 InstrItinData<IIC_IntISEL, [InstrStage<1, [P7_DU1], 0>, 93 InstrStage<1, [P7_FX1, P7_FX2], 0>, 94 InstrStage<1, [P7_BRU]>], 96 InstrItinData<IIC_IntCompare , [InstrStage<1, [P7_DU1, P7_DU2, 98 InstrStage<1, [P7_FX1, P7_FX2]>], 101 InstrItinData<IIC_IntDivW , [InstrStage<1, [P7_DU1], 0>, [all …]
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D | PPCScheduleP8.td | 58 InstrItinData<IIC_IntSimple , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 60 InstrStage<1, [P8_FXU1, P8_FXU2, 64 InstrItinData<IIC_IntGeneral , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 66 InstrStage<1, [P8_FXU1, P8_FXU2, P8_LU1, 69 InstrItinData<IIC_IntISEL, [InstrStage<1, [P8_DU1], 0>, 70 InstrStage<1, [P8_FXU1, P8_FXU2], 0>, 71 InstrStage<1, [P8_BRU]>], 73 InstrItinData<IIC_IntCompare , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, 75 InstrStage<1, [P8_FXU1, P8_FXU2]>], 77 InstrItinData<IIC_IntDivW , [InstrStage<1, [P8_DU1, P8_DU2, P8_DU3, [all …]
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D | PPCScheduleE5500.td | 51 InstrItinData<IIC_IntSimple, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 52 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 56 InstrItinData<IIC_IntGeneral, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 57 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 61 InstrItinData<IIC_IntISEL, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 62 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 67 InstrItinData<IIC_IntCompare, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 68 InstrStage<1, [E5500_SFX0, E5500_SFX1]>], 72 InstrItinData<IIC_IntDivD, [InstrStage<1, [E5500_DIS0, E5500_DIS1], 0>, 73 InstrStage<1, [E5500_CFX_0], 0>, [all …]
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D | PPCScheduleG5.td | 29 InstrItinData<IIC_IntSimple , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 30 InstrItinData<IIC_IntGeneral , [InstrStage<2, [G5_IU1, G5_IU2]>]>, 31 InstrItinData<IIC_IntCompare , [InstrStage<3, [G5_IU1, G5_IU2]>]>, 32 InstrItinData<IIC_IntDivD , [InstrStage<68, [G5_IU1]>]>, 33 InstrItinData<IIC_IntDivW , [InstrStage<36, [G5_IU1]>]>, 34 InstrItinData<IIC_IntMFFS , [InstrStage<6, [G5_IU2]>]>, 35 InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [G5_VFPU]>]>, 36 InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>, 37 InstrItinData<IIC_IntMulHD , [InstrStage<7, [G5_IU1, G5_IU2]>]>, 38 InstrItinData<IIC_IntMulHW , [InstrStage<5, [G5_IU1, G5_IU2]>]>, [all …]
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/external/llvm/lib/Target/X86/ |
D | X86ScheduleAtom.td | 29 // InstrItinData<class, [InstrStage<N, [P0]>] >, 31 // InstrItinData<class, [InstrStage<N, [P0, P1]>] >, 33 // InstrItinData<class, [InstrStage<N, [P0], 0>, InstrStage<N, [P1]>] >, 36 InstrItinData<IIC_ALU_MEM, [InstrStage<1, [Port0]>] >, 37 InstrItinData<IIC_ALU_NONMEM, [InstrStage<1, [Port0, Port1]>] >, 38 InstrItinData<IIC_LEA, [InstrStage<1, [Port1]>] >, 39 InstrItinData<IIC_LEA_16, [InstrStage<2, [Port0, Port1]>] >, 41 InstrItinData<IIC_MUL8, [InstrStage<7, [Port0, Port1]>] >, 42 InstrItinData<IIC_MUL16_MEM, [InstrStage<8, [Port0, Port1]>] >, 43 InstrItinData<IIC_MUL16_REG, [InstrStage<7, [Port0, Port1]>] >, [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMScheduleA8.td | 31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>, 38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, [all …]
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D | ARMScheduleA9.td | 46 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>, 48 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 49 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 50 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 51 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 52 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 53 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, 54 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 55 InstrStage<1, [A9_ALU0, A9_ALU1]>, [all …]
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D | ARMScheduleV6.td | 25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 34 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 36 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 37 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 40 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, [all …]
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/external/llvm/lib/Target/ARM/ |
D | ARMScheduleA8.td | 31 InstrItinData<IIC_iALUx , [InstrStage<1, [A8_Pipe0, A8_Pipe1]>]>, 34 InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 35 InstrItinData<IIC_iALUr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 36 InstrItinData<IIC_iALUsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 37 InstrItinData<IIC_iALUsir,[InstrStage<1,[A8_Pipe0, A8_Pipe1]>], [2, 1, 2]>, 38 InstrItinData<IIC_iALUsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, 41 InstrItinData<IIC_iBITi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, 42 InstrItinData<IIC_iBITr ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 2]>, 43 InstrItinData<IIC_iBITsi,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1]>, 44 InstrItinData<IIC_iBITsr,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2, 1, 1]>, [all …]
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D | ARMScheduleA9.td | 46 InstrItinData<IIC_iMOVi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 47 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1]>, 48 InstrItinData<IIC_iMOVr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 49 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 50 InstrItinData<IIC_iMOVsi , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 51 InstrStage<1, [A9_ALU0, A9_ALU1]>], [1, 1]>, 52 InstrItinData<IIC_iMOVsr , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 53 InstrStage<2, [A9_ALU0, A9_ALU1]>], [2, 1, 1]>, 54 InstrItinData<IIC_iMOVix2 , [InstrStage<1, [A9_Issue0, A9_Issue1], 0>, 55 InstrStage<1, [A9_ALU0, A9_ALU1]>, [all …]
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D | ARMScheduleV6.td | 25 InstrItinData<IIC_iALUx , [InstrStage<1, [V6_Pipe]>]>, 28 InstrItinData<IIC_iALUi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 29 InstrItinData<IIC_iALUr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 30 InstrItinData<IIC_iALUsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 31 InstrItinData<IIC_iALUsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 34 InstrItinData<IIC_iBITi , [InstrStage<1, [V6_Pipe]>], [2, 2]>, 35 InstrItinData<IIC_iBITr , [InstrStage<1, [V6_Pipe]>], [2, 2, 2]>, 36 InstrItinData<IIC_iBITsi , [InstrStage<1, [V6_Pipe]>], [2, 2, 1]>, 37 InstrItinData<IIC_iBITsr , [InstrStage<2, [V6_Pipe]>], [3, 3, 2, 1]>, 40 InstrItinData<IIC_iUNAr , [InstrStage<1, [V6_Pipe]>], [2, 2]>, [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonDepIICHVX.td | 98 [InstrStage<1, [SLOT0], 0>, 99 InstrStage<1, [CVI_ST], 0>, 100 InstrStage<1, [CVI_MPY0, CVI_MPY1, CVI_SHIFT, CVI_XLANE]>], [3, 2, 1, 2, 7], 104 [InstrStage<1, [SLOT0], 0>, 105 InstrStage<1, [CVI_ST]>], [1, 2, 5], 109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, 110 InstrStage<1, [CVI_MPY01, CVI_XLSHF]>], [9, 2, 7, 7], 114 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>, 115 InstrStage<1, [CVI_ALL]>], [3, 2], 119 [InstrStage<1, [SLOT0], 0>, [all …]
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D | HexagonDepIICScalar.td | 177 InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>, 178 InstrItinData <tc_00e7c26e, [InstrStage<1, [SLOT0]>]>, 179 InstrItinData <tc_03220ffa, [InstrStage<1, [SLOT0, SLOT1]>]>, 180 InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>, 181 InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>, 182 InstrItinData <tc_05b6c987, [InstrStage<1, [SLOT0, SLOT1]>]>, 183 InstrItinData <tc_0cd51c76, [InstrStage<1, [SLOT0, SLOT1]>]>, 184 InstrItinData <tc_0dc560de, [InstrStage<1, [SLOT0, SLOT1]>]>, 185 InstrItinData <tc_0fc1ae07, [InstrStage<1, [SLOT0]>]>, 186 InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>, [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | MipsSchedule.td | 384 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>, 385 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>, 386 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>, 387 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>, 388 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>, 389 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>, 390 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>, 391 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>, 392 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>, 393 InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>, [all …]
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/external/llvm/lib/Target/Mips/ |
D | MipsSchedule.td | 314 InstrItinData<IIM16Alu , [InstrStage<1, [ALU]>]>, 315 InstrItinData<II_ADDI , [InstrStage<1, [ALU]>]>, 316 InstrItinData<II_ADDIU , [InstrStage<1, [ALU]>]>, 317 InstrItinData<II_ADDIUPC , [InstrStage<1, [ALU]>]>, 318 InstrItinData<II_ADD , [InstrStage<1, [ALU]>]>, 319 InstrItinData<II_ADDU , [InstrStage<1, [ALU]>]>, 320 InstrItinData<II_AUI , [InstrStage<1, [ALU]>]>, 321 InstrItinData<II_AND , [InstrStage<1, [ALU]>]>, 322 InstrItinData<II_ALUIPC , [InstrStage<1, [ALU]>]>, 323 InstrItinData<II_AUIPC , [InstrStage<1, [ALU]>]>, [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCScheduleG5.td | 16 InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>, 17 InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>, 18 InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>, 19 InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>, 20 InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>, 21 InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>, 22 InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>, 23 InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>, 24 InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>, 25 InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>, [all …]
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