| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/ |
| D | mno-ldc1-sdc1.ll | 3 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-LDC1
7 ; RUN: FileCheck %s -check-prefixes=ALL,32R6-LDC1
117 ; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
121 ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
202 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
206 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
257 ; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
262 ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
305 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
310 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
| /external/llvm/test/CodeGen/Mips/ |
| D | mno-ldc1-sdc1.ll | 3 ; RUN: FileCheck %s -check-prefixes=ALL,32R1-LDC1
7 ; RUN: FileCheck %s -check-prefixes=ALL,32R6-LDC1
117 ; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
121 ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
202 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
206 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
257 ; 32R1-LDC1: ldc1 $f0, 0(${{[0-9]+}})
262 ; 32R6-LDC1: ldc1 $f0, 0(${{[0-9]+}})
305 ; 32R1-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
310 ; 32R6-LDC1: sdc1 $f{{[0-9]+}}, 0(${{[0-9]+}})
|
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsInstrInfo.cpp | 55 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || in isLoadFromStackSlot()
207 Opc = Mips::LDC1; in loadRegFromStackSlot()
|
| D | MipsInstrFPU.td | 208 def LDC1 : FPLoad<0x35, "ldc1", load, AFGR64, mem>;
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 218 case Mips::LDC1: in isBasePlusOffsetMemoryAccess()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsNaClELFStreamer.cpp | 227 case Mips::LDC1: in isBasePlusOffsetMemoryAccess()
|
| /external/v8/src/compiler/mips64/ |
| D | instruction-scheduler-mips64.cc | 445 LDC1 = 4, enumerator
800 int Ldc1Latency() { return AdjustBaseAndOffsetLatency() + Latency::LDC1; } in Ldc1Latency()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
280 Opc = Mips::LDC1; in loadRegFromStack()
|
| D | MipsInstrFPU.td | 420 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
653 def : LoadRegImmPat<LDC1, f64, load>, FGR_32;
|
| D | MipsFastISel.cpp | 750 Opc = Mips::LDC1; in emitLoad()
|
| /external/v8/src/mips/ |
| D | constants-mips.h | 474 LDC1 = ((6U << 3) + 5) << kOpcodeShift, enumerator
1273 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
|
| D | disasm-mips.cc | 1964 case LDC1: in DecodeTypeImmediate()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 51 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
353 Opc = Mips::LDC1; in loadRegFromStack()
|
| D | MipsInstrFPU.td | 549 def LDC1 : MMRel, StdMMR6Rel, LW_FT<"ldc1", AFGR64Opnd, mem_simm16, II_LDC1,
781 <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>,
933 def : LoadRegImmPat<LDC1, f64, load>, ISA_MIPS1, FGR_32;
|
| D | MipsScheduleP5600.td | 566 def : InstRW<[P5600WriteLoadFPU], (instrs LDC1, LDXC1, LWC1, LWXC1, LUXC1)>;
|
| D | MipsFastISel.cpp | 784 Opc = Mips::LDC1; in emitLoad()
|
| /external/v8/src/mips64/ |
| D | constants-mips64.h | 453 LDC1 = ((6U << 3) + 5) << kOpcodeShift, enumerator
1309 OpcodeToBitNumber(LWC1) | OpcodeToBitNumber(LDC1) |
|
| D | disasm-mips64.cc | 2264 case LDC1: in DecodeTypeImmediate()
|
| /external/v8/src/compiler/mips/ |
| D | instruction-scheduler-mips.cc | 412 LDC1 = 4, enumerator
|
| /external/llvm/test/MC/Mips/ |
| D | mips-expansions.s | 16 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
|
| D | target-soft-float.s | 271 # FIXME: LDC1 is correctly rejected but the wrong error message is emitted.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | target-soft-float.s | 271 # FIXME: LDC1 is correctly rejected but the wrong error message is emitted.
|
| D | mips-expansions.s | 52 # LW/SW and LDC1/SDC1 of symbol address, done by MipsAsmParser::expandMemInst():
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenSubtargetInfo.inc | 956 {DBGFIELD("LDC1") 1, false, false, 26, 2, 2, 1, 0, 0}, // #681
1976 {DBGFIELD("LDC1") 2, false, false, 77, 4, 6, 1, 0, 0}, // #681
|
| /external/capstone/arch/Mips/ |
| D | MipsGenAsmWriter.inc | 919 12599337U, // LDC1
2633 0U, // LDC1
4685 // LB, LB64, LB_MM, LBu, LBu64, LBu_MM, LD, LDC1, LDC164, LDC1_MM, LDC2, ...
|