/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
D | machine-outliner-regsave.mir | 75 # CHECK-DAG: early-clobber $sp, $lr = LDRXpost $sp, 16 78 # CHECK-DAG: early-clobber $sp, $lr = LDRXpost $sp, 16 81 # CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16
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D | machine-outliner-calls.mir | 65 # CHECK-NEXT: early-clobber $sp, $lr = LDRXpost $sp, 16
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D | arm64-ldst-unscaled-pre-post.mir | 48 # CHECK: $x1 = LDRXpost $x0, -4
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D | ldst-miflags.mir | 96 ; CHECK: = frame-setup frame-destroy LDRXpost
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D | reverse-csr-restore-seq.mir | 104 ; AFTERLDSTOPT-NEXT: early-clobber $sp, $x21 = frame-destroy LDRXpost $sp, 32
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
D | AArch64FalkorHWPFFix.cpp | 591 case AArch64::LDRXpost: in getLoadInfo()
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D | AArch64InstrInfo.cpp | 5462 MachineInstr *LDRXpost = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost)) in buildOutlinedFrame() local 5467 Et = MBB.insert(Et, LDRXpost); in buildOutlinedFrame() 5541 Restore = BuildMI(MF, DebugLoc(), get(AArch64::LDRXpost)) in insertOutlinedCall()
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D | AArch64FrameLowering.cpp | 451 NewOpc = AArch64::LDRXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
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D | AArch64LoadStoreOptimizer.cpp | 497 return AArch64::LDRXpost; in getPostIndexedOpcode()
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D | AArch64SchedThunderX2T99.td | 727 def : InstRW<[THX2T99Write_5Cyc_LS01_I012, WriteI], (instrs LDRXpost)>; 765 def : InstRW<[THX2T99Write_5Cyc_LS01_I012_I012, WriteI], (instrs LDRXpost)>;
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D | AArch64ISelDAGToDAG.cpp | 1114 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()
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D | AArch64InstrInfo.td | 2150 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64z, "ldr">;
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/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 937 case AArch64::LDRXpost: in DecodeSignedLdStInstruction() 1022 case AArch64::LDRXpost: in DecodeSignedLdStInstruction()
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/external/llvm/lib/Target/AArch64/ |
D | AArch64FrameLowering.cpp | 349 NewOpc = AArch64::LDRXpost; in convertCalleeSaveRestoreToSPPrePostIncDec()
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D | AArch64LoadStoreOptimizer.cpp | 537 return AArch64::LDRXpost; in getPostIndexedOpcode()
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D | AArch64ISelDAGToDAG.cpp | 1057 Opcode = IsPre ? AArch64::LDRXpre : AArch64::LDRXpost; in tryIndexedLoad()
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D | AArch64InstrInfo.td | 1943 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 1122 case AArch64::LDRXpost: in DecodeSignedLdStInstruction() 1215 case AArch64::LDRXpost: in DecodeSignedLdStInstruction()
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/external/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 3527 case AArch64::LDRXpost: { in validateInstruction()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
D | AArch64AsmParser.cpp | 3901 case AArch64::LDRXpost: { in validateInstruction()
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
D | AArch64GenMCCodeEmitter.inc | 2351 UINT64_C(4164944896), // LDRXpost 10021 case AArch64::LDRXpost: 14403 0, // LDRXpost = 2338
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D | AArch64GenAsmWriter1.inc | 4099 742582611U, // LDRXpost 8618 28U, // LDRXpost
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D | AArch64GenAsmWriter.inc | 3150 374960359U, // LDRXpost 7669 28U, // LDRXpost
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/external/capstone/arch/AArch64/ |
D | AArch64GenAsmWriter.inc | 1052 1150584728U, // LDRXpost 3444 4U, // LDRXpost
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D | AArch64GenDisassemblerTables.inc | 7814 /* 32875 */ MCD_OPC_Decode, 139, 8, 226, 1, // Opcode: LDRXpost
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