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/external/mesa3d/src/mesa/drivers/dri/i965/
Dhsw_queryobj.c43 MI_MATH_ALU2(LOAD, SRCA, R0), in mult_gpr0_by_80()
44 MI_MATH_ALU2(LOAD, SRCB, R0), in mult_gpr0_by_80()
47 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
48 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
51 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
52 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
55 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
56 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
60 MI_MATH_ALU2(LOAD, SRCA, R1), in mult_gpr0_by_80()
61 MI_MATH_ALU2(LOAD, SRCB, R1), in mult_gpr0_by_80()
[all …]
Dhsw_sol.c106 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R2)); in tally_prims_written()
107 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
111 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
112 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
128 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
129 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); in tally_prims_written()
137 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
138 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R0)); in tally_prims_written()
141 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCA, R0)); in tally_prims_written()
142 OUT_BATCH(MI_MATH_ALU2(LOAD, SRCB, R1)); in tally_prims_written()
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll2 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=ALL
6 ; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=NOSTORE -check-prefix=ALL
148 ;;;;;;;;;;;;;;;; LOAD
157 ; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0
158 ; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64
159 ; LOAD: call void @__asan_load4(i64 [[PGEP0]])
160 ; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1
161 ; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64
162 ; LOAD: call void @__asan_load4(i64 [[PGEP1]])
163 ; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dlegalize-load.mir12 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
13 ; CHECK: $vgpr0 = COPY [[LOAD]](s32)
28 ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
29 ; CHECK: $vgpr0 = COPY [[LOAD]](s32)
44 ; CHECK: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)
45 ; CHECK: $vgpr0_vgpr1 = COPY [[LOAD]](p1)
60 ; CHECK: [[LOAD:%[0-9]+]]:_(p4) = G_LOAD [[COPY]](p1) :: (load 8, addrspace 1)
61 ; CHECK: $vgpr0_vgpr1 = COPY [[LOAD]](p4)
77 ; CHECK: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
78 ; CHECK: $vgpr0 = COPY [[LOAD]](p3)
[all …]
Dirtranslator-amdgpu_kernel.ll12 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i3…
17 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
31 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i3…
36 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
50 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i3…
55 ; HSA-VI: G_STORE [[SEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
69 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i3…
74 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
88 …; HSA-VI: [[LOAD:%[0-9]+]]:_(p1) = G_LOAD [[GEP]](p4) :: (non-temporal invariant load 8 from `i3…
93 ; HSA-VI: G_STORE [[ZEXT]](s32), [[LOAD]](p1) :: (store 4 into %ir.out, addrspace 1)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvector-promotion.ll6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
14 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
15 ; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
16 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
34 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
35 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
D2012-08-09-neon-extload.ll21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
36 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
[all …]
/external/llvm/test/CodeGen/ARM/
Dvector-promotion.ll6 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
7 ; IR-BOTH-NEXT: [[VECTOR_OR:%[a-zA-Z_0-9-]+]] = or <2 x i32> [[LOAD]], <i32 undef, i32 1>
14 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
15 ; ASM-NEXT: vorr.i32 [[LOAD]], #0x1
16 ; ASM-NEXT: vst1.32 {[[LOAD]][1]}, [r1:32]
27 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
28 ; IR-BOTH-NEXT: [[EXTRACT:%[a-zA-Z_0-9-]+]] = extractelement <2 x i32> [[LOAD]], i32 0
34 ; ASM: vldr [[LOAD:d[0-9]+]], [r0]
35 ; ASM: vmov.32 {{r[0-9]+}}, [[LOAD]]
47 ; IR-BOTH: [[LOAD:%[a-zA-Z_0-9-]+]] = load <2 x i32>, <2 x i32>* %addr1
[all …]
D2012-08-09-neon-extload.ll21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
22 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
36 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
54 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
69 ; CHECK: vmovl.s8 {{q[0-9]+}}, d[[LOAD]]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
83 ; CHECK: vmovl.s16 {{q[0-9]+}}, d[[LOAD]]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
[all …]
/external/u-boot/arch/arm/cpu/arm926ejs/mxs/
Dmxsimage-signed.cfg4 LOAD 0x1000 spl/u-boot-spl.bin
5 LOAD 0x8000 spl/u-boot-spl.ivt
6 LOAD 0x8040 spl/u-boot-spl.sig
8 LOAD 0x40002000 u-boot.bin
9 LOAD 0x40001000 u-boot.ivt
10 LOAD 0x40001040 u-boot.sig
Dmxsimage.mx28.cfg4 LOAD 0x1000 spl/u-boot-spl.bin
5 LOAD IVT 0x8000 0x1000
7 LOAD 0x40002000 u-boot.bin
8 LOAD IVT 0x8000 0x40002000
/external/llvm/test/CodeGen/AMDGPU/
Dtrunc-cmp-constant.ll5 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
6 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
20 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
21 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
46 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
47 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
58 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
59 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
82 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
83 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
[all …]
Dtrunc-store-i1.ll6 ; SI: s_load_dword [[LOAD:s[0-9]+]],
7 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
25 ; SI: s_load_dword [[LOAD:s[0-9]+]],
26 ; SI: s_and_b32 [[SREG:s[0-9]+]], [[LOAD]], 1
/external/mesa3d/src/gallium/drivers/swr/
Dswr_shader.cpp364 LOAD(GEP(iface->pVtxAttribMap, {C(0), attr_chan_index})); in swr_gs_llvm_fetch_input()
366 Value *pVertex = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pVerts}); in swr_gs_llvm_fetch_input()
367 Value *pInputVertStride = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_inputVertStride}); in swr_gs_llvm_fetch_input()
370 Value *pInput = LOAD(GEP(pVertex, {pVector, unwrap(swizzle_index)})); in swr_gs_llvm_fetch_input()
378 Value *attrib = LOAD(GEP(iface->pVtxAttribMap, {C(0), attr_index})); in swr_gs_llvm_fetch_input()
380 Value *pVertex = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pVerts}); in swr_gs_llvm_fetch_input()
381 Value *pInputVertStride = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_inputVertStride}); in swr_gs_llvm_fetch_input()
385 Value *pInput = LOAD(GEP(pVertex, {pVector, unwrap(swizzle_index)})); in swr_gs_llvm_fetch_input()
410 Value *vMask = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_mask}); in swr_gs_llvm_emit_vertex()
438 Value *pStream = LOAD(iface->pGsCtx, {0, SWR_GS_CONTEXT_pStreams, lane}); in swr_gs_llvm_emit_vertex()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dtrunc-cmp-constant.ll7 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
8 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
22 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
23 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
48 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
49 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
60 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
61 ; SI: v_and_b32_e32 [[RESULT:v[0-9]+]], 1, [[LOAD]]
84 ; SI: buffer_load_ubyte [[LOAD:v[0-9]+]]
85 ; SI: v_and_b32_e32 [[TMP:v[0-9]+]], 1, [[LOAD]]
[all …]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
Dstreamout_jit.cpp49 return LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_pBuffer, buffer }); in getSOBuffer()
64 Value* enabled = TRUNC(LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_enable }), IRB()->getInt1Ty()); in oob()
67 Value* bufferSize = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_bufferSize }); in oob()
70 Value* streamOffset = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_streamOffset }); in oob()
73 Value* pitch = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_pitch }); in oob()
148 Value *vattrib = LOAD(pAttrib); in buildDecl()
195 … Value *numPrimStorageNeeded = LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimStorageNeeded }); in buildStream()
214 Value* numPrimsWritten = LOAD(pSoCtx, { 0, SWR_STREAMOUT_CONTEXT_numPrimsWritten }); in buildStream()
225 Value* pData = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_pBuffer }); in buildStream()
226 Value* streamOffset = LOAD(pBuf, { 0, SWR_STREAMOUT_BUFFER_streamOffset }); in buildStream()
[all …]
/external/u-boot/doc/uImage.FIT/
Dx86-fit-boot.txt79 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE
81 CONTENTS, ALLOC, LOAD, READONLY, CODE
83 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
85 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
87 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
89 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
91 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
93 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
95 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA
97 CONTENTS, ALLOC, LOAD, READONLY, DATA
[all …]
/external/llvm/test/tools/llvm-objdump/X86/
Dmacho-private-headers.test5 // RUN: | FileCheck %s -check-prefix=LOAD
364 LOAD: Load command 10
365 LOAD: cmd LC_LOAD_DYLIB
366 LOAD: cmdsize 48
367 LOAD: name /usr/lib/foo1.dylib (offset 24)
368 LOAD: current version 0.0.0
369 LOAD: compatibility version 0.0.0
370 LOAD: Load command 11
371 LOAD: cmd LC_LOAD_WEAK_DYLIB
372 LOAD: cmdsize 48
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/tools/llvm-objdump/X86/
Dmacho-private-headers.test5 // RUN: | FileCheck %s -check-prefix=LOAD
366 LOAD: Load command 10
367 LOAD: cmd LC_LOAD_DYLIB
368 LOAD: cmdsize 48
369 LOAD: name /usr/lib/foo1.dylib (offset 24)
370 LOAD: current version 0.0.0
371 LOAD: compatibility version 0.0.0
372 LOAD: Load command 11
373 LOAD: cmd LC_LOAD_WEAK_DYLIB
374 LOAD: cmdsize 48
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/GlobalISel/
Dx86-legalize-ptrtoint.mir48 …; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stac…
49 ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s1) = G_PTRTOINT [[LOAD]](p0)
77 …; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stac…
78 ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s8) = G_PTRTOINT [[LOAD]](p0)
104 …; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stac…
105 ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s16) = G_PTRTOINT [[LOAD]](p0)
131 …; CHECK: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stac…
132 ; CHECK: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[LOAD]](p0)
Dlegalize-memop-scalar.mir37 ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
43 ; X64: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
52 ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load 1)
58 ; X32: [[COPY:%[0-9]+]]:_(s8) = COPY [[LOAD]](s8)
95 ; X64: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[DEF]](p0) :: (load 8)
96 ; X64: G_STORE [[LOAD]](s64), [[DEF]](p0) :: (store 8)
99 ; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[DEF]](p0) :: (load 4, align 8)
103 ; X32: G_STORE [[LOAD]](s32), [[DEF]](p0) :: (store 4, align 8)
Dirtranslator-callingconv.ll13 …; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stac…
31 ; X32: G_STORE [[LOAD]](s8), [[GV]](p0) :: (store 1 into @a1_8bit)
34 ; X32: $al = COPY [[LOAD]](s8)
52 …; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stac…
59 ; X64: G_STORE [[LOAD]](s8), [[GV1]](p0) :: (store 1 into @a7_8bit)
79 …; X32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-sta…
97 ; X32: G_STORE [[LOAD]](s32), [[GV]](p0) :: (store 4 into @a1_32bit)
100 ; X32: $eax = COPY [[LOAD]](s32)
112 …; X64: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-sta…
119 ; X64: G_STORE [[LOAD]](s32), [[GV1]](p0) :: (store 4 into @a7_32bit)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepIICHVX.td135 InstrItinData <tc_35e92f8e, /*SLOT0,NOSLOT1,LOAD,VP*/
142 InstrItinData <tc_38208312, /*SLOT01,LOAD*/
178 InstrItinData <tc_4fd8566e, /*SLOT0,NOSLOT1,LOAD,VP*/
185 InstrItinData <tc_51cd3aab, /*SLOT01,LOAD*/
205 InstrItinData <tc_5cbf490b, /*SLOT01,LOAD,VA*/
211 InstrItinData <tc_63e3d94c, /*SLOT1,LOAD,VA*/
222 InstrItinData <tc_66bb62ea, /*SLOT1,LOAD,VA*/
260 InstrItinData <tc_77a4c701, /*SLOT01,LOAD*/
329 InstrItinData <tc_98733e9d, /*SLOT1,LOAD,VA_DV*/
346 InstrItinData <tc_9c267309, /*SLOT01,LOAD*/
[all …]
/external/swiftshader/third_party/subzero/tests_lit/asan_tests/
Derrors.ll8 ; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
11 ; RUN: %t.pexe -o %t && %t 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
16 ; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
19 ; RUN: %t.pexe -o %t && %t 1 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
24 ; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
27 ; RUN: %t.pexe -o %t && %t 1 2 2>&1 | FileCheck --check-prefix=LOCAL-LOAD %s
33 ; RUN: --check-prefix=GLOBAL-LOAD %s
37 ; RUN: --check-prefix=GLOBAL-LOAD %s
43 ; RUN: --check-prefix=GLOBAL-LOAD %s
47 ; RUN: --check-prefix=GLOBAL-LOAD %s
[all …]
/external/tensorflow/tensorflow/core/kernels/
Dsparse_matmul_op.cc277 #define LOAD(x) Eigen::internal::pload<Packet>(x); macro
412 const auto b = LOAD(inp); in MulAdd()
416 auto c1 = LOAD(*out); in MulAdd()
417 auto c2 = LOAD(*out + kNumOperands); in MulAdd()
432 auto c1 = LOAD(*out); in MulAdd3Way()
433 auto c2 = LOAD(*out + kNumOperands); in MulAdd3Way()
434 const auto b1 = LOAD(inp1); in MulAdd3Way()
438 const auto b2 = LOAD(inp2); in MulAdd3Way()
442 const auto b3 = LOAD(inp3); in MulAdd3Way()
465 auto c1 = LOAD(*out); in TwoMulAdd3Way()
[all …]

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