1; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -S \ 2; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=STORE -check-prefix=ALL 3; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -asan-instrument-reads=0 -S \ 4; RUN: | FileCheck %s -check-prefix=NOLOAD -check-prefix=STORE -check-prefix=ALL 5; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -asan-instrument-writes=0 -S \ 6; RUN: | FileCheck %s -check-prefix=LOAD -check-prefix=NOSTORE -check-prefix=ALL 7; RUN: opt < %s -asan -asan-instrumentation-with-call-threshold=0 -asan-instrument-reads=0 -asan-instrument-writes=0 -S \ 8; RUN: | FileCheck %s -check-prefix=NOLOAD -check-prefix=NOSTORE -check-prefix=ALL 9; Support ASan instrumentation for constant-mask llvm.masked.{load,store} 10 11target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" 12 13@v4f32 = global <4 x float>* zeroinitializer, align 8 14@v8i32 = global <8 x i32>* zeroinitializer, align 8 15@v4i64 = global <4 x i32*>* zeroinitializer, align 8 16 17;;;;;;;;;;;;;;;; STORE 18declare void @llvm.masked.store.v4f32.p0v4f32(<4 x float>, <4 x float>*, i32, <4 x i1>) argmemonly nounwind 19declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>) argmemonly nounwind 20declare void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*>, <4 x i32*>*, i32, <4 x i1>) argmemonly nounwind 21 22define void @store.v4f32.1110(<4 x float> %arg) sanitize_address { 23; ALL-LABEL: @store.v4f32.1110 24 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 25; NOSTORE-NOT: call void @__asan_store 26; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 27; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 28; STORE: call void @__asan_store4(i64 [[PGEP0]]) 29; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 30; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 31; STORE: call void @__asan_store4(i64 [[PGEP1]]) 32; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 33; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 34; STORE: call void @__asan_store4(i64 [[PGEP2]]) 35; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 false>) 36 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 true, i1 true, i1 false>) 37 ret void 38} 39 40define void @store.v8i32.10010110(<8 x i32> %arg) sanitize_address { 41; ALL-LABEL: @store.v8i32.10010110 42 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8 43; NOSTORE-NOT: call void @__asan_store 44; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0 45; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64 46; STORE: call void @__asan_store4(i64 [[PGEP0]]) 47; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 3 48; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP3]] to i64 49; STORE: call void @__asan_store4(i64 [[PGEP3]]) 50; STORE: [[GEP5:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 5 51; STORE: [[PGEP5:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP5]] to i64 52; STORE: call void @__asan_store4(i64 [[PGEP5]]) 53; STORE: [[GEP6:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 6 54; STORE: [[PGEP6:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP6]] to i64 55; STORE: call void @__asan_store4(i64 [[PGEP6]]) 56; STORE: tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>) 57 tail call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %arg, <8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 false>) 58 ret void 59} 60 61define void @store.v4i64.0001(<4 x i32*> %arg) sanitize_address { 62; ALL-LABEL: @store.v4i64.0001 63 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8 64; NOSTORE-NOT: call void @__asan_store 65; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3 66; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64 67; STORE: call void @__asan_store8(i64 [[PGEP3]]) 68; STORE: tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>) 69 tail call void @llvm.masked.store.v4p0i32.p0v4p0i32(<4 x i32*> %arg, <4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>) 70 ret void 71} 72 73define void @store.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address { 74; ALL-LABEL: @store.v4f32.variable 75 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 76; STORE: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0 77; STORE: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]] 78; STORE: <label>:[[THEN0]]: 79; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 80; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 81; STORE: call void @__asan_store4(i64 [[PGEP0]]) 82; STORE: br label %[[AFTER0]] 83; STORE: <label>:[[AFTER0]] 84 85; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1 86; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]] 87; STORE: <label>:[[THEN1]]: 88; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 89; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 90; STORE: call void @__asan_store4(i64 [[PGEP1]]) 91; STORE: br label %[[AFTER1]] 92; STORE: <label>:[[AFTER1]] 93 94; STORE: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2 95; STORE: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]] 96; STORE: <label>:[[THEN2]]: 97; STORE: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 98; STORE: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 99; STORE: call void @__asan_store4(i64 [[PGEP2]]) 100; STORE: br label %[[AFTER2]] 101; STORE: <label>:[[AFTER2]] 102 103; STORE: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3 104; STORE: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]] 105; STORE: <label>:[[THEN3]]: 106; STORE: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 107; STORE: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 108; STORE: call void @__asan_store4(i64 [[PGEP3]]) 109; STORE: br label %[[AFTER3]] 110; STORE: <label>:[[AFTER3]] 111 112; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask) 113 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> %mask) 114 ret void 115} 116 117;; Store using two masked.stores, which should instrument them both. 118define void @store.v4f32.1010.split(<4 x float> %arg) sanitize_address { 119; BOTH-LABEL: @store.v4f32.1010.split 120 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 121; STORE: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 122; STORE: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 123; STORE: call void @__asan_store4(i64 [[PGEP0]]) 124; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>) 125 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>) 126; STORE: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 127; STORE: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 128; STORE: call void @__asan_store4(i64 [[PGEP1]]) 129; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>) 130 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>) 131 ret void 132} 133 134;; Store using a masked.store after a full store. Shouldn't instrument the second one. 135define void @store.v4f32.0010.after.full.store(<4 x float> %arg) sanitize_address { 136; BOTH-LABEL: @store.v4f32.0010.after.full.store 137 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 138; STORE: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint <4 x float>* %p to i64 139; STORE: call void @__asan_store16(i64 [[PTRTOINT]]) 140; STORE: store <4 x float> %arg, <4 x float>* %p 141 store <4 x float> %arg, <4 x float>* %p 142; STORE-NOT: call void @__asan_store 143; STORE: tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>) 144 tail call void @llvm.masked.store.v4f32.p0v4f32(<4 x float> %arg, <4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 true, i1 false>) 145 ret void 146} 147 148;;;;;;;;;;;;;;;; LOAD 149declare <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>*, i32, <4 x i1>, <4 x float>) argmemonly nounwind 150declare <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>) argmemonly nounwind 151declare <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>*, i32, <4 x i1>, <4 x i32*>) argmemonly nounwind 152 153define <8 x i32> @load.v8i32.11100001(<8 x i32> %arg) sanitize_address { 154; ALL-LABEL: @load.v8i32.11100001 155 %p = load <8 x i32>*, <8 x i32>** @v8i32, align 8 156; NOLOAD-NOT: call void @__asan_load 157; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 0 158; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP0]] to i64 159; LOAD: call void @__asan_load4(i64 [[PGEP0]]) 160; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 1 161; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP1]] to i64 162; LOAD: call void @__asan_load4(i64 [[PGEP1]]) 163; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 2 164; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP2]] to i64 165; LOAD: call void @__asan_load4(i64 [[PGEP2]]) 166; LOAD: [[GEP7:%[0-9A-Za-z]+]] = getelementptr <8 x i32>, <8 x i32>* %p, i64 0, i64 7 167; LOAD: [[PGEP7:%[0-9A-Za-z]+]] = ptrtoint i32* [[GEP7]] to i64 168; LOAD: call void @__asan_load4(i64 [[PGEP7]]) 169; LOAD: tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> %arg) 170 %res = tail call <8 x i32> @llvm.masked.load.v8i32.p0v8i32(<8 x i32>* %p, i32 8, <8 x i1> <i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 true>, <8 x i32> %arg) 171 ret <8 x i32> %res 172} 173 174define <4 x float> @load.v4f32.1001(<4 x float> %arg) sanitize_address { 175; ALL-LABEL: @load.v4f32.1001 176 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 177; NOLOAD-NOT: call void @__asan_load 178; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 179; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 180; LOAD: call void @__asan_load4(i64 [[PGEP0]]) 181; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 182; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 183; LOAD: call void @__asan_load4(i64 [[PGEP3]]) 184; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %arg) 185 %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 true>, <4 x float> %arg) 186 ret <4 x float> %res 187} 188 189define <4 x i32*> @load.v4i64.0001(<4 x i32*> %arg) sanitize_address { 190; ALL-LABEL: @load.v4i64.0001 191 %p = load <4 x i32*>*, <4 x i32*>** @v4i64, align 8 192; NOLOAD-NOT: call void @__asan_load 193; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x i32*>, <4 x i32*>* %p, i64 0, i64 3 194; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint i32** [[GEP3]] to i64 195; LOAD: call void @__asan_load8(i64 [[PGEP3]]) 196; LOAD: tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32*> %arg) 197 %res = tail call <4 x i32*> @llvm.masked.load.v4p0i32.p0v4p0i32(<4 x i32*>* %p, i32 8, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x i32*> %arg) 198 ret <4 x i32*> %res 199} 200 201define <4 x float> @load.v4f32.variable(<4 x float> %arg, <4 x i1> %mask) sanitize_address { 202; ALL-LABEL: @load.v4f32.variable 203 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 204; LOAD: [[MASK0:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 0 205; LOAD: br i1 [[MASK0]], label %[[THEN0:[0-9A-Za-z]+]], label %[[AFTER0:[0-9A-Za-z]+]] 206; LOAD: <label>:[[THEN0]]: 207; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 208; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 209; LOAD: call void @__asan_load4(i64 [[PGEP0]]) 210; LOAD: br label %[[AFTER0]] 211; LOAD: <label>:[[AFTER0]] 212 213; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1 214; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]] 215; LOAD: <label>:[[THEN1]]: 216; LOAD: [[GEP1:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 1 217; LOAD: [[PGEP1:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP1]] to i64 218; LOAD: call void @__asan_load4(i64 [[PGEP1]]) 219; LOAD: br label %[[AFTER1]] 220; LOAD: <label>:[[AFTER1]] 221 222; LOAD: [[MASK2:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 2 223; LOAD: br i1 [[MASK2]], label %[[THEN2:[0-9A-Za-z]+]], label %[[AFTER2:[0-9A-Za-z]+]] 224; LOAD: <label>:[[THEN2]]: 225; LOAD: [[GEP2:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 2 226; LOAD: [[PGEP2:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP2]] to i64 227; LOAD: call void @__asan_load4(i64 [[PGEP2]]) 228; LOAD: br label %[[AFTER2]] 229; LOAD: <label>:[[AFTER2]] 230 231; LOAD: [[MASK3:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 3 232; LOAD: br i1 [[MASK3]], label %[[THEN3:[0-9A-Za-z]+]], label %[[AFTER3:[0-9A-Za-z]+]] 233; LOAD: <label>:[[THEN3]]: 234; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 235; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 236; LOAD: call void @__asan_load4(i64 [[PGEP3]]) 237; LOAD: br label %[[AFTER3]] 238; LOAD: <label>:[[AFTER3]] 239 240; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg) 241 %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> %mask, <4 x float> %arg) 242 ret <4 x float> %res 243} 244 245;; Load using two masked.loads, which should instrument them both. 246define <4 x float> @load.v4f32.1001.split(<4 x float> %arg) sanitize_address { 247; BOTH-LABEL: @load.v4f32.1001 248 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 249; LOAD: [[GEP0:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 0 250; LOAD: [[PGEP0:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP0]] to i64 251; LOAD: call void @__asan_load4(i64 [[PGEP0]]) 252; LOAD: %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %arg) 253 %res = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %arg) 254; LOAD: [[GEP3:%[0-9A-Za-z]+]] = getelementptr <4 x float>, <4 x float>* %p, i64 0, i64 3 255; LOAD: [[PGEP3:%[0-9A-Za-z]+]] = ptrtoint float* [[GEP3]] to i64 256; LOAD: call void @__asan_load4(i64 [[PGEP3]]) 257; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %res) 258 %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %res) 259 ret <4 x float> %res2 260} 261 262;; Load using a masked.load after a full load. Shouldn't instrument the second one. 263define <4 x float> @load.v4f32.1001.after.full.load(<4 x float> %arg) sanitize_address { 264; BOTH-LABEL: @load.v4f32.1001.after.full.load 265 %p = load <4 x float>*, <4 x float>** @v4f32, align 8 266; LOAD: [[PTRTOINT:%[0-9A-Za-z]+]] = ptrtoint <4 x float>* %p to i64 267; LOAD: call void @__asan_load16(i64 [[PTRTOINT]]) 268; LOAD: %res = load <4 x float>, <4 x float>* %p 269 %res = load <4 x float>, <4 x float>* %p 270; LOAD-NOT: call void @__asan_load 271; LOAD: tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %arg) 272 %res2 = tail call <4 x float> @llvm.masked.load.v4f32.p0v4f32(<4 x float>* %p, i32 4, <4 x i1> <i1 false, i1 false, i1 false, i1 true>, <4 x float> %arg) 273 ret <4 x float> %res2 274} 275