Searched refs:LoSR (Results 1 – 2 of 2) sorted by relevance
/external/llvm/lib/Target/Hexagon/ |
D | HexagonSplitDouble.cpp | 765 unsigned LoSR = subreg_loreg; in splitShift() local 771 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 796 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 799 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 802 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift() 808 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift() 830 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)); in splitShift() 842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 848 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)) in splitShift() 886 unsigned LoSR = subreg_loreg; in splitAslOr() local [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonSplitDouble.cpp | 806 unsigned LoSR = isub_lo; in splitShift() local 812 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 837 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 840 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 843 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift() 849 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR) in splitShift() 871 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)); in splitShift() 883 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR); in splitShift() 889 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR)) in splitShift() 927 unsigned LoSR = isub_lo; in splitAslOr() local [all …]
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