| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1616 unsigned LoadOpc; in expandLoadVec2() local
1620 LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; in expandLoadVec2()
1622 LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; in expandLoadVec2()
1624 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
1631 LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; in expandLoadVec2()
1633 LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; in expandLoadVec2()
1635 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
1702 unsigned LoadOpc; in expandLoadVec() local
1705 LoadOpc = !Is128B ? Hexagon::V6_vL32b_ai : Hexagon::V6_vL32b_ai_128B; in expandLoadVec()
1707 LoadOpc = !Is128B ? Hexagon::V6_vL32Ub_ai : Hexagon::V6_vL32Ub_ai_128B; in expandLoadVec()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 1774 unsigned LoadOpc; in expandLoadVec2() local
1777 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1779 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo) in expandLoadVec2()
1785 LoadOpc = NeedAlign <= MinAlign(HasAlign, Size) ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1787 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi) in expandLoadVec2()
1841 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec() local
1843 BuildMI(B, It, DL, HII.get(LoadOpc), DstR) in expandLoadVec()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 39 unsigned LoadImmOpc, unsigned LoadOpc) const;
|
| D | ARMBaseInstrInfo.cpp | 4121 unsigned LoadOpc) const { in expandLoadStackGuardBase()
4133 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
4142 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 976 unsigned LoadOpc = PPC::LFD; in PPCMoveToFPReg() local
980 LoadOpc = PPC::LFIWZX; in PPCMoveToFPReg()
983 LoadOpc = PPC::LFIWAX; in PPCMoveToFPReg()
990 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc)) in PPCMoveToFPReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 44 unsigned LoadImmOpc, unsigned LoadOpc) const;
|
| D | ARMBaseInstrInfo.cpp | 4510 unsigned LoadOpc) const { in expandLoadStackGuardBase()
4525 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
4535 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg); in expandLoadStackGuardBase()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCFastISel.cpp | 1035 unsigned LoadOpc = PPC::LFD; in PPCMoveToFPReg() local
1039 LoadOpc = PPC::LFIWZX; in PPCMoveToFPReg()
1042 LoadOpc = PPC::LFIWAX; in PPCMoveToFPReg()
1049 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc)) in PPCMoveToFPReg()
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 10902 unsigned LoadOpc, in EmitAtomicBitwiseWithCustomInserter() argument
10958 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); in EmitAtomicBitwiseWithCustomInserter()
11026 const unsigned LoadOpc = X86::MOV32rm; in EmitAtomicBit6432WithCustomInserter() local
11075 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); in EmitAtomicBit6432WithCustomInserter()
11079 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); in EmitAtomicBit6432WithCustomInserter()
|