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Searched refs:MASK1 (Results 1 – 9 of 9) sorted by relevance

/external/syzkaller/pkg/ifuzz/gen/
Dall-enc-instructions.txt27345 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
27359 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
27373 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
27389 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
27403 OPERANDS: REG0=ZMM_R3():w:zf32:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
27417 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f32:TXT=BCASTSTR
27561 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
27575 OPERANDS: REG0=ZMM_R3():w:zf64:TXT=SAESTR REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
27589 OPERANDS: REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR MEM0:r:vv:f64:TXT=BCASTSTR
27605 OPERANDS: REG0=ZMM_R3():w:zf32 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf32
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/external/lua/src/
Dlopcodes.h80 #define MASK1(n,p) ((~((~(Instruction)0)<<(n)))<<(p)) macro
83 #define MASK0(n,p) (~MASK1(n,p))
89 #define GET_OPCODE(i) (cast(OpCode, ((i)>>POS_OP) & MASK1(SIZE_OP,0)))
91 ((cast(Instruction, o)<<POS_OP)&MASK1(SIZE_OP,POS_OP))))
93 #define getarg(i,pos,size) (cast(int, ((i)>>pos) & MASK1(size,0)))
95 ((cast(Instruction, v)<<pos)&MASK1(size,pos))))
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/
Dunal-altivec.ll35 ; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
39 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
/external/llvm/test/CodeGen/PowerPC/
Dunal-altivec.ll36 ; CHECK-DAG: lvsl [[MASK1:[0-9]+]], [[B1:[0-9]+]], [[C0]]
44 ; CHECK-DAG: vperm [[R1:[0-9]+]], [[LD1]], [[LD2]], [[MASK1]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dicmp-logical.ll6 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
7 ; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 0
20 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
21 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
34 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
35 ; CHECK-NEXT: [[TST1:%.*]] = icmp ne i32 [[MASK1]], 7
48 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 7
49 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 7
120 ; CHECK-NEXT: [[MASK1:%.*]] = and i32 [[A:%.*]], 15
121 ; CHECK-NEXT: [[TST1:%.*]] = icmp eq i32 [[MASK1]], 0
/external/mesa3d/src/mesa/program/
Dprogram_lexer.l377 return MASK1;
434 return_token_or_DOT(require_ARB_fp, MASK1);
445 return MASK1;
Dprogram_parse.y192 %token <swiz_mask> MASK4 MASK3 MASK2 MASK1 SWIZZLE
933 addrComponent: MASK1
944 addrWriteMask: MASK1
956 scalarSuffix: MASK1;
958 swizzleSuffix: MASK1
964 optionalMask: MASK4 | MASK3 | MASK2 | MASK1
/external/swiftshader/third_party/llvm-7.0/llvm/test/Instrumentation/AddressSanitizer/
Dasan-masked-load-store.ll85 ; STORE: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
86 ; STORE: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
213 ; LOAD: [[MASK1:%[0-9A-Za-z]+]] = extractelement <4 x i1> %mask, i64 1
214 ; LOAD: br i1 [[MASK1]], label %[[THEN1:[0-9A-Za-z]+]], label %[[AFTER1:[0-9A-Za-z]+]]
/external/llvm/test/CodeGen/AMDGPU/
Duniform-cfg.ll310 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]
340 ; SI: s_xor_b64 [[MASK1:s\[[0-9]+:[0-9]+\]]], exec, [[MASK]]