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Searched refs:MCII (Results 1 – 25 of 134) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.h45 MCInstrInfo const &MCII; variable
52 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst);
53 PacketIterator(MCInstrInfo const &MCII, MCInst const &Inst, std::nullptr_t);
81 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
86 bundleInstructions(MCInstrInfo const &MCII, MCInst const &MCI);
93 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
100 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
108 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
112 unsigned getMemAccessSize(MCInstrInfo const &MCII, MCInst const &MCI);
115 unsigned getAddrMode(MCInstrInfo const &MCII, MCInst const &MCI);
[all …]
DHexagonMCInstrInfo.cpp40 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
42 : MCII(MCII), BundleCurrent(Inst.begin() + in PacketIterator()
46 Hexagon::PacketIterator::PacketIterator(MCInstrInfo const &MCII, in PacketIterator() argument
48 : MCII(MCII), BundleCurrent(Inst.end()), BundleEnd(Inst.end()), in PacketIterator()
64 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in operator ++()
89 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
93 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
97 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); in addConstExtender()
104 HexagonMCInstrInfo::bundleInstructions(MCInstrInfo const &MCII, in bundleInstructions() argument
107 return make_range(Hexagon::PacketIterator(MCII, MCI), in bundleInstructions()
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DHexagonMCChecker.cpp58 if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) { in init()
70 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in initReg()
73 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in initReg()
76 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in initReg()
89 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
122 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
161 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && in init()
165 else if (i == 0 && HexagonMCInstrInfo::getType(MCII, MCI) == in init()
173 else if (i <= 1 && HexagonMCInstrInfo::hasNewValue2(MCII, MCI)) in init()
183 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in init()
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DHexagonMCShuffler.cpp41 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode()) in init()
43 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo()); in init()
46 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
61 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
65 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
68 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, MI)); in init()
74 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, AddMI)); in init()
107 MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
109 HexagonMCShuffler MCS(Context, Fatal, MCII, STI, MCB); in HexagonMCShuffle()
134 llvm::HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII, in HexagonMCShuffle() argument
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DHexagonShuffler.cpp144 MCInstrInfo const &MCII, unsigned s, in HexagonCVIResource() argument
147 unsigned T = HexagonMCInstrInfo::getType(MCII, *id); in HexagonCVIResource()
154 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
155 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
199 MCInstrInfo const &MCII, in HexagonShuffler() argument
201 : Context(Context), MCII(MCII), STI(STI), ReportErrors(ReportErrors) { in HexagonShuffler()
213 HexagonInstr PI(&TUL, MCII, &ID, Extender, S); in append()
229 if (HexagonMCInstrInfo::isRestrictSlot1AOK(MCII, Inst)) { in restrictSlot1AOK()
237 unsigned Type = HexagonMCInstrInfo::getType(MCII, Inst); in restrictSlot1AOK()
260 if (HexagonMCInstrInfo::isRestrictNoSlot1Store(MCII, Inst)) { in restrictNoSlot1Store()
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DHexagonMCShuffler.h32 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, in HexagonMCShuffler() argument
34 : HexagonShuffler(Context, Fatal, MCII, STI) { in HexagonMCShuffler()
38 HexagonMCShuffler(MCContext &Context, bool Fatal, MCInstrInfo const &MCII, in HexagonMCShuffler() argument
41 : HexagonShuffler(Context, Fatal, MCII, STI) { in HexagonMCShuffler()
57 bool HexagonMCShuffle(MCContext &Context, bool Fatal, MCInstrInfo const &MCII,
59 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
62 bool HexagonMCShuffle(MCContext &Context, MCInstrInfo const &MCII,
DHexagonMCCodeEmitter.cpp344 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
416 assert(!HexagonMCInstrInfo::getDesc(MCII, MI).isPseudo() && in EncodeSingleInstruction()
419 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
428 << HexagonMCInstrInfo::getName(MCII, MI) << "'\n"); in EncodeSingleInstruction()
471 MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, in getFixupNoBits() argument
473 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); in getFixupNoBits()
474 unsigned InsnType = HexagonMCInstrInfo::getType(MCII, MI); in getFixupNoBits()
485 const MCInstrDesc &NextD = HexagonMCInstrInfo::getDesc(MCII, NextI); in getFixupNoBits()
487 HexagonMCInstrInfo::getType(MCII, NextI) == HexagonII::TypeCR) in getFixupNoBits()
593 bool InstExtendable = HexagonMCInstrInfo::isExtendable(MCII, MI) || in getExprOpValue()
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DHexagonAsmBackend.cpp45 std::unique_ptr <MCInstrInfo> MCII; member in __anon6dff73310111::HexagonAsmBackend
66 MCII(T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
540 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
543 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
544 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ && in isInstRelaxable()
546 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNCJ && in isInstRelaxable()
548 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
550 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
553 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
675 *MCII, CrntHMI, in relaxInstruction()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCInstrInfo.h56 void addConstExtender(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
66 bool canonicalizePacket(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
71 void clampExtended(MCInstrInfo const &MCII, MCContext &Context, MCInst &MCI);
77 void extendIfNeeded(MCContext &Context, MCInstrInfo const &MCII, MCInst &MCB,
83 MCInst deriveExtender(MCInstrInfo const &MCII, MCInst const &Inst,
93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
97 unsigned getBitCount(MCInstrInfo const &MCII, MCInst const &MCI);
100 unsigned short getCExtOpNum(MCInstrInfo const &MCII, MCInst const &MCI);
102 MCInstrDesc const &getDesc(MCInstrInfo const &MCII, MCInst const &MCI);
108 SmallVector<DuplexCandidate, 8> getDuplexPossibilties(MCInstrInfo const &MCII,
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DHexagonMCInstrInfo.cpp32 MCInstrInfo const &MCII, MCInst &MCB, in addConstExtender() argument
36 MCI.getOperand(HexagonMCInstrInfo::getExtendableOp(MCII, MCI)); in addConstExtender()
40 new (Context) MCInst(HexagonMCInstrInfo::deriveExtender(MCII, MCI, exOp)); in addConstExtender()
58 bool HexagonMCInstrInfo::canonicalizePacket(MCInstrInfo const &MCII, in canonicalizePacket() argument
65 HexagonMCInstrInfo::tryCompound(MCII, Context, MCB); in canonicalizePacket()
70 HexagonMCShuffle(MCII, STI, MCB); in canonicalizePacket()
76 possibleDuplexes = HexagonMCInstrInfo::getDuplexPossibilties(MCII, MCB); in canonicalizePacket()
77 HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes); in canonicalizePacket()
86 HexagonMCShuffle(MCII, STI, MCB); in canonicalizePacket()
90 void HexagonMCInstrInfo::clampExtended(MCInstrInfo const &MCII, in clampExtended() argument
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DHexagonMCChecker.cpp57 const MCInstrDesc& MCID = HexagonMCInstrInfo::getDesc(MCII, MCI); in init()
66 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in init()
69 isTrue = HexagonMCInstrInfo::isPredicatedTrue(MCII, MCI); in init()
72 if (HexagonMCInstrInfo::isPredicatedNew(MCII, MCI)) in init()
108 HexagonMCInstrInfo::isPredicateLate(MCII, MCI)) in init()
149 else if (HexagonMCInstrInfo::isPredicateLate(MCII, MCI) && isPredicateRegister(*SRI)) in init()
152 … else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_CUR_LD) in init()
157 … else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCVI_VM_TMP_LD) in init()
164 else if (i <= 1 && llvm::HexagonMCInstrInfo::hasNewValue2(MCII, MCI) ) in init()
174 if (HexagonMCInstrInfo::hasNewValue(MCII, MCI)) { in init()
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DHexagonShuffler.cpp122 MCInstrInfo const &MCII, unsigned s, in HexagonCVIResource() argument
125 unsigned T = HexagonMCInstrInfo::getType(MCII, *id); in HexagonCVIResource()
132 setLoad(HexagonMCInstrInfo::getDesc(MCII, *id).mayLoad()); in HexagonCVIResource()
133 setStore(HexagonMCInstrInfo::getDesc(MCII, *id).mayStore()); in HexagonCVIResource()
144 HexagonShuffler::HexagonShuffler(MCInstrInfo const &MCII, in HexagonShuffler() argument
146 : MCII(MCII), STI(STI) { in HexagonShuffler()
159 HexagonInstr PI(&TUL, MCII, ID, Extender, S, X); in append()
197 if (HexagonMCInstrInfo::isSolo(MCII, *ID)) in check()
199 else if (HexagonMCInstrInfo::isSoloAX(MCII, *ID)) in check()
201 else if (HexagonMCInstrInfo::isSoloAin1(MCII, *ID)) in check()
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DHexagonMCShuffler.cpp36 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
40 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), in init()
55 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), in init()
60 assert(!HexagonMCInstrInfo::getDesc(MCII, *I.getInst()).isPseudo()); in init()
63 append(MI, Extender, HexagonMCInstrInfo::getUnits(MCII, STI, *MI), in init()
70 append(AddMI, nullptr, HexagonMCInstrInfo::getUnits(MCII, STI, *AddMI), in init()
101 bool llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
103 HexagonMCShuffler MCS(MCII, STI, MCB); in HexagonMCShuffle()
151 llvm::HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffle() argument
179 HexagonMCShuffler MCS(MCII, STI, Attempt); // copy packet to the shuffler in HexagonMCShuffle()
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DHexagonMCShuffler.h30 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, in HexagonMCShuffler() argument
32 : HexagonShuffler(MCII, STI) { in HexagonMCShuffler()
35 HexagonMCShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
38 : HexagonShuffler(MCII, STI) { in HexagonShuffler() argument
56 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
58 bool HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
60 unsigned HexagonMCShuffle(MCInstrInfo const &MCII, MCSubtargetInfo const &STI,
DHexagonMCCodeEmitter.cpp37 : MCT(aMCT), MCII(aMII), Addend(new unsigned(0)), in HexagonMCCodeEmitter()
43 bool Duplex = HexagonMCInstrInfo::isDuplex(MCII, MCI); in parseBits()
120 assert(!HexagonMCInstrInfo::getDesc(MCII, HMB).isPseudo() && in EncodeSingleInstruction()
123 " `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'" in EncodeSingleInstruction()
126 if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) { in EncodeSingleInstruction()
136 if (HexagonMCInstrInfo::isNewValue(MCII, HMB)) { in EncodeSingleInstruction()
139 HMB.getOperand(HexagonMCInstrInfo::getNewValueOp(MCII, HMB)); in EncodeSingleInstruction()
153 if (HexagonMCInstrInfo::isVector(MCII, Inst)) in EncodeSingleInstruction()
157 HexagonMCInstrInfo::hasNewValue(MCII, Inst) in EncodeSingleInstruction()
158 ? HexagonMCInstrInfo::getNewValueOperand(MCII, Inst).getReg() in EncodeSingleInstruction()
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DHexagonAsmBackend.cpp45 std::unique_ptr <MCInstrInfo> MCII; member in __anonb2f861f90111::HexagonAsmBackend
63 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *), in HexagonAsmBackend()
523 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI); in isInstRelaxable()
526 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ || in isInstRelaxable()
527 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == in isInstRelaxable()
530 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV && in isInstRelaxable()
532 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR && in isInstRelaxable()
534 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI)) { in isInstRelaxable()
537 HMI.getOperand(HexagonMCInstrInfo::getExtendableOp(*MCII, HMI)); in isInstRelaxable()
656 *MCII, CrntHMI, in relaxInstruction()
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/external/llvm/lib/Target/WebAssembly/MCTargetDesc/
DWebAssemblyMCCodeEmitter.cpp36 const MCInstrInfo &MCII; member in __anonc8578c7d0111::WebAssemblyMCCodeEmitter
48 WebAssemblyMCCodeEmitter(const MCInstrInfo &mcii) : MCII(mcii) {} in WebAssemblyMCCodeEmitter()
52 MCCodeEmitter *llvm::createWebAssemblyMCCodeEmitter(const MCInstrInfo &MCII) { in createWebAssemblyMCCodeEmitter() argument
53 return new WebAssemblyMCCodeEmitter(MCII); in createWebAssemblyMCCodeEmitter()
63 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
78 (1 + MCII.get(MI.getOpcode()).isVariadic() + i) * sizeof(uint64_t), in encodeInstruction()
/external/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp34 std::unique_ptr<const MCInstrInfo> MCII; member in __anond6fd61fe0111::WebAssemblyDisassembler
43 std::unique_ptr<const MCInstrInfo> MCII) in WebAssemblyDisassembler() argument
44 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {} in WebAssemblyDisassembler()
51 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo()); in createWebAssemblyDisassembler() local
52 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII)); in createWebAssemblyDisassembler()
79 const MCInstrDesc &Desc = MCII->get(Opcode); in getInstruction()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp32 const MCInstrInfo &MCII; member in __anona8da455f0111::MipsMCCodeEmitter
38 : MCII(mcii), STI(sti) {} in MipsMCCodeEmitter()
48 MCCodeEmitter *llvm::createMipsMCCodeEmitter(const MCInstrInfo &MCII, in createMipsMCCodeEmitter() argument
51 return new MipsMCCodeEmitter(MCII, STI, Ctx); in createMipsMCCodeEmitter()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp34 const MCInstrInfo &MCII; member in __anon065090e90111::BPFMCCodeEmitter
41 : MCII(mcii), MRI(mri), IsLittleEndian(IsLittleEndian) {} in BPFMCCodeEmitter()
74 MCCodeEmitter *llvm::createBPFMCCodeEmitter(const MCInstrInfo &MCII, in createBPFMCCodeEmitter() argument
77 return new BPFMCCodeEmitter(MCII, MRI, true); in createBPFMCCodeEmitter()
80 MCCodeEmitter *llvm::createBPFbeMCCodeEmitter(const MCInstrInfo &MCII, in createBPFbeMCCodeEmitter() argument
83 return new BPFMCCodeEmitter(MCII, MRI, false); in createBPFbeMCCodeEmitter()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/Disassembler/
DWebAssemblyDisassembler.cpp41 std::unique_ptr<const MCInstrInfo> MCII; member in __anon9b1559360111::WebAssemblyDisassembler
50 std::unique_ptr<const MCInstrInfo> MCII) in WebAssemblyDisassembler() argument
51 : MCDisassembler(STI, Ctx), MCII(std::move(MCII)) {} in WebAssemblyDisassembler()
58 std::unique_ptr<const MCInstrInfo> MCII(T.createMCInstrInfo()); in createWebAssemblyDisassembler() local
59 return new WebAssemblyDisassembler(STI, Ctx, std::move(MCII)); in createWebAssemblyDisassembler()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/MCTargetDesc/
DRISCVMCCodeEmitter.cpp44 MCInstrInfo const &MCII; member in __anon91b54a270111::RISCVMCCodeEmitter
47 RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII) in RISCVMCCodeEmitter() argument
48 : Ctx(ctx), MCII(MCII) {} in RISCVMCCodeEmitter()
82 MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII, in createRISCVMCCodeEmitter() argument
85 return new RISCVMCCodeEmitter(Ctx, MCII); in createRISCVMCCodeEmitter()
131 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
196 MCInstrDesc const &Desc = MCII.get(MI.getOpcode()); in getImmOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/Disassembler/
DHexagonDisassembler.cpp46 std::unique_ptr<MCInstrInfo const> const MCII; member in __anon2e59ca4e0111::HexagonDisassembler
51 MCInstrInfo const *MCII) in HexagonDisassembler() argument
52 : MCDisassembler(STI, Ctx), MCII(MCII), CurrentBundle(new MCInst *), in HexagonDisassembler()
68 MCInstrInfo MCII = *Disassembler.MCII; in fullValue() local
70 MI.size() != HexagonMCInstrInfo::getExtendableOp(MCII, MI)) in fullValue()
72 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI); in fullValue()
243 HexagonMCChecker Checker(getContext(), *MCII, STI, MI, in getInstruction()
510 if (HexagonMCInstrInfo::isNewValue(*MCII, MI)) { in getSingleInstruction()
511 unsigned OpIndex = HexagonMCInstrInfo::getNewValueOp(*MCII, MI); in getSingleInstruction()
521 bool Vector = HexagonMCInstrInfo::isVector(*MCII, MI); in getSingleInstruction()
[all …]
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp37 const MCInstrInfo &MCII; member in __anon894aee870111::R600MCCodeEmitter
42 : MCII(mcii), MRI(mri) { } in R600MCCodeEmitter()
80 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
83 return new R600MCCodeEmitter(MCII, MRI); in createR600MCCodeEmitter()
89 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
160 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DR600MCCodeEmitter.cpp40 const MCInstrInfo &MCII; member in __anon1a98b8bf0111::R600MCCodeEmitter
44 : MRI(mri), MCII(mcii) {} in R600MCCodeEmitter()
93 MCCodeEmitter *llvm::createR600MCCodeEmitter(const MCInstrInfo &MCII, in createR600MCCodeEmitter() argument
96 return new R600MCCodeEmitter(MCII, MRI); in createR600MCCodeEmitter()
105 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in encodeInstruction()
176 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags)) in getMachineOpValue()

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