| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | load.ll | 21 ; MIPS32-NEXT: # <MCOperand Reg:1>
22 ; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
24 ; MIPS32-NEXT: # <MCOperand Reg:19>>
26 ; MIPS32-NEXT: # <MCOperand Reg:321>
27 ; MIPS32-NEXT: # <MCOperand Reg:1>
28 ; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
33 ; MMR3-NEXT: # <MCOperand Reg:1>
34 ; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
36 ; MMR3-NEXT: # <MCOperand Reg:19>>
38 ; MMR3-NEXT: # <MCOperand Reg:321>
[all …]
|
| D | store.ll | 20 ; MIPS32-NEXT: # <MCOperand Reg:1>
21 ; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
23 ; MIPS32-NEXT: # <MCOperand Reg:19>>
25 ; MIPS32-NEXT: # <MCOperand Reg:22>
26 ; MIPS32-NEXT: # <MCOperand Reg:1>
27 ; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
32 ; MMR3-NEXT: # <MCOperand Reg:1>
33 ; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
35 ; MMR3-NEXT: # <MCOperand Reg:19>>
37 ; MMR3-NEXT: # <MCOperand Reg:22>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Lanai/ |
| D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
|
| D | conditional_inst.s | 10 ! CHECK-NEXT: <MCOperand Reg:12>>
16 ! CHECK-NEXT: <MCOperand Imm:4660>
22 ! CHECK-NEXT: <MCOperand Imm:2000>
23 ! CHECK-NEXT: <MCOperand Imm:13>
30 ! CHECK-NEXT: <MCOperand Expr:(jump1)>
31 ! CHECK-NEXT: <MCOperand Imm:13>
37 ! CHECK-NEXT: <MCOperand Expr:(jump2)>
38 ! CHECK-NEXT: <MCOperand Imm:10>
46 ! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
52 ! CHECK-NEXT: <MCOperand Reg:26>
[all …]
|
| /external/llvm/test/MC/Lanai/ |
| D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13>
11 ! CHECK-NEXT: <MCOperand Reg:14>
12 ! CHECK-NEXT: <MCOperand Imm:0>
13 ! CHECK-NEXT: <MCOperand Imm:0>
18 ! CHECK-NEXT: <MCOperand Reg:13>
19 ! CHECK-NEXT: <MCOperand Reg:13>
20 ! CHECK-NEXT: <MCOperand Imm:0>
21 ! CHECK-NEXT: <MCOperand Imm:0>
26 ! CHECK-NEXT: <MCOperand Reg:13>
27 ! CHECK-NEXT: <MCOperand Reg:14>
[all …]
|
| D | conditional_inst.s | 10 ! CHECK-NEXT: <MCOperand Reg:12>>
16 ! CHECK-NEXT: <MCOperand Imm:4660>
22 ! CHECK-NEXT: <MCOperand Imm:2000>
23 ! CHECK-NEXT: <MCOperand Imm:13>
30 ! CHECK-NEXT: <MCOperand Expr:(jump1)>
31 ! CHECK-NEXT: <MCOperand Imm:13>
37 ! CHECK-NEXT: <MCOperand Expr:(jump2)>
38 ! CHECK-NEXT: <MCOperand Imm:10>
46 ! CHECK-NEXT: <MCOperand Expr:(.Ltmp0)>
52 ! CHECK-NEXT: <MCOperand Reg:26>
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.h | 33 class MCOperand; variable
62 MCOperand createRegOperand(unsigned int RegId) const;
63 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
64 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
66 MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
74 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
75 MCOperand decodeOperand_VS_32(unsigned Val) const;
76 MCOperand decodeOperand_VS_64(unsigned Val) const;
77 MCOperand decodeOperand_VS_128(unsigned Val) const;
78 MCOperand decodeOperand_VSrc16(unsigned Val) const;
[all …]
|
| D | AMDGPUDisassembler.cpp | 58 addOperand(MCInst &Inst, const MCOperand& Opnd) { in addOperand()
65 static int insertNamedMCOperand(MCInst &MI, const MCOperand &Op, in insertNamedMCOperand()
85 return addOperand(Inst, MCOperand::createImm(Imm)); in decodeSoppBrTarget()
251 insertNamedMCOperand(MI, MCOperand::createImm(0), in getInstruction()
273 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp); in convertSDWAInst()
282 insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod); in convertSDWAInst()
364 MI.getOperand(VDataIdx) = MCOperand::createReg(NewVdata); in convertMIMGInst()
368 MI.getOperand(VDstIdx) = MCOperand::createReg(NewVdata); in convertMIMGInst()
380 MCOperand AMDGPUDisassembler::errOperand(unsigned V, in errOperand()
386 return MCOperand(); in errOperand()
[all …]
|
| /external/llvm/lib/Target/AMDGPU/Disassembler/ |
| D | AMDGPUDisassembler.h | 26 class MCOperand; variable
46 MCOperand createRegOperand(unsigned int RegId) const;
47 MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
48 MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
50 MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
57 MCOperand decodeOperand_VGPR_32(unsigned Val) const;
58 MCOperand decodeOperand_VS_32(unsigned Val) const;
59 MCOperand decodeOperand_VS_64(unsigned Val) const;
61 MCOperand decodeOperand_VReg_64(unsigned Val) const;
62 MCOperand decodeOperand_VReg_96(unsigned Val) const;
[all …]
|
| D | AMDGPUDisassembler.cpp | 44 addOperand(MCInst &Inst, const MCOperand& Opnd) { in addOperand()
169 MCOperand AMDGPUDisassembler::errOperand(unsigned V, in errOperand()
175 return MCOperand(); in errOperand()
179 MCOperand AMDGPUDisassembler::createRegOperand(unsigned int RegId) const { in createRegOperand()
180 return MCOperand::createReg(RegId); in createRegOperand()
184 MCOperand AMDGPUDisassembler::createRegOperand(unsigned RegClassID, in createRegOperand()
194 MCOperand AMDGPUDisassembler::createSRegOperand(unsigned SRegClassID, in createSRegOperand()
229 MCOperand AMDGPUDisassembler::decodeOperand_VS_32(unsigned Val) const { in decodeOperand_VS_32()
233 MCOperand AMDGPUDisassembler::decodeOperand_VS_64(unsigned Val) const { in decodeOperand_VS_64()
237 MCOperand AMDGPUDisassembler::decodeOperand_VGPR_32(unsigned Val) const { in decodeOperand_VGPR_32()
[all …]
|
| /external/capstone/ |
| D | MCInst.h | 29 typedef struct MCOperand MCOperand; typedef
33 struct MCOperand { struct
49 bool MCOperand_isValid(const MCOperand *op); argument
51 bool MCOperand_isReg(const MCOperand *op);
53 bool MCOperand_isImm(const MCOperand *op);
55 bool MCOperand_isFPImm(const MCOperand *op);
57 bool MCOperand_isInst(const MCOperand *op);
60 unsigned MCOperand_getReg(const MCOperand *op);
63 void MCOperand_setReg(MCOperand *op, unsigned Reg);
65 int64_t MCOperand_getImm(MCOperand *op);
[all …]
|
| D | MCInst.c | 32 void MCInst_insert0(MCInst *inst, int index, MCOperand *Op) in MCInst_insert0()
64 MCOperand *MCInst_getOperand(MCInst *inst, unsigned i) in MCInst_getOperand()
75 void MCInst_addOperand2(MCInst *inst, MCOperand *Op) in MCInst_addOperand2()
82 void MCOperand_Init(MCOperand *op) in MCOperand_Init()
88 bool MCOperand_isValid(const MCOperand *op) in MCOperand_isValid()
93 bool MCOperand_isReg(const MCOperand *op) in MCOperand_isReg()
98 bool MCOperand_isImm(const MCOperand *op) in MCOperand_isImm()
103 bool MCOperand_isFPImm(const MCOperand *op) in MCOperand_isFPImm()
109 unsigned MCOperand_getReg(const MCOperand *op) in MCOperand_getReg()
115 void MCOperand_setReg(MCOperand *op, unsigned Reg) in MCOperand_setReg()
[all …]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMAsmPrinter.cpp | 984 BrInst.addOperand(MCOperand::CreateExpr(MBBSymbolExpr)); in EmitJump2Table()
985 BrInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitJump2Table()
986 BrInst.addOperand(MCOperand::CreateReg(0)); in EmitJump2Table()
1031 Inst.addOperand(MCOperand::CreateReg(Dest)); in populateADROperands()
1032 Inst.addOperand(MCOperand::CreateExpr(SymbolExpr)); in populateADROperands()
1034 Inst.addOperand(MCOperand::CreateImm(pred)); in populateADROperands()
1035 Inst.addOperand(MCOperand::CreateReg(ccreg)); in populateADROperands()
1245 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); in EmitInstruction()
1246 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); in EmitInstruction()
1248 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL)); in EmitInstruction()
[all …]
|
| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 577 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
583 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
622 MI.addOperand(MCOperand::createImm(Imm)); in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 620 MI.addOperand(MCOperand::createImm(tmp)); in DecodeINSVE_DF()
626 MI.addOperand(MCOperand::createImm(0)); in DecodeINSVE_DF()
636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
640 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATIMMR6()
650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
654 MI.addOperand(MCOperand::createImm(Imm)); in DecodeDAHIDATI()
688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
[all …]
|
| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 33 class MCOperand {
53 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
111 static MCOperand createReg(unsigned Reg) { in createReg()
112 MCOperand Op; in createReg()
117 static MCOperand createImm(int64_t Val) { in createImm()
118 MCOperand Op; in createImm()
123 static MCOperand createFPImm(double Val) { in createFPImm()
124 MCOperand Op; in createFPImm()
129 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
130 MCOperand Op; in createExpr()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 16 MCOperand MCOp;
32 MCOperand MCOp;
48 MCOperand MCOp;
64 MCOperand MCOp;
67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
78 MCOperand MCOp;
81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
90 MCOperand MCOp;
93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCInst.h | 35 class MCOperand {
55 MCOperand() : FPImmVal(0.0) {} in MCOperand() function
116 static MCOperand createReg(unsigned Reg) { in createReg()
117 MCOperand Op; in createReg()
123 static MCOperand createImm(int64_t Val) { in createImm()
124 MCOperand Op; in createImm()
130 static MCOperand createFPImm(double Val) { in createFPImm()
131 MCOperand Op; in createFPImm()
137 static MCOperand createExpr(const MCExpr *Val) { in createExpr()
138 MCOperand Op; in createExpr()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 161 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); in translateRegister()
230 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
233 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
256 mcInst.addOperand(MCOperand::CreateImm(immediate)); in translateImmediate()
287 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; in translateRMRegister()
316 MCOperand baseReg; in translateRMMemory()
317 MCOperand scaleAmount; in translateRMMemory()
318 MCOperand indexReg; in translateRMMemory()
319 MCOperand displacement; in translateRMMemory()
320 MCOperand segmentReg; in translateRMMemory()
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInst.h | 31 class MCOperand {
49 MCOperand() : Kind(kInvalid), FPImmVal(0.0) {} in MCOperand() function
97 static MCOperand CreateReg(unsigned Reg) { in CreateReg()
98 MCOperand Op; in CreateReg()
103 static MCOperand CreateImm(int64_t Val) { in CreateImm()
104 MCOperand Op; in CreateImm()
109 static MCOperand CreateFPImm(double Val) { in CreateFPImm()
110 MCOperand Op; in CreateFPImm()
115 static MCOperand CreateExpr(const MCExpr *Val) { in CreateExpr()
116 MCOperand Op; in CreateExpr()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 60 const MCOperand &Dst = MI->getOperand(0); in printInst()
61 const MCOperand &MO1 = MI->getOperand(1); in printInst()
62 const MCOperand &MO2 = MI->getOperand(2); in printInst()
63 const MCOperand &MO3 = MI->getOperand(3); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
201 const MCOperand &Op = MI->getOperand(OpNo); in printOperand()
226 const MCOperand &MO1 = MI->getOperand(OpNum); in printT2LdrLabelOperand()
242 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 75 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
80 return MCOperand::createExpr(expr); in createSparcMCOperand()
83 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
88 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
103 return MCOperand::createExpr(expr); in createPCXRelExprOp()
107 MCOperand &Callee, in EmitCall()
117 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
128 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
140 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
146 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
[all …]
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcAsmPrinter.cpp | 77 static MCOperand createSparcMCOperand(SparcMCExpr::VariantKind Kind, in createSparcMCOperand()
82 return MCOperand::createExpr(expr); in createSparcMCOperand()
85 static MCOperand createPCXCallOP(MCSymbol *Label, in createPCXCallOP()
90 static MCOperand createPCXRelExprOp(SparcMCExpr::VariantKind Kind, in createPCXRelExprOp()
105 return MCOperand::createExpr(expr); in createPCXRelExprOp()
109 MCOperand &Callee, in EmitCall()
119 MCOperand &Imm, MCOperand &RD, in EmitSETHI()
130 MCOperand &RS1, MCOperand &Src2, MCOperand &RD, in EmitBinary()
142 MCOperand &RS1, MCOperand &Imm, MCOperand &RD, in EmitOR()
148 MCOperand &RS1, MCOperand &RS2, MCOperand &RD, in EmitADD()
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 538 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
539 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
540 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
546 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
547 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
548 instr.addOperand(MCOperand::CreateReg(RB)); in getInstruction()
558 instr.addOperand(MCOperand::CreateReg(RD)); in getInstruction()
559 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
564 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF)); in getInstruction()
565 instr.addOperand(MCOperand::CreateReg(RA)); in getInstruction()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 16 MCOperand MCOp;
22 TmpInst.addOperand(MCOperand::createImm(14));
23 TmpInst.addOperand(MCOperand::createReg(0));
29 MCOperand MCOp;
54 MCOperand MCOp;
81 MCOperand MCOp;
84 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
89 TmpInst.addOperand(MCOperand::createImm(14));
90 TmpInst.addOperand(MCOperand::createReg(0));
92 TmpInst.addOperand(MCOperand::createReg(0));
[all …]
|