1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
2|*                                                                            *|
3|* Pseudo-instruction MC lowering Source Fragment                             *|
4|*                                                                            *|
5|* Automatically generated file, do not edit!                                 *|
6|*                                                                            *|
7\*===----------------------------------------------------------------------===*/
8
9bool ARMAsmPrinter::
10emitPseudoExpansionLowering(MCStreamer &OutStreamer,
11                            const MachineInstr *MI) {
12  switch (MI->getOpcode()) {
13    default: return false;
14    case ARM::B: {
15      MCInst TmpInst;
16      MCOperand MCOp;
17      TmpInst.setOpcode(ARM::Bcc);
18      // Operand: target
19      lowerOperand(MI->getOperand(0), MCOp);
20      TmpInst.addOperand(MCOp);
21      // Operand: p
22      TmpInst.addOperand(MCOperand::createImm(14));
23      TmpInst.addOperand(MCOperand::createReg(0));
24      EmitToStreamer(OutStreamer, TmpInst);
25      break;
26    }
27    case ARM::LDMIA_RET: {
28      MCInst TmpInst;
29      MCOperand MCOp;
30      TmpInst.setOpcode(ARM::LDMIA_UPD);
31      // Operand: wb
32      lowerOperand(MI->getOperand(0), MCOp);
33      TmpInst.addOperand(MCOp);
34      // Operand: Rn
35      lowerOperand(MI->getOperand(1), MCOp);
36      TmpInst.addOperand(MCOp);
37      // Operand: p
38      lowerOperand(MI->getOperand(2), MCOp);
39      TmpInst.addOperand(MCOp);
40      lowerOperand(MI->getOperand(3), MCOp);
41      TmpInst.addOperand(MCOp);
42      // Operand: regs
43      lowerOperand(MI->getOperand(4), MCOp);
44      TmpInst.addOperand(MCOp);
45      // variable_ops
46      for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i)
47        if (lowerOperand(MI->getOperand(i), MCOp))
48          TmpInst.addOperand(MCOp);
49      EmitToStreamer(OutStreamer, TmpInst);
50      break;
51    }
52    case ARM::MLAv5: {
53      MCInst TmpInst;
54      MCOperand MCOp;
55      TmpInst.setOpcode(ARM::MLA);
56      // Operand: Rd
57      lowerOperand(MI->getOperand(0), MCOp);
58      TmpInst.addOperand(MCOp);
59      // Operand: Rn
60      lowerOperand(MI->getOperand(1), MCOp);
61      TmpInst.addOperand(MCOp);
62      // Operand: Rm
63      lowerOperand(MI->getOperand(2), MCOp);
64      TmpInst.addOperand(MCOp);
65      // Operand: Ra
66      lowerOperand(MI->getOperand(3), MCOp);
67      TmpInst.addOperand(MCOp);
68      // Operand: p
69      lowerOperand(MI->getOperand(4), MCOp);
70      TmpInst.addOperand(MCOp);
71      lowerOperand(MI->getOperand(5), MCOp);
72      TmpInst.addOperand(MCOp);
73      // Operand: s
74      lowerOperand(MI->getOperand(6), MCOp);
75      TmpInst.addOperand(MCOp);
76      EmitToStreamer(OutStreamer, TmpInst);
77      break;
78    }
79    case ARM::MOVPCRX: {
80      MCInst TmpInst;
81      MCOperand MCOp;
82      TmpInst.setOpcode(ARM::MOVr);
83      // Operand: Rd
84      TmpInst.addOperand(MCOperand::createReg(ARM::PC));
85      // Operand: Rm
86      lowerOperand(MI->getOperand(0), MCOp);
87      TmpInst.addOperand(MCOp);
88      // Operand: p
89      TmpInst.addOperand(MCOperand::createImm(14));
90      TmpInst.addOperand(MCOperand::createReg(0));
91      // Operand: s
92      TmpInst.addOperand(MCOperand::createReg(0));
93      EmitToStreamer(OutStreamer, TmpInst);
94      break;
95    }
96    case ARM::MULv5: {
97      MCInst TmpInst;
98      MCOperand MCOp;
99      TmpInst.setOpcode(ARM::MUL);
100      // Operand: Rd
101      lowerOperand(MI->getOperand(0), MCOp);
102      TmpInst.addOperand(MCOp);
103      // Operand: Rn
104      lowerOperand(MI->getOperand(1), MCOp);
105      TmpInst.addOperand(MCOp);
106      // Operand: Rm
107      lowerOperand(MI->getOperand(2), MCOp);
108      TmpInst.addOperand(MCOp);
109      // Operand: p
110      lowerOperand(MI->getOperand(3), MCOp);
111      TmpInst.addOperand(MCOp);
112      lowerOperand(MI->getOperand(4), MCOp);
113      TmpInst.addOperand(MCOp);
114      // Operand: s
115      lowerOperand(MI->getOperand(5), MCOp);
116      TmpInst.addOperand(MCOp);
117      EmitToStreamer(OutStreamer, TmpInst);
118      break;
119    }
120    case ARM::SMLALv5: {
121      MCInst TmpInst;
122      MCOperand MCOp;
123      TmpInst.setOpcode(ARM::SMLAL);
124      // Operand: RdLo
125      lowerOperand(MI->getOperand(0), MCOp);
126      TmpInst.addOperand(MCOp);
127      // Operand: RdHi
128      lowerOperand(MI->getOperand(1), MCOp);
129      TmpInst.addOperand(MCOp);
130      // Operand: Rn
131      lowerOperand(MI->getOperand(2), MCOp);
132      TmpInst.addOperand(MCOp);
133      // Operand: Rm
134      lowerOperand(MI->getOperand(3), MCOp);
135      TmpInst.addOperand(MCOp);
136      // Operand: RLo
137      lowerOperand(MI->getOperand(4), MCOp);
138      TmpInst.addOperand(MCOp);
139      // Operand: RHi
140      lowerOperand(MI->getOperand(5), MCOp);
141      TmpInst.addOperand(MCOp);
142      // Operand: p
143      lowerOperand(MI->getOperand(6), MCOp);
144      TmpInst.addOperand(MCOp);
145      lowerOperand(MI->getOperand(7), MCOp);
146      TmpInst.addOperand(MCOp);
147      // Operand: s
148      lowerOperand(MI->getOperand(8), MCOp);
149      TmpInst.addOperand(MCOp);
150      EmitToStreamer(OutStreamer, TmpInst);
151      break;
152    }
153    case ARM::SMULLv5: {
154      MCInst TmpInst;
155      MCOperand MCOp;
156      TmpInst.setOpcode(ARM::SMULL);
157      // Operand: RdLo
158      lowerOperand(MI->getOperand(0), MCOp);
159      TmpInst.addOperand(MCOp);
160      // Operand: RdHi
161      lowerOperand(MI->getOperand(1), MCOp);
162      TmpInst.addOperand(MCOp);
163      // Operand: Rn
164      lowerOperand(MI->getOperand(2), MCOp);
165      TmpInst.addOperand(MCOp);
166      // Operand: Rm
167      lowerOperand(MI->getOperand(3), MCOp);
168      TmpInst.addOperand(MCOp);
169      // Operand: p
170      lowerOperand(MI->getOperand(4), MCOp);
171      TmpInst.addOperand(MCOp);
172      lowerOperand(MI->getOperand(5), MCOp);
173      TmpInst.addOperand(MCOp);
174      // Operand: s
175      lowerOperand(MI->getOperand(6), MCOp);
176      TmpInst.addOperand(MCOp);
177      EmitToStreamer(OutStreamer, TmpInst);
178      break;
179    }
180    case ARM::TAILJMPd: {
181      MCInst TmpInst;
182      MCOperand MCOp;
183      TmpInst.setOpcode(ARM::Bcc);
184      // Operand: target
185      lowerOperand(MI->getOperand(0), MCOp);
186      TmpInst.addOperand(MCOp);
187      // Operand: p
188      TmpInst.addOperand(MCOperand::createImm(14));
189      TmpInst.addOperand(MCOperand::createReg(0));
190      EmitToStreamer(OutStreamer, TmpInst);
191      break;
192    }
193    case ARM::TAILJMPr: {
194      MCInst TmpInst;
195      MCOperand MCOp;
196      TmpInst.setOpcode(ARM::BX);
197      // Operand: dst
198      lowerOperand(MI->getOperand(0), MCOp);
199      TmpInst.addOperand(MCOp);
200      EmitToStreamer(OutStreamer, TmpInst);
201      break;
202    }
203    case ARM::TAILJMPr4: {
204      MCInst TmpInst;
205      MCOperand MCOp;
206      TmpInst.setOpcode(ARM::MOVr);
207      // Operand: Rd
208      TmpInst.addOperand(MCOperand::createReg(ARM::PC));
209      // Operand: Rm
210      lowerOperand(MI->getOperand(0), MCOp);
211      TmpInst.addOperand(MCOp);
212      // Operand: p
213      TmpInst.addOperand(MCOperand::createImm(14));
214      TmpInst.addOperand(MCOperand::createReg(0));
215      // Operand: s
216      TmpInst.addOperand(MCOperand::createReg(0));
217      EmitToStreamer(OutStreamer, TmpInst);
218      break;
219    }
220    case ARM::UMLALv5: {
221      MCInst TmpInst;
222      MCOperand MCOp;
223      TmpInst.setOpcode(ARM::UMLAL);
224      // Operand: RdLo
225      lowerOperand(MI->getOperand(0), MCOp);
226      TmpInst.addOperand(MCOp);
227      // Operand: RdHi
228      lowerOperand(MI->getOperand(1), MCOp);
229      TmpInst.addOperand(MCOp);
230      // Operand: Rn
231      lowerOperand(MI->getOperand(2), MCOp);
232      TmpInst.addOperand(MCOp);
233      // Operand: Rm
234      lowerOperand(MI->getOperand(3), MCOp);
235      TmpInst.addOperand(MCOp);
236      // Operand: RLo
237      lowerOperand(MI->getOperand(4), MCOp);
238      TmpInst.addOperand(MCOp);
239      // Operand: RHi
240      lowerOperand(MI->getOperand(5), MCOp);
241      TmpInst.addOperand(MCOp);
242      // Operand: p
243      lowerOperand(MI->getOperand(6), MCOp);
244      TmpInst.addOperand(MCOp);
245      lowerOperand(MI->getOperand(7), MCOp);
246      TmpInst.addOperand(MCOp);
247      // Operand: s
248      lowerOperand(MI->getOperand(8), MCOp);
249      TmpInst.addOperand(MCOp);
250      EmitToStreamer(OutStreamer, TmpInst);
251      break;
252    }
253    case ARM::UMULLv5: {
254      MCInst TmpInst;
255      MCOperand MCOp;
256      TmpInst.setOpcode(ARM::UMULL);
257      // Operand: RdLo
258      lowerOperand(MI->getOperand(0), MCOp);
259      TmpInst.addOperand(MCOp);
260      // Operand: RdHi
261      lowerOperand(MI->getOperand(1), MCOp);
262      TmpInst.addOperand(MCOp);
263      // Operand: Rn
264      lowerOperand(MI->getOperand(2), MCOp);
265      TmpInst.addOperand(MCOp);
266      // Operand: Rm
267      lowerOperand(MI->getOperand(3), MCOp);
268      TmpInst.addOperand(MCOp);
269      // Operand: p
270      lowerOperand(MI->getOperand(4), MCOp);
271      TmpInst.addOperand(MCOp);
272      lowerOperand(MI->getOperand(5), MCOp);
273      TmpInst.addOperand(MCOp);
274      // Operand: s
275      lowerOperand(MI->getOperand(6), MCOp);
276      TmpInst.addOperand(MCOp);
277      EmitToStreamer(OutStreamer, TmpInst);
278      break;
279    }
280    case ARM::VMOVD0: {
281      MCInst TmpInst;
282      MCOperand MCOp;
283      TmpInst.setOpcode(ARM::VMOVv2i32);
284      // Operand: Vd
285      lowerOperand(MI->getOperand(0), MCOp);
286      TmpInst.addOperand(MCOp);
287      // Operand: SIMM
288      TmpInst.addOperand(MCOperand::createImm(0));
289      // Operand: p
290      TmpInst.addOperand(MCOperand::createImm(14));
291      TmpInst.addOperand(MCOperand::createReg(0));
292      EmitToStreamer(OutStreamer, TmpInst);
293      break;
294    }
295    case ARM::VMOVQ0: {
296      MCInst TmpInst;
297      MCOperand MCOp;
298      TmpInst.setOpcode(ARM::VMOVv4i32);
299      // Operand: Vd
300      lowerOperand(MI->getOperand(0), MCOp);
301      TmpInst.addOperand(MCOp);
302      // Operand: SIMM
303      TmpInst.addOperand(MCOperand::createImm(0));
304      // Operand: p
305      TmpInst.addOperand(MCOperand::createImm(14));
306      TmpInst.addOperand(MCOperand::createReg(0));
307      EmitToStreamer(OutStreamer, TmpInst);
308      break;
309    }
310    case ARM::t2LDMIA_RET: {
311      MCInst TmpInst;
312      MCOperand MCOp;
313      TmpInst.setOpcode(ARM::t2LDMIA_UPD);
314      // Operand: wb
315      lowerOperand(MI->getOperand(0), MCOp);
316      TmpInst.addOperand(MCOp);
317      // Operand: Rn
318      lowerOperand(MI->getOperand(1), MCOp);
319      TmpInst.addOperand(MCOp);
320      // Operand: p
321      lowerOperand(MI->getOperand(2), MCOp);
322      TmpInst.addOperand(MCOp);
323      lowerOperand(MI->getOperand(3), MCOp);
324      TmpInst.addOperand(MCOp);
325      // Operand: regs
326      lowerOperand(MI->getOperand(4), MCOp);
327      TmpInst.addOperand(MCOp);
328      // variable_ops
329      for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i)
330        if (lowerOperand(MI->getOperand(i), MCOp))
331          TmpInst.addOperand(MCOp);
332      EmitToStreamer(OutStreamer, TmpInst);
333      break;
334    }
335    case ARM::tBRIND: {
336      MCInst TmpInst;
337      MCOperand MCOp;
338      TmpInst.setOpcode(ARM::tMOVr);
339      // Operand: Rd
340      TmpInst.addOperand(MCOperand::createReg(ARM::PC));
341      // Operand: Rm
342      lowerOperand(MI->getOperand(0), MCOp);
343      TmpInst.addOperand(MCOp);
344      // Operand: p
345      lowerOperand(MI->getOperand(1), MCOp);
346      TmpInst.addOperand(MCOp);
347      lowerOperand(MI->getOperand(2), MCOp);
348      TmpInst.addOperand(MCOp);
349      EmitToStreamer(OutStreamer, TmpInst);
350      break;
351    }
352    case ARM::tBX_RET: {
353      MCInst TmpInst;
354      MCOperand MCOp;
355      TmpInst.setOpcode(ARM::tBX);
356      // Operand: Rm
357      TmpInst.addOperand(MCOperand::createReg(ARM::LR));
358      // Operand: p
359      lowerOperand(MI->getOperand(0), MCOp);
360      TmpInst.addOperand(MCOp);
361      lowerOperand(MI->getOperand(1), MCOp);
362      TmpInst.addOperand(MCOp);
363      EmitToStreamer(OutStreamer, TmpInst);
364      break;
365    }
366    case ARM::tBX_RET_vararg: {
367      MCInst TmpInst;
368      MCOperand MCOp;
369      TmpInst.setOpcode(ARM::tBX);
370      // Operand: Rm
371      lowerOperand(MI->getOperand(0), MCOp);
372      TmpInst.addOperand(MCOp);
373      // Operand: p
374      lowerOperand(MI->getOperand(1), MCOp);
375      TmpInst.addOperand(MCOp);
376      lowerOperand(MI->getOperand(2), MCOp);
377      TmpInst.addOperand(MCOp);
378      EmitToStreamer(OutStreamer, TmpInst);
379      break;
380    }
381    case ARM::tBfar: {
382      MCInst TmpInst;
383      MCOperand MCOp;
384      TmpInst.setOpcode(ARM::tBL);
385      // Operand: p
386      lowerOperand(MI->getOperand(1), MCOp);
387      TmpInst.addOperand(MCOp);
388      lowerOperand(MI->getOperand(2), MCOp);
389      TmpInst.addOperand(MCOp);
390      // Operand: func
391      lowerOperand(MI->getOperand(0), MCOp);
392      TmpInst.addOperand(MCOp);
393      EmitToStreamer(OutStreamer, TmpInst);
394      break;
395    }
396    case ARM::tLDMIA_UPD: {
397      MCInst TmpInst;
398      MCOperand MCOp;
399      TmpInst.setOpcode(ARM::tLDMIA);
400      // Operand: Rn
401      lowerOperand(MI->getOperand(1), MCOp);
402      TmpInst.addOperand(MCOp);
403      // Operand: p
404      lowerOperand(MI->getOperand(2), MCOp);
405      TmpInst.addOperand(MCOp);
406      lowerOperand(MI->getOperand(3), MCOp);
407      TmpInst.addOperand(MCOp);
408      // Operand: regs
409      lowerOperand(MI->getOperand(4), MCOp);
410      TmpInst.addOperand(MCOp);
411      // variable_ops
412      for (unsigned i = 5, e = MI->getNumOperands(); i != e; ++i)
413        if (lowerOperand(MI->getOperand(i), MCOp))
414          TmpInst.addOperand(MCOp);
415      EmitToStreamer(OutStreamer, TmpInst);
416      break;
417    }
418    case ARM::tPOP_RET: {
419      MCInst TmpInst;
420      MCOperand MCOp;
421      TmpInst.setOpcode(ARM::tPOP);
422      // Operand: p
423      lowerOperand(MI->getOperand(0), MCOp);
424      TmpInst.addOperand(MCOp);
425      lowerOperand(MI->getOperand(1), MCOp);
426      TmpInst.addOperand(MCOp);
427      // Operand: regs
428      lowerOperand(MI->getOperand(2), MCOp);
429      TmpInst.addOperand(MCOp);
430      // variable_ops
431      for (unsigned i = 3, e = MI->getNumOperands(); i != e; ++i)
432        if (lowerOperand(MI->getOperand(i), MCOp))
433          TmpInst.addOperand(MCOp);
434      EmitToStreamer(OutStreamer, TmpInst);
435      break;
436    }
437    case ARM::tTAILJMPd: {
438      MCInst TmpInst;
439      MCOperand MCOp;
440      TmpInst.setOpcode(ARM::t2B);
441      // Operand: target
442      lowerOperand(MI->getOperand(0), MCOp);
443      TmpInst.addOperand(MCOp);
444      // Operand: p
445      lowerOperand(MI->getOperand(1), MCOp);
446      TmpInst.addOperand(MCOp);
447      lowerOperand(MI->getOperand(2), MCOp);
448      TmpInst.addOperand(MCOp);
449      EmitToStreamer(OutStreamer, TmpInst);
450      break;
451    }
452    case ARM::tTAILJMPdND: {
453      MCInst TmpInst;
454      MCOperand MCOp;
455      TmpInst.setOpcode(ARM::tB);
456      // Operand: target
457      lowerOperand(MI->getOperand(0), MCOp);
458      TmpInst.addOperand(MCOp);
459      // Operand: p
460      lowerOperand(MI->getOperand(1), MCOp);
461      TmpInst.addOperand(MCOp);
462      lowerOperand(MI->getOperand(2), MCOp);
463      TmpInst.addOperand(MCOp);
464      EmitToStreamer(OutStreamer, TmpInst);
465      break;
466    }
467    case ARM::tTAILJMPr: {
468      MCInst TmpInst;
469      MCOperand MCOp;
470      TmpInst.setOpcode(ARM::tBX);
471      // Operand: Rm
472      lowerOperand(MI->getOperand(0), MCOp);
473      TmpInst.addOperand(MCOp);
474      // Operand: p
475      TmpInst.addOperand(MCOperand::createImm(14));
476      TmpInst.addOperand(MCOperand::createReg(0));
477      EmitToStreamer(OutStreamer, TmpInst);
478      break;
479    }
480  }
481  return true;
482}
483
484