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Searched refs:MIs (Results 1 – 22 of 22) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DInstructionSelectorImpl.h94 MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx); in executeMatchTable()
111 if ((size_t)NewInsnID < State.MIs.size()) in executeMatchTable()
112 State.MIs[NewInsnID] = NewMI; in executeMatchTable()
114 assert((size_t)NewInsnID == State.MIs.size() && in executeMatchTable()
116 State.MIs.push_back(NewMI); in executeMatchTable()
143 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
144 unsigned Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
163 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
164 const int64_t Opcode = State.MIs[InsnID]->getOpcode(); in executeMatchTable()
191 assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); in executeMatchTable()
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DInstructionSelector.h369 RecordedMIVector MIs; member
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DGlobalISelEmitter.td237 // CHECK-NEXT: State.MIs.clear();
238 // CHECK-NEXT: State.MIs.push_back(&I);
267 // R19N-NEXT: // MIs[0] dst
270 // R19N-NEXT: // MIs[0] src1
273 // R19N-NEXT: // MIs[0] Operand 2
277 // R19N-NEXT: // MIs[0] Operand 3
279 // R19C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1]
282 // R19N-NEXT: // MIs[1] Operand 0
284 // R19N-NEXT: // MIs[1] src3
289 // R19N-NEXT: // MIs[1] src4
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/external/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp238 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
239 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); in RemoveMI()
243 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
244 MIs.erase(std::find(MIs.begin(), MIs.end(), MI), MIs.end()); in RemoveMI()
301 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
303 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
DR600InstrInfo.h139 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
DR600ControlFlowFinalizer.cpp483 void CounterPropagateAddr(const std::set<MachineInstr *> &MIs, in CounterPropagateAddr() argument
485 for (MachineInstr *MI : MIs) { in CounterPropagateAddr()
DR600InstrInfo.cpp618 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs) in fitsConstReadLimitations()
622 for (unsigned i = 0, n = MIs.size(); i < n; i++) { in fitsConstReadLimitations()
623 MachineInstr &MI = *MIs[i]; in fitsConstReadLimitations()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600OptimizeVectorRegisters.cpp260 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
261 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
265 std::vector<MachineInstr *> &MIs = (*It).second; in RemoveMI() local
266 MIs.erase(llvm::find(MIs, MI), MIs.end()); in RemoveMI()
323 std::vector<MachineInstr *> &MIs = in tryMergeUsingFreeSlot() local
325 CompatibleRSI = PreviousRegSeq[MIs.back()]; in tryMergeUsingFreeSlot()
DR600InstrInfo.h144 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
DR600ControlFlowFinalizer.cpp496 void CounterPropagateAddr(const std::set<MachineInstr *> &MIs, in CounterPropagateAddr() argument
498 for (MachineInstr *MI : MIs) { in CounterPropagateAddr()
DR600InstrInfo.cpp609 R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs) in fitsConstReadLimitations()
613 for (unsigned i = 0, n = MIs.size(); i < n; i++) { in fitsConstReadLimitations()
614 MachineInstr &MI = *MIs[i]; in fitsConstReadLimitations()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DVirtRegMap.cpp409 SmallVector<MachineInstr *, 2> MIs({&MI}); in expandCopyBundle() local
418 MIs.push_back(&*I); in expandCopyBundle()
420 MachineInstr *FirstMI = MIs.back(); in expandCopyBundle()
436 for (int E = MIs.size(), PrevE = E; E > 1; PrevE = E) { in expandCopyBundle()
438 if (!anyRegsAlias(MIs[I], makeArrayRef(MIs).take_front(E), TRI)) { in expandCopyBundle()
440 std::swap(MIs[I], MIs[E - 1]); in expandCopyBundle()
451 for (MachineInstr *BundledMI : llvm::reverse(MIs)) { in expandCopyBundle()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc711 State.MIs.clear();
712 State.MIs.push_back(&I);
775 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
799 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
823 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
847 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
872 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
896 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
920 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
944 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenGlobalISel.inc792 State.MIs.clear();
793 State.MIs.push_back(&I);
930 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
934 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
938 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
941 // MIs[3] Operand 1
965 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
969 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2]
973 GIM_RecordInsn, /*DefineMI*/3, /*MI*/1, /*OpIdx*/2, // MIs[3]
976 // MIs[3] Operand 1
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc782 State.MIs.clear();
783 State.MIs.push_back(&I);
875 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
877 // MIs[1] Operand 1
945 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
948 // MIs[1] Operand 1
962 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
964 // MIs[1] Operand 1
1032 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
1035 // MIs[1] Operand 1
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc532 State.MIs.clear();
533 State.MIs.push_back(&I);
602 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1]
607 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
610 // MIs[2] Operand 1
630 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
635 GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2]
638 // MIs[2] Operand 1
657 GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
660 // MIs[1] Operand 1
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dsetmemrefs.ll4 ; memrefs of the resulting load MIs correctly, so that they are packetized
Dtrivialmemaliascheck.ll6 ; surface. do not have only one mem operand. However, the backend knows MIs and
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DInstructionSelector.cpp33 : Renderers(MaxRenderers), MIs() {} in MatcherState()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp1783 SmallVector<MachineInstr*, 4> MIs; in RescheduleLoadStoreInstrs() local
1784 MIs.push_back(MI); in RescheduleLoadStoreInstrs()
1785 Base2LdsMap[Base] = MIs; in RescheduleLoadStoreInstrs()
1801 SmallVector<MachineInstr*, 4> MIs; in RescheduleLoadStoreInstrs() local
1802 MIs.push_back(MI); in RescheduleLoadStoreInstrs()
1803 Base2StsMap[Base] = MIs; in RescheduleLoadStoreInstrs()
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DCodeGenerator.rst527 Conceptually a MI bundle is a MI with a number of other MIs nested within:
566 MachineBasicBlock and MachineInstr. All the MIs (including top level and nested
567 ones) are stored as sequential list of MIs. The "bundled" MIs are marked with
569 to represent the start of a bundle. It's legal to mix BUNDLE MIs with individual
570 MIs that are not inside bundles nor represent bundles.
573 methods have been taught to correctly handle bundles and MIs inside bundles.
574 The MachineBasicBlock iterator has been modified to skip over bundled MIs to
577 over all of the MIs in a MachineBasicBlock, including those which are nested
580 the bundled MIs.
583 allocation super-pass. More specifically, the pass which determines what MIs
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/external/llvm/docs/
DCodeGenerator.rst527 Conceptually a MI bundle is a MI with a number of other MIs nested within:
566 MachineBasicBlock and MachineInstr. All the MIs (including top level and nested
567 ones) are stored as sequential list of MIs. The "bundled" MIs are marked with
569 to represent the start of a bundle. It's legal to mix BUNDLE MIs with indiviual
570 MIs that are not inside bundles nor represent bundles.
573 methods have been taught to correctly handle bundles and MIs inside bundles.
574 The MachineBasicBlock iterator has been modified to skip over bundled MIs to
577 over all of the MIs in a MachineBasicBlock, including those which are nested
580 the bundled MIs.
583 allocation super-pass. More specifically, the pass which determines what MIs
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