Searched refs:NextReg (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1128 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1133 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1139 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1141 NextReg += 4; in emitAlignedDPRCS2Spills()
1147 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1151 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1155 .addReg(ARM::R4).addImm(16).addReg(NextReg) in emitAlignedDPRCS2Spills()
1157 NextReg += 4; in emitAlignedDPRCS2Spills()
1163 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1168 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 1227 unsigned NextReg = ARM::D8; in emitAlignedDPRCS2Spills() local
1232 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1238 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1241 NextReg += 4; in emitAlignedDPRCS2Spills()
1247 unsigned R4BaseReg = NextReg; in emitAlignedDPRCS2Spills()
1251 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1257 .addReg(NextReg) in emitAlignedDPRCS2Spills()
1260 NextReg += 4; in emitAlignedDPRCS2Spills()
1266 unsigned SupReg = TRI->getMatchingSuperReg(NextReg, ARM::dsub_0, in emitAlignedDPRCS2Spills()
1274 NextReg += 2; in emitAlignedDPRCS2Spills()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 869 unsigned NextReg = SrcReg; in getSrcVReg() local
872 NextReg = getIncomingRegForBlock(Inst, BB1); in getSrcVReg()
877 NextReg = Inst->getOperand(1).getReg(); in getSrcVReg()
878 if (NextReg == SrcReg || !TargetRegisterInfo::isVirtualRegister(NextReg)) in getSrcVReg()
880 SrcReg = NextReg; in getSrcVReg()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 913 unsigned NextReg = CSI[i + 1].getReg(); in computeCalleeSaveRegisterPairs() local
914 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()
915 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg))) in computeCalleeSaveRegisterPairs()
916 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FrameLowering.cpp | 1186 unsigned NextReg = CSI[i + 1].getReg(); in computeCalleeSaveRegisterPairs() local
1187 if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) || in computeCalleeSaveRegisterPairs()
1188 (!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg))) in computeCalleeSaveRegisterPairs()
1189 RPI.Reg2 = NextReg; in computeCalleeSaveRegisterPairs()
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| /external/swiftshader/third_party/subzero/src/ |
| D | IceInstARM32.cpp | 1438 const Variable *NextReg = getStackReg(i); in emitUsingForm() local
1439 assert(NextReg->hasReg()); in emitUsingForm()
1441 BaseReg = NextReg; in emitUsingForm()
1444 isAssignedConsecutiveRegisters(Reg, NextReg)) { in emitUsingForm()
1448 BaseReg = NextReg; in emitUsingForm()
1451 Reg = NextReg; in emitUsingForm()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 1743 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; in CC_MipsO32() local
1745 r < std::min(IntRegsSize, NextReg); ++r) in CC_MipsO32()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 5535 int NextReg = nextReg(((MipsOperand &)*Operands[1]).getGPR32Reg()); in ConvertXWPOperands() local
5536 Inst.addOperand(MCOperand::createReg(NextReg)); in ConvertXWPOperands()
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