| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 212 SDNode *SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
220 SDNode *SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
228 bool isUpdating, unsigned NumVecs,
234 SDNode *SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
240 SDNode *SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
284 SDValue GetVLDSTAlign(SDValue Align, unsigned NumVecs, bool is64BitVector);
1533 SDValue ARMDAGToDAGISel::GetVLDSTAlign(SDValue Align, unsigned NumVecs, in GetVLDSTAlign() argument
1535 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1536 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1552 SDNode *ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
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| D | ARMISelLowering.cpp | 7176 unsigned NumVecs = 0; in CombineBaseUpdate() local
7182 NumVecs = 1; break; in CombineBaseUpdate()
7184 NumVecs = 2; break; in CombineBaseUpdate()
7186 NumVecs = 3; break; in CombineBaseUpdate()
7188 NumVecs = 4; break; in CombineBaseUpdate()
7190 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
7192 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
7194 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
7196 NumVecs = 1; isLoad = false; break; in CombineBaseUpdate()
7198 NumVecs = 2; isLoad = false; break; in CombineBaseUpdate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Analysis/ |
| D | VectorUtils.cpp | 495 unsigned NumVecs) { in createInterleaveMask() argument
498 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
553 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
554 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
560 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
562 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
569 if (NumVecs % 2 != 0) in concatenateVectors()
570 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
573 NumVecs = ResList.size(); in concatenateVectors()
574 } while (NumVecs > 1); in concatenateVectors()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 204 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
212 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
220 unsigned NumVecs, const uint16_t *DOpcodes,
226 void SelectVLDDup(SDNode *N, bool isUpdating, unsigned NumVecs,
232 void SelectVTBL(SDNode *N, bool IsExt, unsigned NumVecs, unsigned Opc);
268 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1688 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1689 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1690 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1808 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs, in SelectVLD() argument
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| D | ARMISelLowering.cpp | 9923 unsigned NumVecs = 0; in CombineBaseUpdate() local
9929 NumVecs = 1; break; in CombineBaseUpdate()
9931 NumVecs = 2; break; in CombineBaseUpdate()
9933 NumVecs = 3; break; in CombineBaseUpdate()
9935 NumVecs = 4; break; in CombineBaseUpdate()
9937 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
9939 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
9941 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
9943 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
9945 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMISelDAGToDAG.cpp | 185 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
193 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
201 unsigned NumVecs, const uint16_t *DOpcodes,
208 unsigned NumVecs, const uint16_t *DOpcodes,
244 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1603 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1604 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1605 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
1738 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
1740 return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs; in isPerfectIncrement()
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| D | ARMISelLowering.cpp | 11552 unsigned NumVecs = 0; in CombineBaseUpdate() local
11558 NumVecs = 1; break; in CombineBaseUpdate()
11560 NumVecs = 2; break; in CombineBaseUpdate()
11562 NumVecs = 3; break; in CombineBaseUpdate()
11564 NumVecs = 4; break; in CombineBaseUpdate()
11572 NumVecs = 2; isLaneOp = true; break; in CombineBaseUpdate()
11574 NumVecs = 3; isLaneOp = true; break; in CombineBaseUpdate()
11576 NumVecs = 4; isLaneOp = true; break; in CombineBaseUpdate()
11578 NumVecs = 1; isLoadOp = false; break; in CombineBaseUpdate()
11580 NumVecs = 2; isLoadOp = false; break; in CombineBaseUpdate()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 151 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
155 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
157 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
159 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
160 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
165 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1076 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable() argument
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| D | AArch64ISelLowering.cpp | 10249 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
10254 NumVecs = 2; break; in performNEONPostLDSTCombine()
10256 NumVecs = 3; break; in performNEONPostLDSTCombine()
10258 NumVecs = 4; break; in performNEONPostLDSTCombine()
10260 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
10262 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
10264 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
10266 NumVecs = 2; break; in performNEONPostLDSTCombine()
10268 NumVecs = 3; break; in performNEONPostLDSTCombine()
10270 NumVecs = 4; break; in performNEONPostLDSTCombine()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelDAGToDAG.cpp | 150 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
154 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
156 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
158 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
159 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
161 void SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
162 void SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
163 void SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
164 void SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable() argument
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| D | AArch64ISelLowering.cpp | 9229 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
9234 NumVecs = 2; break; in performNEONPostLDSTCombine()
9236 NumVecs = 3; break; in performNEONPostLDSTCombine()
9238 NumVecs = 4; break; in performNEONPostLDSTCombine()
9240 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
9242 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
9244 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
9246 NumVecs = 2; break; in performNEONPostLDSTCombine()
9248 NumVecs = 3; break; in performNEONPostLDSTCombine()
9250 NumVecs = 4; break; in performNEONPostLDSTCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Analysis/ |
| D | VectorUtils.h | 139 unsigned NumVecs);
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 37753 unsigned NumVecs = VT.getSizeInBits() / SplitSize; in combineToExtendVectorInReg() local
37759 for (unsigned i = 0, Offset = 0; i != NumVecs; ++i, Offset += NumSubElts) { in combineToExtendVectorInReg()
|