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Searched refs:OpSize (Results 1 – 25 of 56) sorted by relevance

123

/external/llvm/utils/TableGen/
DX86RecognizableInstr.h51 uint8_t OpSize; variable
122 bool hasREX_WPrefix, uint8_t OpSize);
133 uint8_t OpSize);
138 uint8_t OpSize);
143 uint8_t OpSize);
145 uint8_t OpSize);
147 uint8_t OpSize);
149 uint8_t OpSize);
151 uint8_t OpSize);
153 uint8_t OpSize);
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DX86RecognizableInstr.cpp211 OpSize = byteFromRec(Rec, "OpSizeBits"); in RecognizableInstr()
419 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
423 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
425 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
427 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
429 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
446 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
448 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
450 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
452 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
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/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DX86RecognizableInstr.h173 uint8_t OpSize; variable
242 bool hasREX_WPrefix, uint8_t OpSize);
253 uint8_t OpSize);
258 uint8_t OpSize);
263 uint8_t OpSize);
265 uint8_t OpSize);
267 uint8_t OpSize);
269 uint8_t OpSize);
271 uint8_t OpSize);
273 uint8_t OpSize);
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DX86RecognizableInstr.cpp83 OpSize = byteFromRec(Rec, "OpSizeBits"); in RecognizableInstr()
304 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) in insnContext()
308 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
310 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
314 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) in insnContext()
316 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
333 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) in insnContext()
335 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) in insnContext()
343 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) in insnContext()
345 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) in insnContext()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSystem.td59 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
73 "in{w}\t{%dx, %ax|AX, DX}", []>, OpSize;
83 "in{w}\t{$port, %ax|AX, $port}", []>, OpSize;
93 "out{w}\t{%ax, %dx|DX, AX}", []>, OpSize;
103 "out{w}\t{%ax, $port|$port, AX}", []>, OpSize;
109 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>, OpSize;
154 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
161 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
168 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
175 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
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DX86InstrShiftRotate.td25 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
55 "shl{w}\t$dst", []>, OpSize;
72 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
86 OpSize;
101 OpSize;
116 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
130 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
144 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
161 OpSize;
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DX86InstrVMX.td20 "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
22 "invept {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
25 "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
27 "invvpid {$src2, $src1|$src1, $src2}", []>, OpSize, T8;
31 "vmclear\t$vmcs", []>, OpSize, TB;
DX86InstrFormats.td88 class OpSize { bit hasOpSizePrefix = 1; }
284 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
295 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
335 // PDI - SSE2 instructions with TB and OpSize prefixes.
336 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
338 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
349 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
353 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
362 OpSize, Requires<[HasAVX]>;
366 // S3I - SSE3 instructions with TB and OpSize prefixes.
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DX86InstrInfo.td648 "nop{w}\t$zero", []>, TB, OpSize;
673 OpSize;
676 OpSize;
678 OpSize;
682 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
689 OpSize;
692 OpSize;
694 OpSize;
701 "push{w}\t$imm", []>, OpSize;
705 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
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DX86InstrSSE.td669 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
673 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
678 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
682 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
686 "movapd", SSEPackedDouble>, TB, OpSize;
690 "movupd", SSEPackedDouble, 0>, TB, OpSize;
931 SSEPackedDouble>, TB, OpSize;
1659 // SSE2 instructions without OpSize prefix
1840 // SSE2 instructions without OpSize prefix
2050 "ucomisd", SSEPackedDouble>, TB, OpSize, VEX,
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DX86InstrExtension.td17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
42 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
44 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
59 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
61 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
DX86InstrArithmetic.td21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
59 []>, OpSize; // AX,DX = AX*GR16
83 []>, OpSize; // AX,DX = AX*[mem16]
100 OpSize; // AX,DX = AX*GR16
114 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
133 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
151 TB, OpSize;
173 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
179 OpSize;
208 OpSize;
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DX86InstrControl.td29 []>, OpSize;
37 "lretw\t$amt", []>, OpSize;
113 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
121 "ljmp{w}\t{*}$dst", []>, OpSize;
158 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
164 "lcall{w}\t{*}$dst", []>, OpSize;
172 "callw\t$dst", []>, OpSize;
DX86InstrCMovSetCC.td24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
42 CondNode, EFLAGS))]>, TB, OpSize;
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp44 uint32_t getLitEncoding(const MCOperand &MO, unsigned OpSize) const;
164 unsigned OpSize) const { in getLitEncoding()
183 if (OpSize == 4) in getLitEncoding()
186 assert(OpSize == 8); in getLitEncoding()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp343 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalar() local
347 if (SrcStart + NarrowSize <= OpStart || SrcStart >= OpStart + OpSize) { in narrowScalar()
362 SegSize = std::min(NarrowSize, OpStart + OpSize - SrcStart); in narrowScalar()
365 SegSize = std::min(SrcStart + NarrowSize - OpStart, OpSize); in narrowScalar()
396 uint64_t OpSize = MRI.getType(OpReg).getSizeInBits(); in narrowScalar() local
400 if (DstStart + NarrowSize <= OpStart || DstStart >= OpStart + OpSize) { in narrowScalar()
418 SegSize = std::min(NarrowSize, OpStart + OpSize - DstStart); in narrowScalar()
423 std::min(NarrowSize - InsertOffset, OpStart + OpSize - DstStart); in narrowScalar()
427 if (ExtractOffset != 0 || SegSize != OpSize) { in narrowScalar()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLegalizerInfo.cpp349 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits(); in legalizeCustom() local
354 auto Libcalls = getFCmpLibcalls(Predicate, OpSize); in legalizeCustom()
366 assert((OpSize == 32 || OpSize == 64) && "Unsupported operand size"); in legalizeCustom()
367 auto *ArgTy = OpSize == 32 ? Type::getFloatTy(Ctx) : Type::getDoubleTy(Ctx); in legalizeCustom()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/IR/
DMetadata.cpp482 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local
485 OpSize = alignTo(OpSize, alignof(uint64_t)); in operator new()
486 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize; in operator new()
495 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
496 OpSize = alignTo(OpSize, alignof(uint64_t)); in operator delete()
501 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize); in operator delete()
/external/llvm/lib/IR/
DMetadata.cpp445 size_t OpSize = NumOps * sizeof(MDOperand); in operator new() local
448 OpSize = alignTo(OpSize, llvm::alignOf<uint64_t>()); in operator new()
449 void *Ptr = reinterpret_cast<char *>(::operator new(OpSize + Size)) + OpSize; in operator new()
458 size_t OpSize = N->NumOperands * sizeof(MDOperand); in operator delete() local
459 OpSize = alignTo(OpSize, llvm::alignOf<uint64_t>()); in operator delete()
464 ::operator delete(reinterpret_cast<char *>(Mem) - OpSize); in operator delete()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsInstructionSelector.cpp133 const unsigned OpSize = MRI.getType(DestReg).getSizeInBits(); in select() local
135 if (DestRegBank != Mips::GPRBRegBankID || OpSize != 32) in select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64RegisterBankInfo.cpp540 SmallVector<unsigned, 4> OpSize(NumOperands); in getInstrMapping() local
548 OpSize[Idx] = Ty.getSizeInBits(); in getInstrMapping()
581 OpSize[0]); in getInstrMapping()
641 auto Mapping = getValueMapping(OpRegBankIdx[Idx], OpSize[Idx]); in getInstrMapping()
DAArch64InstructionSelector.cpp223 unsigned OpSize) { in selectBinaryOp() argument
226 if (OpSize == 32) { in selectBinaryOp()
237 } else if (OpSize == 64) { in selectBinaryOp()
253 switch (OpSize) { in selectBinaryOp()
294 unsigned OpSize) { in selectLoadStoreUIOp() argument
298 switch (OpSize) { in selectLoadStoreUIOp()
310 switch (OpSize) { in selectLoadStoreUIOp()
1119 const unsigned OpSize = Ty.getSizeInBits(); in select() local
1124 const unsigned NewOpc = selectBinaryOp(I.getOpcode(), RB.getID(), OpSize); in select()
/external/llvm/test/CodeGen/X86/
Drotate4.ll4 ; a << (b & (OpSize-1)) | a >> ((0 - b) & (OpSize-1))
/external/llvm/include/llvm/Analysis/
DTargetTransformInfoImpl.h76 unsigned OpSize = OpTy->getScalarSizeInBits(); in getOperationCost() local
77 if (DL.isLegalInteger(OpSize) && in getOperationCost()
78 OpSize <= DL.getPointerTypeSizeInBits(Ty)) in getOperationCost()
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.h376 bool isInlineConstant(const MachineOperand &MO, unsigned OpSize) const;
377 bool isLiteralConstant(const MachineOperand &MO, unsigned OpSize) const;
389 unsigned OpSize) const;

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