1//===- X86InstrSystem.td - System Instructions -------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the X86 instructions that are generally used in
11// privileged modes.  These are not typically used by the compiler, but are
12// supported for the assembler and disassembler.
13//
14//===----------------------------------------------------------------------===//
15
16let Defs = [RAX, RDX] in
17  def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)]>, TB;
18
19let Defs = [RAX, RCX, RDX] in
20  def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
21
22// CPU flow control instructions
23
24let isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
25  def TRAP    : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
26  def UD2B    : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
27}
28
29def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
30def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", []>, TB;
31
32// Interrupt and SysCall Instructions.
33let Uses = [EFLAGS] in
34  def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
35def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
36              [(int_x86_int (i8 3))]>;
37
38// The long form of "int $3" turns into int3 as a size optimization.
39// FIXME: This doesn't work because InstAlias can't match immediate constants.
40//def : InstAlias<"int\t$3", (INT3)>;
41
42
43def INT : Ii8<0xcd, RawFrm, (outs), (ins i8imm:$trap), "int\t$trap",
44              [(int_x86_int imm:$trap)]>;
45
46
47def SYSCALL  : I<0x05, RawFrm, (outs), (ins), "syscall", []>, TB;
48def SYSRETL  : I<0x07, RawFrm, (outs), (ins), "sysretl", []>, TB;
49def SYSRETQ  :RI<0x07, RawFrm, (outs), (ins), "sysretq", []>, TB,
50               Requires<[In64BitMode]>;
51
52def SYSENTER : I<0x34, RawFrm, (outs), (ins), "sysenter", []>, TB;
53
54def SYSEXIT   : I<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
55                Requires<[In32BitMode]>;
56def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit", []>, TB,
57                Requires<[In64BitMode]>;
58
59def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
60def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>;
61def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", []>,
62             Requires<[In64BitMode]>;
63
64
65//===----------------------------------------------------------------------===//
66//  Input/Output Instructions.
67//
68let Defs = [AL], Uses = [DX] in
69def IN8rr  : I<0xEC, RawFrm, (outs), (ins),
70               "in{b}\t{%dx, %al|AL, DX}", []>;
71let Defs = [AX], Uses = [DX] in
72def IN16rr : I<0xED, RawFrm, (outs), (ins),
73               "in{w}\t{%dx, %ax|AX, DX}", []>,  OpSize;
74let Defs = [EAX], Uses = [DX] in
75def IN32rr : I<0xED, RawFrm, (outs), (ins),
76               "in{l}\t{%dx, %eax|EAX, DX}", []>;
77
78let Defs = [AL] in
79def IN8ri  : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
80                  "in{b}\t{$port, %al|AL, $port}", []>;
81let Defs = [AX] in
82def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
83                  "in{w}\t{$port, %ax|AX, $port}", []>, OpSize;
84let Defs = [EAX] in
85def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
86                  "in{l}\t{$port, %eax|EAX, $port}", []>;
87
88let Uses = [DX, AL] in
89def OUT8rr  : I<0xEE, RawFrm, (outs), (ins),
90                "out{b}\t{%al, %dx|DX, AL}", []>;
91let Uses = [DX, AX] in
92def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
93                "out{w}\t{%ax, %dx|DX, AX}", []>, OpSize;
94let Uses = [DX, EAX] in
95def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
96                "out{l}\t{%eax, %dx|DX, EAX}", []>;
97
98let Uses = [AL] in
99def OUT8ir  : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
100                   "out{b}\t{%al, $port|$port, AL}", []>;
101let Uses = [AX] in
102def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
103                   "out{w}\t{%ax, $port|$port, AX}", []>, OpSize;
104let Uses = [EAX] in
105def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
106                   "out{l}\t{%eax, $port|$port, EAX}", []>;
107
108def IN8  : I<0x6C, RawFrm, (outs), (ins), "ins{b}", []>;
109def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>,  OpSize;
110def IN32 : I<0x6D, RawFrm, (outs), (ins), "ins{l}", []>;
111
112//===----------------------------------------------------------------------===//
113// Moves to and from debug registers
114
115def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
116                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
117def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
118                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
119
120def MOV32dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR32:$src),
121                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
122def MOV64dr : I<0x23, MRMSrcReg, (outs DEBUG_REG:$dst), (ins GR64:$src),
123                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
124
125//===----------------------------------------------------------------------===//
126// Moves to and from control registers
127
128def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
129                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
130def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
131                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
132
133def MOV32cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR32:$src),
134                "mov{l}\t{$src, $dst|$dst, $src}", []>, TB;
135def MOV64cr : I<0x22, MRMSrcReg, (outs CONTROL_REG:$dst), (ins GR64:$src),
136                "mov{q}\t{$src, $dst|$dst, $src}", []>, TB;
137
138//===----------------------------------------------------------------------===//
139// Segment override instruction prefixes
140
141def CS_PREFIX : I<0x2E, RawFrm, (outs), (ins), "cs", []>;
142def SS_PREFIX : I<0x36, RawFrm, (outs), (ins), "ss", []>;
143def DS_PREFIX : I<0x3E, RawFrm, (outs), (ins), "ds", []>;
144def ES_PREFIX : I<0x26, RawFrm, (outs), (ins), "es", []>;
145def FS_PREFIX : I<0x64, RawFrm, (outs), (ins), "fs", []>;
146def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
147
148
149//===----------------------------------------------------------------------===//
150// Moves to and from segment registers.
151//
152
153def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
154                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
155def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
156                "mov{l}\t{$src, $dst|$dst, $src}", []>;
157def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
158                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
159
160def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
161                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
162def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
163                "mov{l}\t{$src, $dst|$dst, $src}", []>;
164def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
165                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
166
167def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
168                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
169def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
170                "mov{l}\t{$src, $dst|$dst, $src}", []>;
171def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
172                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
173
174def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
175                "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
176def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
177                "mov{l}\t{$src, $dst|$dst, $src}", []>;
178def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
179                 "mov{q}\t{$src, $dst|$dst, $src}", []>;
180
181//===----------------------------------------------------------------------===//
182// Segmentation support instructions.
183
184def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", []>, TB;
185
186def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
187                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
188def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
189                "lar{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
190
191// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
192def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
193                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
194def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
195                "lar{l}\t{$src, $dst|$dst, $src}", []>, TB;
196// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
197def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
198                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
199def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
200                 "lar{q}\t{$src, $dst|$dst, $src}", []>, TB;
201
202def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
203                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
204def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
205                "lsl{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
206def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
207                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
208def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
209                "lsl{l}\t{$src, $dst|$dst, $src}", []>, TB;
210def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
211                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
212def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
213                 "lsl{q}\t{$src, $dst|$dst, $src}", []>, TB;
214
215def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr", []>, TB;
216
217def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
218               "str{w}\t{$dst}", []>, TB, OpSize;
219def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
220               "str{l}\t{$dst}", []>, TB;
221def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
222                "str{q}\t{$dst}", []>, TB;
223def STRm   : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
224               "str{w}\t{$dst}", []>, TB;
225
226def LTRr : I<0x00, MRM3r, (outs), (ins GR16:$src),
227             "ltr{w}\t{$src}", []>, TB;
228def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
229             "ltr{w}\t{$src}", []>, TB;
230
231def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
232                 "push{w}\t{%cs|CS}", []>, Requires<[In32BitMode]>, OpSize;
233def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
234                 "push{l}\t{%cs|CS}", []>, Requires<[In32BitMode]>;
235def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
236                 "push{w}\t{%ss|SS}", []>, Requires<[In32BitMode]>, OpSize;
237def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
238                 "push{l}\t{%ss|SS}", []>, Requires<[In32BitMode]>;
239def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
240                 "push{w}\t{%ds|DS}", []>, Requires<[In32BitMode]>, OpSize;
241def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
242                 "push{l}\t{%ds|DS}", []>, Requires<[In32BitMode]>;
243def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
244                 "push{w}\t{%es|ES}", []>, Requires<[In32BitMode]>, OpSize;
245def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
246                 "push{l}\t{%es|ES}", []>, Requires<[In32BitMode]>;
247
248def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
249                 "push{w}\t{%fs|FS}", []>, OpSize, TB;
250def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
251                 "push{l}\t{%fs|FS}", []>, TB, Requires<[In32BitMode]>;
252def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
253                 "push{w}\t{%gs|GS}", []>, OpSize, TB;
254def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
255                 "push{l}\t{%gs|GS}", []>, TB, Requires<[In32BitMode]>;
256
257def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
258                 "push{q}\t{%fs|FS}", []>, TB;
259def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
260                 "push{q}\t{%gs|GS}", []>, TB;
261
262// No "pop cs" instruction.
263def POPSS16 : I<0x17, RawFrm, (outs), (ins),
264                "pop{w}\t{%ss|SS}", []>, OpSize, Requires<[In32BitMode]>;
265def POPSS32 : I<0x17, RawFrm, (outs), (ins),
266                "pop{l}\t{%ss|SS}", []>        , Requires<[In32BitMode]>;
267
268def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
269                "pop{w}\t{%ds|DS}", []>, OpSize, Requires<[In32BitMode]>;
270def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
271                "pop{l}\t{%ds|DS}", []>        , Requires<[In32BitMode]>;
272
273def POPES16 : I<0x07, RawFrm, (outs), (ins),
274                "pop{w}\t{%es|ES}", []>, OpSize, Requires<[In32BitMode]>;
275def POPES32 : I<0x07, RawFrm, (outs), (ins),
276                "pop{l}\t{%es|ES}", []>        , Requires<[In32BitMode]>;
277
278def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
279                "pop{w}\t{%fs|FS}", []>, OpSize, TB;
280def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
281                "pop{l}\t{%fs|FS}", []>, TB    , Requires<[In32BitMode]>;
282def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
283                "pop{q}\t{%fs|FS}", []>, TB;
284
285def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
286                "pop{w}\t{%gs|GS}", []>, OpSize, TB;
287def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
288                "pop{l}\t{%gs|GS}", []>, TB    , Requires<[In32BitMode]>;
289def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
290                "pop{q}\t{%gs|GS}", []>, TB;
291
292
293def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
294                "lds{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
295def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
296                "lds{l}\t{$src, $dst|$dst, $src}", []>;
297
298def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
299                "lss{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
300def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
301                "lss{l}\t{$src, $dst|$dst, $src}", []>, TB;
302def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
303                 "lss{q}\t{$src, $dst|$dst, $src}", []>, TB;
304
305def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
306                "les{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
307def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
308                "les{l}\t{$src, $dst|$dst, $src}", []>;
309
310def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
311                "lfs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
312def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
313                "lfs{l}\t{$src, $dst|$dst, $src}", []>, TB;
314def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
315                 "lfs{q}\t{$src, $dst|$dst, $src}", []>, TB;
316
317def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
318                "lgs{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
319def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
320                "lgs{l}\t{$src, $dst|$dst, $src}", []>, TB;
321
322def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
323                 "lgs{q}\t{$src, $dst|$dst, $src}", []>, TB;
324
325
326def VERRr : I<0x00, MRM4r, (outs), (ins GR16:$seg),
327              "verr\t$seg", []>, TB;
328def VERRm : I<0x00, MRM4m, (outs), (ins i16mem:$seg),
329              "verr\t$seg", []>, TB;
330def VERWr : I<0x00, MRM5r, (outs), (ins GR16:$seg),
331              "verw\t$seg", []>, TB;
332def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
333              "verw\t$seg", []>, TB;
334
335//===----------------------------------------------------------------------===//
336// Descriptor-table support instructions
337
338def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
339              "sgdtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
340def SGDTm : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
341              "sgdt\t$dst", []>, TB;
342def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
343              "sidtw\t$dst", []>, TB, OpSize, Requires<[In32BitMode]>;
344def SIDTm : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
345              "sidt\t$dst", []>, TB;
346def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
347                "sldt{w}\t$dst", []>, TB, OpSize;
348def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
349                "sldt{w}\t$dst", []>, TB;
350def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
351                "sldt{l}\t$dst", []>, TB;
352
353// LLDT is not interpreted specially in 64-bit mode because there is no sign
354//   extension.
355def SLDT64r : RI<0x00, MRM0r, (outs GR64:$dst), (ins),
356                 "sldt{q}\t$dst", []>, TB;
357def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
358                 "sldt{q}\t$dst", []>, TB;
359
360def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
361              "lgdtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
362def LGDTm : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
363              "lgdt\t$src", []>, TB;
364def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
365              "lidtw\t$src", []>, TB, OpSize, Requires<[In32BitMode]>;
366def LIDTm : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
367              "lidt\t$src", []>, TB;
368def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
369                "lldt{w}\t$src", []>, TB;
370def LLDT16m : I<0x00, MRM2m, (outs), (ins i16mem:$src),
371                "lldt{w}\t$src", []>, TB;
372
373//===----------------------------------------------------------------------===//
374// Specialized register support
375def WRMSR : I<0x30, RawFrm, (outs), (ins), "wrmsr", []>, TB;
376def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", []>, TB;
377def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;
378
379def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
380                "smsw{w}\t$dst", []>, OpSize, TB;
381def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
382                "smsw{l}\t$dst", []>, TB;
383// no m form encodable; use SMSW16m
384def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
385                 "smsw{q}\t$dst", []>, TB;
386
387// For memory operands, there is only a 16-bit form
388def SMSW16m : I<0x01, MRM4m, (outs i16mem:$dst), (ins),
389                "smsw{w}\t$dst", []>, TB;
390
391def LMSW16r : I<0x01, MRM6r, (outs), (ins GR16:$src),
392                "lmsw{w}\t$src", []>, TB;
393def LMSW16m : I<0x01, MRM6m, (outs), (ins i16mem:$src),
394                "lmsw{w}\t$src", []>, TB;
395
396def CPUID : I<0xA2, RawFrm, (outs), (ins), "cpuid", []>, TB;
397
398//===----------------------------------------------------------------------===//
399// Cache instructions
400def INVD : I<0x08, RawFrm, (outs), (ins), "invd", []>, TB;
401def WBINVD : I<0x09, RawFrm, (outs), (ins), "wbinvd", []>, TB;
402
403//===----------------------------------------------------------------------===//
404// XSAVE instructions
405let Defs = [RDX, RAX], Uses = [RCX] in
406  def XGETBV : I<0x01, MRM_D0, (outs), (ins), "xgetbv", []>, TB;
407
408let Uses = [RDX, RAX, RCX] in
409  def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
410
411let Uses = [RDX, RAX] in {
412  def XSAVE : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
413               "xsave\t$dst", []>, TB;
414  def XSAVE64 : I<0xAE, MRM4m, (outs opaque512mem:$dst), (ins),
415                 "xsaveq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
416  def XRSTOR : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
417               "xrstor\t$dst", []>, TB;
418  def XRSTOR64 : I<0xAE, MRM5m, (outs), (ins opaque512mem:$dst),
419                 "xrstorq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
420  def XSAVEOPT : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
421                  "xsaveopt\t$dst", []>, TB;
422  def XSAVEOPT64 : I<0xAE, MRM6m, (outs opaque512mem:$dst), (ins),
423                    "xsaveoptq\t$dst", []>, TB, REX_W, Requires<[In64BitMode]>;
424}
425
426//===----------------------------------------------------------------------===//
427// VIA PadLock crypto instructions
428let Defs = [RAX, RDI], Uses = [RDX, RDI] in
429  def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
430
431def : InstAlias<"xstorerng", (XSTORE)>;
432
433let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
434  def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
435  def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
436  def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
437  def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
438  def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
439}
440
441let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
442  def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
443  def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
444}
445let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
446  def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;
447
448//===----------------------------------------------------------------------===//
449// FS/GS Base Instructions
450let Predicates = [In64BitMode] in {
451  def RDFSBASE : I<0xAE, MRM0r, (outs GR32:$dst), (ins),
452                   "rdfsbase{l}\t$dst", []>, TB, XS;
453  def RDFSBASE64 : RI<0xAE, MRM0r, (outs GR64:$dst), (ins),
454                     "rdfsbase{q}\t$dst", []>, TB, XS;
455  def RDGSBASE : I<0xAE, MRM1r, (outs GR32:$dst), (ins),
456                   "rdgsbase{l}\t$dst", []>, TB, XS;
457  def RDGSBASE64 : RI<0xAE, MRM1r, (outs GR64:$dst), (ins),
458                     "rdgsbase{q}\t$dst", []>, TB, XS;
459  def WRFSBASE : I<0xAE, MRM2r, (outs), (ins GR32:$dst),
460                   "wrfsbase{l}\t$dst", []>, TB, XS;
461  def WRFSBASE64 : RI<0xAE, MRM2r, (outs), (ins GR64:$dst),
462                   "wrfsbase{q}\t$dst", []>, TB, XS;
463  def WRGSBASE : I<0xAE, MRM3r, (outs), (ins GR32:$dst),
464                   "wrgsbase{l}\t$dst", []>, TB, XS;
465  def WRGSBASE64 : RI<0xAE, MRM3r, (outs), (ins GR64:$dst),
466                    "wrgsbase{q}\t$dst", []>, TB, XS;
467}
468