| /external/llvm/lib/CodeGen/ |
| D | InlineSpiller.cpp | 89 bool isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, MachineBasicBlock &BB,
104 void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
1080 bool HoistSpillHelper::isSpillCandBB(unsigned OrigReg, VNInfo &OrigVNI, in isSpillCandBB() argument
1083 LiveInterval &OrigLI = LIS.getInterval(OrigReg); in isSpillCandBB()
1089 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
1090 assert((LIS.getInterval(OrigReg)).getVNInfoAt(Idx) == &OrigVNI && in isSpillCandBB()
1229 unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills, in runHoistSpills() argument
1304 if (!isSpillCandBB(OrigReg, OrigVNI, *Block, LiveReg)) in runHoistSpills()
1384 unsigned OrigReg = SlotToOrigReg[Slot]; in hoistAllSpills() local
1385 LiveInterval &OrigLI = LIS.getInterval(OrigReg); in hoistAllSpills()
[all …]
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| D | TailDuplicator.cpp | 287 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, in addSSAUpdateEntry() argument
290 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
296 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
297 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
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| D | SplitKit.cpp | 316 unsigned OrigReg = VRM.getOriginal(CurLI->reg); in isOriginalEndpoint() local
317 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
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| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| D | MipsFrameLowering.cpp | 109 static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm, in expandRegLargeImmPair() argument
115 NewReg = OrigReg; in expandRegLargeImmPair()
130 BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg) in expandRegLargeImmPair()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | TailDuplication.cpp | 80 void AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
359 void TailDuplicatePass::AddSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, in AddSSAUpdateEntry() argument
361 DenseMap<unsigned, AvailableValsTy>::iterator LI= SSAUpdateVals.find(OrigReg); in AddSSAUpdateEntry()
367 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in AddSSAUpdateEntry()
368 SSAUpdateVRs.push_back(OrigReg); in AddSSAUpdateEntry()
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| D | SplitKit.cpp | 277 unsigned OrigReg = VRM.getOriginal(CurLI->reg); in isOriginalEndpoint() local
278 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
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| /external/llvm/include/llvm/CodeGen/ |
| D | TailDuplicator.h | 60 void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 557 unsigned OrigReg = U.getReg(); in colorChain() local
558 U.setReg(Substs[OrigReg]); in colorChain()
562 ToErase.push_back(OrigReg); in colorChain()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64A57FPLoadBalancing.cpp | 570 unsigned OrigReg = U.getReg(); in colorChain() local
571 U.setReg(Substs[OrigReg]); in colorChain()
575 ToErase.push_back(OrigReg); in colorChain()
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TailDuplicator.h | 93 void addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg,
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | TailDuplicator.cpp | 323 void TailDuplicator::addSSAUpdateEntry(unsigned OrigReg, unsigned NewReg, in addSSAUpdateEntry() argument
326 SSAUpdateVals.find(OrigReg); in addSSAUpdateEntry()
332 SSAUpdateVals.insert(std::make_pair(OrigReg, Vals)); in addSSAUpdateEntry()
333 SSAUpdateVRs.push_back(OrigReg); in addSSAUpdateEntry()
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| D | InlineSpiller.cpp | 1142 unsigned OrigReg = OrigLI.reg; in isSpillCandBB() local
1148 SmallSetVector<unsigned, 16> &Siblings = Virt2SiblingsMap[OrigReg]; in isSpillCandBB()
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| D | SplitKit.cpp | 342 unsigned OrigReg = VRM.getOriginal(CurLI->reg); in isOriginalEndpoint() local
343 const LiveInterval &Orig = LIS.getInterval(OrigReg); in isOriginalEndpoint()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | RegisterBankInfo.cpp | 433 unsigned OrigReg = MO.getReg(); in applyDefaultMapping() local
435 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
441 LLT OrigTy = MRI.getType(OrigReg); in applyDefaultMapping()
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| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 2690 const SCEV *OrigReg; member
2693 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
2702 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
2754 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
2757 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
2759 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
2761 DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg << '\n'); in GenerateCrossUseConstantOffsets()
2781 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
2798 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
2800 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
[all …]
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 3623 const SCEV *OrigReg; member
3626 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
3635 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
3682 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
3685 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
3687 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
3689 DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg << '\n'); in GenerateCrossUseConstantOffsets()
3710 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
3725 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
3727 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 3959 const SCEV *OrigReg; member
3962 : LUIdx(LI), Imm(I), OrigReg(R) {} in WorkItem()
3972 OS << "in formulae referencing " << *OrigReg << " in use " << LUIdx in print()
4021 const SCEV *OrigReg = J->second; in GenerateCrossUseConstantOffsets() local
4024 const SmallBitVector &UsedByIndices = RegUses.getUsedByIndices(OrigReg); in GenerateCrossUseConstantOffsets()
4026 if (!isa<SCEVConstant>(OrigReg) && in GenerateCrossUseConstantOffsets()
4028 LLVM_DEBUG(dbgs() << "Skipping cross-use reuse for " << *OrigReg in GenerateCrossUseConstantOffsets()
4049 WorkItems.push_back(WorkItem(LUIdx, Imm, OrigReg)); in GenerateCrossUseConstantOffsets()
4064 const SCEV *OrigReg = WI.OrigReg; in GenerateCrossUseConstantOffsets() local
4066 Type *IntTy = SE.getEffectiveSCEVType(OrigReg->getType()); in GenerateCrossUseConstantOffsets()
[all …]
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| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1078 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1084 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1089 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1091 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1093 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1103 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86AsmParser.cpp | 1279 unsigned OrigReg = OrigOp.Mem.BaseReg; in VerifyAndAdjustOperands() local
1285 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) { in VerifyAndAdjustOperands()
1290 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1292 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1294 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg)) in VerifyAndAdjustOperands()
1304 if (FinalReg != OrigReg) { in VerifyAndAdjustOperands()
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