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Searched refs:PPC (Results 1 – 25 of 316) sorted by relevance

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/external/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
71 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
72 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
73 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
74 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
75 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
76 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
77 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
78 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/
DPPCDisassembler.cpp66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
67 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
71 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
72 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
73 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
74 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
75 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
76 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
77 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
78 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
[all …]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
21 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
22 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
23 case PPC::PRED_LT: return PPC::PRED_GE; in InvertPredicate()
24 case PPC::PRED_GE: return PPC::PRED_LT; in InvertPredicate()
25 case PPC::PRED_GT: return PPC::PRED_LE; in InvertPredicate()
26 case PPC::PRED_LE: return PPC::PRED_GT; in InvertPredicate()
27 case PPC::PRED_NU: return PPC::PRED_UN; in InvertPredicate()
28 case PPC::PRED_UN: return PPC::PRED_NU; in InvertPredicate()
29 case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS; in InvertPredicate()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCPredicates.cpp19 PPC::Predicate PPC::InvertPredicate(PPC::Predicate Opcode) { in InvertPredicate()
21 case PPC::PRED_EQ: return PPC::PRED_NE; in InvertPredicate()
22 case PPC::PRED_NE: return PPC::PRED_EQ; in InvertPredicate()
23 case PPC::PRED_LT: return PPC::PRED_GE; in InvertPredicate()
24 case PPC::PRED_GE: return PPC::PRED_LT; in InvertPredicate()
25 case PPC::PRED_GT: return PPC::PRED_LE; in InvertPredicate()
26 case PPC::PRED_LE: return PPC::PRED_GT; in InvertPredicate()
27 case PPC::PRED_NU: return PPC::PRED_UN; in InvertPredicate()
28 case PPC::PRED_UN: return PPC::PRED_NU; in InvertPredicate()
29 case PPC::PRED_EQ_MINUS: return PPC::PRED_NE_PLUS; in InvertPredicate()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.cpp72 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
76 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
77 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
78 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
79 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
80 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
81 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
82 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
83 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
86 ImmToIdxMap[PPC::LHA8] = PPC::LHAX8; ImmToIdxMap[PPC::LBZ8] = PPC::LBZX8; in PPCRegisterInfo()
[all …]
DPPCFrameLowering.h118 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; in getCalleeSavedSpillSlots()
121 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
134 {PPC::F31, -8}, in getCalleeSavedSpillSlots()
135 {PPC::F30, -16}, in getCalleeSavedSpillSlots()
136 {PPC::F29, -24}, in getCalleeSavedSpillSlots()
137 {PPC::F28, -32}, in getCalleeSavedSpillSlots()
138 {PPC::F27, -40}, in getCalleeSavedSpillSlots()
139 {PPC::F26, -48}, in getCalleeSavedSpillSlots()
140 {PPC::F25, -56}, in getCalleeSavedSpillSlots()
141 {PPC::F24, -64}, in getCalleeSavedSpillSlots()
[all …]
DPPCHazardRecognizers.cpp166 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4)) in getHazardType()
175 case PPC::LBZ: case PPC::LBZU: in getHazardType()
176 case PPC::LBZX: in getHazardType()
177 case PPC::LBZ8: case PPC::LBZU8: in getHazardType()
178 case PPC::LBZX8: in getHazardType()
179 case PPC::LVEBX: in getHazardType()
182 case PPC::LHA: case PPC::LHAU: in getHazardType()
183 case PPC::LHAX: in getHazardType()
184 case PPC::LHZ: case PPC::LHZU: in getHazardType()
185 case PPC::LHZX: in getHazardType()
[all …]
DPPCInstrInfo.cpp44 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), in PPCInstrInfo()
63 case PPC::LD: in isLoadFromStackSlot()
64 case PPC::LWZ: in isLoadFromStackSlot()
65 case PPC::LFS: in isLoadFromStackSlot()
66 case PPC::LFD: in isLoadFromStackSlot()
81 case PPC::STD: in isStoreToStackSlot()
82 case PPC::STW: in isStoreToStackSlot()
83 case PPC::STFS: in isStoreToStackSlot()
84 case PPC::STFD: in isStoreToStackSlot()
102 if (MI->getOpcode() != PPC::RLWIMI) in commuteInstruction()
[all …]
DPPCFrameLowering.cpp42 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
43 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
44 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
45 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
59 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); in RemoveVRSaveCode()
71 if (MBBI->getOpcode() == PPC::MTVRSAVE) { in RemoveVRSaveCode()
87 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); in RemoveVRSaveCode()
136 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
140 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
145 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp102 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP, in PPCInstrInfo()
104 STI.isPPC64() ? PPC::BLR8 : PPC::BLR), in PPCInstrInfo()
114 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
115 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
133 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
137 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
138 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
194 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
195 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
197 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
[all …]
DPPCRegisterInfo.cpp75 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
79 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
80 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
81 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
82 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
83 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
84 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
85 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
86 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
87 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
[all …]
DPPCFrameLowering.cpp34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; in getCalleeSavedSpillSlots()
100 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
116 {PPC::F31, -8}, in getCalleeSavedSpillSlots()
117 {PPC::F30, -16}, in getCalleeSavedSpillSlots()
118 {PPC::F29, -24}, in getCalleeSavedSpillSlots()
119 {PPC::F28, -32}, in getCalleeSavedSpillSlots()
[all …]
DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
[all …]
DPPCVSXSwapRemoval.cpp173 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
174 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
179 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
180 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
292 case PPC::XXPERMDI: { in gatherVectorInstructions()
341 case PPC::LVX: in gatherVectorInstructions()
348 case PPC::LXVD2X: in gatherVectorInstructions()
349 case PPC::LXVW4X: in gatherVectorInstructions()
355 case PPC::LXSDX: in gatherVectorInstructions()
356 case PPC::LXSSPX: in gatherVectorInstructions()
[all …]
DPPCMIPeephole.cpp144 if (Opcode == PPC::RLDICL || Opcode == PPC::RLDICLo || in getKnownLeadingZeroCount()
145 Opcode == PPC::RLDCL || Opcode == PPC::RLDCLo) in getKnownLeadingZeroCount()
148 if ((Opcode == PPC::RLDIC || Opcode == PPC::RLDICo) && in getKnownLeadingZeroCount()
152 if ((Opcode == PPC::RLWINM || Opcode == PPC::RLWINMo || in getKnownLeadingZeroCount()
153 Opcode == PPC::RLWNM || Opcode == PPC::RLWNMo || in getKnownLeadingZeroCount()
154 Opcode == PPC::RLWINM8 || Opcode == PPC::RLWNM8) && in getKnownLeadingZeroCount()
158 if (Opcode == PPC::ANDIo) { in getKnownLeadingZeroCount()
163 if (Opcode == PPC::CNTLZW || Opcode == PPC::CNTLZWo || in getKnownLeadingZeroCount()
164 Opcode == PPC::CNTTZW || Opcode == PPC::CNTTZWo || in getKnownLeadingZeroCount()
165 Opcode == PPC::CNTLZW8 || Opcode == PPC::CNTTZW8) in getKnownLeadingZeroCount()
[all …]
DPPCFastISel.cpp150 return RC->getID() == PPC::VSFRCRegClassID; in isVSFRCRegClass()
153 return RC->getID() == PPC::VSSRCRegClassID; in isVSSRCRegClass()
157 const PPC::Predicate Pred);
160 unsigned FP64LoadOpc = PPC::LFD);
216 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) { in getComparePred()
244 return Optional<PPC::Predicate>(); in getComparePred()
248 return PPC::PRED_EQ; in getComparePred()
253 return PPC::PRED_GT; in getComparePred()
258 return PPC::PRED_GE; in getComparePred()
263 return PPC::PRED_LT; in getComparePred()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 PPC::ZERO,
46 PPC::R1, PPC::R2, PPC::R3,
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp68 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), in PPCInstrInfo()
78 if (Directive == PPC::DIR_440 || Directive == PPC::DIR_A2 || in CreateTargetHazardRecognizer()
79 Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500) { in CreateTargetHazardRecognizer()
97 if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8) in CreateTargetPostRAHazardRecognizer()
101 if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 && in CreateTargetPostRAHazardRecognizer()
102 Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) { in CreateTargetPostRAHazardRecognizer()
158 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || in getOperandLatency()
159 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); in getOperandLatency()
161 IsRegCR = PPC::CRRCRegClass.contains(Reg) || in getOperandLatency()
162 PPC::CRBITRCRegClass.contains(Reg); in getOperandLatency()
[all …]
DPPCRegisterInfo.cpp61 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR, in PPCRegisterInfo()
65 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; in PPCRegisterInfo()
66 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; in PPCRegisterInfo()
67 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; in PPCRegisterInfo()
68 ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX; in PPCRegisterInfo()
69 ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX; in PPCRegisterInfo()
70 ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX; in PPCRegisterInfo()
71 ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX; in PPCRegisterInfo()
72 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
73 ImmToIdxMap[PPC::LWA_32] = PPC::LWAX_32; in PPCRegisterInfo()
[all …]
DPPCFrameLowering.cpp34 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
35 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
36 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
37 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 static const SpillSlot darwin64Offsets = {PPC::X31, -8}; in getCalleeSavedSpillSlots()
100 static const SpillSlot darwinOffsets = {PPC::R31, -4}; in getCalleeSavedSpillSlots()
116 {PPC::F31, -8}, in getCalleeSavedSpillSlots()
117 {PPC::F30, -16}, in getCalleeSavedSpillSlots()
118 {PPC::F29, -24}, in getCalleeSavedSpillSlots()
119 {PPC::F28, -32}, in getCalleeSavedSpillSlots()
[all …]
DPPCRegisterInfo.h28 if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT || in getCRFromCRBit()
29 SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN) in getCRFromCRBit()
30 Reg = PPC::CR0; in getCRFromCRBit()
31 else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT || in getCRFromCRBit()
32 SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN) in getCRFromCRBit()
33 Reg = PPC::CR1; in getCRFromCRBit()
34 else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT || in getCRFromCRBit()
35 SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN) in getCRFromCRBit()
36 Reg = PPC::CR2; in getCRFromCRBit()
37 else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT || in getCRFromCRBit()
[all …]
DPPCVSXSwapRemoval.cpp172 return (isRegInClass(Reg, &PPC::VSRCRegClass) || in isVecReg()
173 isRegInClass(Reg, &PPC::VRRCRegClass)); in isVecReg()
178 return (isRegInClass(Reg, &PPC::VSFRCRegClass) || in isScalarVecReg()
179 isRegInClass(Reg, &PPC::VSSRCRegClass)); in isScalarVecReg()
289 case PPC::XXPERMDI: { in gatherVectorInstructions()
338 case PPC::LVX: in gatherVectorInstructions()
345 case PPC::LXVD2X: in gatherVectorInstructions()
346 case PPC::LXVW4X: in gatherVectorInstructions()
352 case PPC::LXSDX: in gatherVectorInstructions()
353 case PPC::LXSSPX: in gatherVectorInstructions()
[all …]
/external/llvm/lib/Target/PowerPC/AsmParser/
DPPCAsmParser.cpp35 PPC::R0, PPC::R1, PPC::R2, PPC::R3,
36 PPC::R4, PPC::R5, PPC::R6, PPC::R7,
37 PPC::R8, PPC::R9, PPC::R10, PPC::R11,
38 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42 PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 PPC::ZERO,
46 PPC::R1, PPC::R2, PPC::R3,
[all …]
/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp59 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
82 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
92 if (MI->getOpcode() == PPC::RLDICR) { in printInst()
115 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) { in printInst()
118 if (MI->getOpcode() == PPC::DCBTST) in printInst()
124 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; in printInst()
151 switch ((PPC::Predicate)Code) { in printPredicateOperand()
152 case PPC::PRED_LT_MINUS: in printPredicateOperand()
153 case PPC::PRED_LT_PLUS: in printPredicateOperand()
154 case PPC::PRED_LT: in printPredicateOperand()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp71 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
94 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
104 if (MI->getOpcode() == PPC::RLDICR || in printInst()
105 MI->getOpcode() == PPC::RLDICR_32) { in printInst()
128 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) { in printInst()
131 if (MI->getOpcode() == PPC::DCBTST) in printInst()
137 bool IsBookE = STI.getFeatureBits()[PPC::FeatureBookE]; in printInst()
152 if (MI->getOpcode() == PPC::DCBF) { in printInst()
183 switch ((PPC::Predicate)Code) { in printPredicateOperand()
184 case PPC::PRED_LT_MINUS: in printPredicateOperand()
[all …]

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