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Searched refs:PTU (Results 1 – 25 of 37) sorted by relevance

12

/external/u-boot/board/gumstix/duovero/
Dduovero_mux_data.h13 {SDMMC1_CLK, (PTU | OFF_EN | OFF_OUT_PTD | M0)}, /* sdmmc1_clk */
14 {SDMMC1_CMD, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_cmd */
15 {SDMMC1_DAT0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat0 */
16 {SDMMC1_DAT1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat1 */
17 {SDMMC1_DAT2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat2 */
18 {SDMMC1_DAT3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M0)}, /* sdmmc1_dat3 */
19 {I2C1_SCL, (PTU | IEN | M0)}, /* i2c1_scl */
20 {I2C1_SDA, (PTU | IEN | M0)}, /* i2c1_sda */
21 {I2C2_SCL, (PTU | IEN | M0)}, /* i2c2_scl */
22 {I2C2_SDA, (PTU | IEN | M0)}, /* i2c2_sda */
[all …]
/external/u-boot/board/compulab/cm_t54/
Dmux.c18 {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
19 {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
20 {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0 */
21 {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1 */
22 {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2 */
23 {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3 */
26 {TIMER5_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_228 */
27 {TIMER6_PWM_EVT, (PTU | IEN | M6)}, /* GPIO8_229 */
30 {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
31 {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
[all …]
/external/u-boot/board/ti/omap5_uevm/
Dmux_data.h15 {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
16 {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
17 {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
18 {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
19 {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
20 {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
21 {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
22 {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
23 {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
24 {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
[all …]
/external/u-boot/board/ti/panda/
Dpanda_mux_data.h17 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
18 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
19 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
20 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
21 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
22 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
23 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
24 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
25 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
26 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
[all …]
/external/u-boot/board/overo/
Dovero.h40 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
41 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
42 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
44 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4)) /*GPIO_63*/\
46 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
48 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | DIS | M4)) /*GPIO_65*/\
91 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M4)) /*GPIO_150-MMC3_WP*/\
95 MUX_VAL(CP(HDQ_SIO), (IDIS | PTU | EN | M4)) /*HDQ_SIO*/\
101 MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176 */\
104 MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTU | EN | M4)) /*GPIO_10*/\
[all …]
Dcommon.c81 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
82 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
83 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
84 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
85 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
86 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
87 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
88 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
89 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
90 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/ti/sdp4430/
Dsdp4430_mux_data.h16 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
17 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
18 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
19 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
20 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
21 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
22 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
23 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
24 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
25 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cmd */
[all …]
/external/u-boot/board/amazon/kc1/
Dkc1.h21 { GPMC_AD0, (IEN | PTU | M1) }, /* sdmmc2_dat0 */
22 { GPMC_AD1, (IEN | PTU | M1) }, /* sdmmc2_dat1 */
23 { GPMC_AD2, (IEN | PTU | M1) }, /* sdmmc2_dat2 */
24 { GPMC_AD3, (IEN | PTU | M1) }, /* sdmmc2_dat3 */
25 { GPMC_AD4, (IEN | PTU | M1) }, /* sdmmc2_dat4 */
26 { GPMC_AD5, (IEN | PTU | M1) }, /* sdmmc2_dat5 */
27 { GPMC_AD6, (IEN | PTU | M1) }, /* sdmmc2_dat6 */
28 { GPMC_AD7, (IEN | PTU | M1) }, /* sdmmc2_dat7 */
29 { GPMC_NOE, (IEN | PTU | M1) }, /* sdmmc2_clk */
30 { GPMC_NWE, (IEN | PTU | M1) }, /* sdmmc2_cmd */
[all …]
/external/u-boot/board/technexion/tao3530/
Dtao3530.h69 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
70 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
71 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
72 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
73 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
74 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
75 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
76 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/compulab/cm_t3517/
Dmux.c53 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
57 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
58 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
59 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
60 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
61 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
62 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
63 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
64 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
65 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); in set_muxconf_regs()
[all …]
/external/u-boot/board/technexion/twister/
Dtwister.h91 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
96 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
97 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
98 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
99 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
100 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/htkw/mcx/
Dmcx.h77 MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \
78 MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \
79 MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \
80 MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \
81 MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \
82 MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \
83 MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \
84 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \
85 MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \
86 MUX_VAL(CP(GPMC_A10), (IEN | PTU | EN | M4)) \
[all …]
/external/u-boot/board/teejet/mt_ventoux/
Dmt_ventoux.h87 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
91 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
92 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
93 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
94 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
95 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
96 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/quipos/cairo/
Dcairo.h51 MUX_VAL(CONTROL_PADCONF_CAM_STROBE, (IDIS | PTU | EN | SB_HI | SB_PU | M4)) \
77 MUX_VAL(CONTROL_PADCONF_DSS_DATA20, (IDIS | PTU | EN | M0)) \
81 MUX_VAL(CONTROL_PADCONF_DSS_HSYNC, (IDIS | PTU | EN | M0)) \
82 MUX_VAL(CONTROL_PADCONF_DSS_PCLK, (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CONTROL_PADCONF_DSS_VSYNC, (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CONTROL_PADCONF_ETK_CLK_ES2, (IDIS | PTU | EN | M3)) \
85 MUX_VAL(CONTROL_PADCONF_ETK_CTL_ES2, (IDIS | PTU | EN | M3)) \
86 MUX_VAL(CONTROL_PADCONF_ETK_D0_ES2, (IEN | PTU | EN | M3)) \
87 MUX_VAL(CONTROL_PADCONF_ETK_D1_ES2, (IEN | PTU | EN | M3)) \
88 MUX_VAL(CONTROL_PADCONF_ETK_D2_ES2, (IEN | PTU | EN | M3)) \
[all …]
/external/u-boot/board/8dtech/eco5pk/
Deco5pk.h79 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
80 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
81 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
82 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/ti/beagle/
Dbeagle.h104 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
105 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
106 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
107 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
108 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
111 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
113 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
114 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
121 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
122 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
[all …]
/external/u-boot/board/logicpd/am3517evm/
Dam3517evm.h82 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) \
83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) \
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) \
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) \
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) \
87 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) \
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) \
89 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) \
90 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) \
91 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) \
[all …]
/external/u-boot/board/ti/evm/
Devm.h88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)) /*GPMC_A1*/\
89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)) /*GPMC_A2*/\
90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)) /*GPMC_A3*/\
91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)) /*GPMC_A4*/\
92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)) /*GPMC_A5*/\
93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)) /*GPMC_A6*/\
94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)) /*GPMC_A7*/\
95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)) /*GPMC_A8*/\
96 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)) /*GPMC_A9*/\
97 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0)) /*GPMC_A10*/\
[all …]
/external/u-boot/board/logicpd/omap3som/
Domap3logic.h85 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ in set_muxconf_regs()
86 MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | DIS | M0)); /*SDRC_CKE1*/ in set_muxconf_regs()
88 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in set_muxconf_regs()
89 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in set_muxconf_regs()
90 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in set_muxconf_regs()
91 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in set_muxconf_regs()
92 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in set_muxconf_regs()
93 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in set_muxconf_regs()
94 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in set_muxconf_regs()
95 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in set_muxconf_regs()
[all …]
/external/u-boot/board/nokia/rx51/
Drx51.h100 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
101 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
102 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
103 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
104 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
107 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*nDMA_REQ3*/\
109 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
110 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
117 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
118 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
[all …]
/external/u-boot/board/compulab/cm_t35/
Dcm_t35.c165 MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)); /*SDRC_CKE0*/ in cm_t3x_set_common_muxconf()
169 MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0)); /*GPMC_A1*/ in cm_t3x_set_common_muxconf()
170 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0)); /*GPMC_A2*/ in cm_t3x_set_common_muxconf()
171 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0)); /*GPMC_A3*/ in cm_t3x_set_common_muxconf()
172 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0)); /*GPMC_A4*/ in cm_t3x_set_common_muxconf()
173 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0)); /*GPMC_A5*/ in cm_t3x_set_common_muxconf()
174 MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0)); /*GPMC_A6*/ in cm_t3x_set_common_muxconf()
175 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0)); /*GPMC_A7*/ in cm_t3x_set_common_muxconf()
176 MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0)); /*GPMC_A8*/ in cm_t3x_set_common_muxconf()
177 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0)); /*GPMC_A9*/ in cm_t3x_set_common_muxconf()
[all …]
/external/u-boot/board/ti/am3517crane/
Dam3517crane.h83 MUX_VAL(CP(GPMC_A2), (IDIS | PTU | DIS | M4))\
84 MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M4))\
85 MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M4))\
86 MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M4))\
88 MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M4))\
89 MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4))\
92 MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0))\
93 MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0))\
94 MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0))\
95 MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0))\
[all …]
/external/u-boot/board/corscience/tricorder/
Dtricorder.h77 MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\
78 MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\
95 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
96 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
97 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
98 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
99 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
100 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
101 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
102 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
[all …]
/external/u-boot/board/timll/devkit8000/
Ddevkit8000.h98 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0 NAND*/\
99 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
100 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
101 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
102 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
103 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
104 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6 DM9000*/\
105 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
107 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\
108 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\
[all …]
/external/u-boot/board/isee/igep00x0/
Digep00x0.h83 MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /* GPMC_nCS0 */\
84 MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /* GPMC_nCS1 */\
85 MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /* GPIO_nCS2 */\
86 MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /* GPIO_nCS3 */\
87 MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /* GPMC_nCS4 */\
88 MUX_VAL(CP(GPMC_NCS5), (IDIS | PTU | EN | M0)) /* GPMC_nCS5 */\
89 MUX_VAL(CP(GPMC_NCS6), (IDIS | PTU | EN | M0)) /* GPMC_nCS6 */\
90 MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | EN | M0)) /* GPMC_nCS7 */\
98 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /* GPMC_WAIT0 */\
99 MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /* MMC1_CLK */\
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