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Searched refs:PopInst (Results 1 – 4 of 4) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp319 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
391 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
394 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
414 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
419 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
424 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
431 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
DR600MachineScheduler.h92 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp318 SUnit *R600SchedStrategy::PopInst(std::vector<SUnit *> &Q, bool AnyALU) { in PopInst() function in R600SchedStrategy
390 SUnit *SlotedSU = PopInst(AvailableAlus[IndexToID[Slot]], AnyAlu); in AttemptFillSlot()
393 SUnit *UnslotedSU = PopInst(AvailableAlus[AluAny], AnyAlu); in AttemptFillSlot()
413 return PopInst(AvailableAlus[AluPredX], false); in pickAlu()
418 return PopInst(AvailableAlus[AluDiscarded], false); in pickAlu()
423 return PopInst(AvailableAlus[AluT_XYZW], false); in pickAlu()
430 return PopInst(AvailableAlus[AluTrans], false); in pickAlu()
DR600MachineScheduler.h90 SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);