| /external/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 226 if (unsigned PrevReg = Result.getRegisterForVar(Var)) in calculateDbgValueHistory() local
227 dropRegDescribedVar(RegVars, PrevReg, Var); in calculateDbgValueHistory()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFISelDAGToDAG.cpp | 615 unsigned PrevReg = -1; in PreprocessTrunc() local
621 PrevReg = MOP.getReg(); in PreprocessTrunc()
622 if (!TargetRegisterInfo::isVirtualRegister(PrevReg)) in PreprocessTrunc()
624 if (!checkLoadDef(PrevReg, match_load_op)) in PreprocessTrunc()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/AsmPrinter/ |
| D | DbgValueHistoryCalculator.cpp | 250 if (unsigned PrevReg = Result.getRegisterForVar(Var)) in calculateDbgValueHistory() local
251 dropRegDescribedVar(RegVars, PrevReg, Var); in calculateDbgValueHistory()
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| /external/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 412 unsigned PrevReg = 0);
2670 unsigned PrevReg = 0; in generateExistingPhis() local
2672 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
2674 Def, NewReg, PrevReg); in generateExistingPhis()
3249 unsigned NewReg, unsigned PrevReg) { in rewriteScheduledInstr() argument
3277 if (PrevReg && InProlog) in rewriteScheduledInstr()
3278 ReplaceReg = PrevReg; in rewriteScheduledInstr()
3279 else if (PrevReg && !Schedule.isLoopCarried(this, *Phi) && in rewriteScheduledInstr()
3281 ReplaceReg = PrevReg; in rewriteScheduledInstr()
3327 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
[all …]
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| D | RegAllocGreedy.cpp | 662 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign() argument
666 if (PhysReg == PrevReg) in canReassign()
682 << PrintReg(PrevReg, TRI) << " to " << PrintReg(PhysReg, TRI) in canReassign()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachinePipeliner.cpp | 450 unsigned PrevReg = 0);
2788 unsigned PrevReg = 0; in generateExistingPhis() local
2790 PrevReg = VRMap[PrevStage - np][LoopVal]; in generateExistingPhis()
2792 Def, NewReg, PrevReg); in generateExistingPhis()
3372 unsigned NewReg, unsigned PrevReg) { in rewriteScheduledInstr() argument
3400 if (PrevReg && InProlog) in rewriteScheduledInstr()
3401 ReplaceReg = PrevReg; in rewriteScheduledInstr()
3402 else if (PrevReg && !Schedule.isLoopCarried(this, *Phi) && in rewriteScheduledInstr()
3404 ReplaceReg = PrevReg; in rewriteScheduledInstr()
3450 unsigned PrevReg = getLoopPhiReg(*Phi, MI->getParent()); in canUseLastOffsetValue() local
[all …]
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| D | RegAllocGreedy.cpp | 466 unsigned canReassign(LiveInterval &VirtReg, unsigned PrevReg);
805 unsigned RAGreedy::canReassign(LiveInterval &VirtReg, unsigned PrevReg) { in canReassign() argument
809 if (PhysReg == PrevReg) in canReassign()
825 << printReg(PrevReg, TRI) << " to " in canReassign()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 528 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
541 PrevReg = MCRegOp; in expandSET()
564 TmpInst.addOperand(PrevReg); in expandSET()
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| /external/llvm/lib/Target/Sparc/AsmParser/ |
| D | SparcAsmParser.cpp | 500 MCOperand PrevReg = MCOperand::createReg(Sparc::G0); in expandSET() local
513 PrevReg = MCRegOp; in expandSET()
536 TmpInst.addOperand(PrevReg); in expandSET()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1119 int PrevReg = *RegList.List->begin(); in isRegList16() local
1122 if ( Reg != PrevReg + 1) in isRegList16()
1124 PrevReg = Reg; in isRegList16()
4647 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
4666 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
4675 PrevReg = TmpReg; in parseRegisterList()
4682 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
4695 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
4719 PrevReg = RegNo; in parseRegisterList()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 2982 int64_t PrevReg = FirstReg; in parseVectorList() local
2997 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg); in parseVectorList()
3020 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) in parseVectorList()
3023 PrevReg = Reg; in parseVectorList()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 1387 int PrevReg = *RegList.List->begin(); in isRegList16() local
1390 if ( Reg != PrevReg + 1) in isRegList16()
1392 PrevReg = Reg; in isRegList16()
6200 unsigned PrevReg = Mips::NoRegister; in parseRegisterList() local
6219 unsigned TmpReg = PrevReg + 1; in parseRegisterList()
6228 PrevReg = TmpReg; in parseRegisterList()
6235 if ((PrevReg == Mips::NoRegister) && in parseRegisterList()
6248 } else if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) && in parseRegisterList()
6272 PrevReg = RegNo; in parseRegisterList()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 3202 int64_t PrevReg = FirstReg; in tryParseVectorList() local
3220 unsigned Space = (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + 32 - PrevReg); in tryParseVectorList()
3246 (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) { in tryParseVectorList()
3251 PrevReg = Reg; in tryParseVectorList()
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