| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| D | SystemZInstrFP.td | 29 def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
33 def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
44 def LD_Fp032 : Pseudo<(outs FP32:$dst), (ins),
47 def LD_Fp064 : Pseudo<(outs FP64:$dst), (ins),
53 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
56 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
62 def FMOV32rm : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
65 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
68 def FMOV64rm : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
71 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
[all …]
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| D | SystemZInstrInfo.td | 71 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
74 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
79 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
83 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
96 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
104 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
[all …]
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| D | SystemZInstrFormats.td | 17 def Pseudo : Format<0>;
125 // Pseudo instructions
128 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
129 : InstSystemZ<0, Pseudo, outs, ins> {
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/BlockFrequencyInfo/ |
| D | double_exit.ll | 16 ; Pseudo-edges = exit
17 ; Pseudo-mass = 1
29 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
30 ; Pseudo-mass = 2/3
89 ; Pseudo-edges = exit
90 ; Pseudo-mass = 1
102 ; Pseudo-edges = outer.inc
103 ; Pseudo-mass = 1/2
115 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
116 ; Pseudo-mass = 2/3
|
| /external/llvm/test/Analysis/BlockFrequencyInfo/ |
| D | double_exit.ll | 16 ; Pseudo-edges = exit
17 ; Pseudo-mass = 1
29 ; Pseudo-edges = outer.inc @ 1/5, exit @ 1/5
30 ; Pseudo-mass = 2/3
89 ; Pseudo-edges = exit
90 ; Pseudo-mass = 1
102 ; Pseudo-edges = outer.inc
103 ; Pseudo-mass = 1/2
115 ; Pseudo-edges = middle.inc @ 1/5, outer.inc @ 1/5
116 ; Pseudo-mass = 2/3
|
| /external/syzkaller/pkg/ifuzz/ |
| D | pseudo.go | 15 Pseudo: true,
28 Pseudo: true,
44 Pseudo: true,
57 Pseudo: true,
71 Pseudo: true,
83 Pseudo: true,
96 Pseudo: true,
117 Pseudo: true,
132 Pseudo: true,
155 Pseudo: true,
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
62 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt),
66 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
76 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
89 def VAARG_64 : I<0, Pseudo,
106 def WIN_ALLOCA : I<0, Pseudo, (outs), (ins),
116 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
[all …]
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
36 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
46 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
50 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
65 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
80 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
94 def VAARG_64 : I<0, Pseudo,
109 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
116 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrCompiler.td | 30 // Random Pseudo Instructions.
37 def MOVPC32r : Ii32<0xE8, Pseudo, (outs GR32:$reg), (ins i32imm:$label),
51 def ADJCALLSTACKDOWN32 : I<0, Pseudo, (outs),
54 def ADJCALLSTACKUP32 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
69 def ADJCALLSTACKDOWN64 : I<0, Pseudo, (outs),
72 def ADJCALLSTACKUP64 : I<0, Pseudo, (outs), (ins i32imm:$amt1, i32imm:$amt2),
84 def VASTART_SAVE_XMM_REGS : I<0, Pseudo,
98 def VAARG_64 : I<0, Pseudo,
113 def SEG_ALLOCA_32 : I<0, Pseudo, (outs GR32:$dst), (ins GR32:$size),
120 def SEG_ALLOCA_64 : I<0, Pseudo, (outs GR64:$dst), (ins GR64:$size),
[all …]
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| D | X86InstrTSX.td | 24 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
37 def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenInstrInfo.inc | 4060 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
4061 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4062 …{ 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4063 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4064 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4065 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4066 …{ 6, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4067 …{ 7, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
4068 …{ 8, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
4069 …{ 9, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove),…
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 64 // Pseudo shift nodes for non-constant shift amounts.
335 def ADJCALLSTACKDOWN : Pseudo<(outs),
345 def ADJCALLSTACKUP : Pseudo<(outs),
369 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
374 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
392 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
399 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
438 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
456 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
486 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
[all …]
|
| /external/llvm/lib/Target/AVR/ |
| D | AVRInstrInfo.td | 64 // Pseudo shift nodes for non-constant shift amounts.
301 def ADJCALLSTACKDOWN : Pseudo<(outs),
311 def ADJCALLSTACKUP : Pseudo<(outs),
335 // Pseudo instruction to add four 8-bit registers as two 16-bit values.
340 def ADDWRdRr : Pseudo<(outs DREGS:$rd),
358 // Pseudo instruction to add four 8-bit registers as two 16-bit values with
365 def ADCWRdRr : Pseudo<(outs DREGS:$rd),
404 def SUBWRdRr : Pseudo<(outs DREGS:$rd),
422 def SUBIWRdK : Pseudo<(outs DLDREGS:$rd),
452 def SBCWRdRr : Pseudo<(outs DREGS:$rd),
[all …]
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | ValueTypes.td | 65 // Pseudo valuetype mapped to the current pointer size to any address space.
69 // Pseudo valuetype to represent "vector of any size"
72 // Pseudo valuetype to represent "float of any format"
75 // Pseudo valuetype to represent "integer of any bit width"
78 // Pseudo valuetype mapped to the current pointer size.
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 102 // Pseudo valuetype mapped to the current pointer size to any address space.
106 // Pseudo valuetype to represent "vector of any size"
109 // Pseudo valuetype to represent "float of any format"
112 // Pseudo valuetype to represent "integer of any bit width"
115 // Pseudo valuetype mapped to the current pointer size.
118 // Pseudo valuetype to represent "any type of any size".
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenInstrInfo.inc | 4695 …{ 0, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, OperandI…
4696 …{ 1, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4697 …{ 2, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4698 …{ 3, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4699 …{ 4, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4700 …{ 5, 1, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, Ope…
4701 …{ 6, 0, 0, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr,…
4702 …{ 7, 3, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo4, -1 ,nullptr }, /…
4703 …{ 8, 4, 1, 0, 0, 0|(1ULL<<MCID::Pseudo), 0x0ULL, nullptr, nullptr, OperandInfo5, -1 ,nullptr }, /…
4704 …{ 9, 1, 1, 0, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove),…
[all …]
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
209 def ATOMIC_LOAD_ADD_I64 : Pseudo<
212 def ATOMIC_LOAD_SUB_I64 : Pseudo<
215 def ATOMIC_LOAD_OR_I64 : Pseudo<
218 def ATOMIC_LOAD_XOR_I64 : Pseudo<
221 def ATOMIC_LOAD_AND_I64 : Pseudo<
224 def ATOMIC_LOAD_NAND_I64 : Pseudo<
228 def ATOMIC_CMP_SWAP_I64 : Pseudo<
232 def ATOMIC_SWAP_I64 : Pseudo<
265 def TCRETURNdi8 :Pseudo< (outs),
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 360 // Pseudo-instructions:
364 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "",
366 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "",
370 def UPDATE_VRSAVE : Pseudo<(outs GPRC:$rD), (ins GPRC:$rS),
375 def DYNALLOC : Pseudo<(outs GPRC:$result), (ins GPRC:$negsize, memri:$fpsi), "",
383 def SELECT_CC_I4 : Pseudo<(outs GPRC:$dst), (ins CRRC:$cond, GPRC:$T, GPRC:$F,
386 def SELECT_CC_I8 : Pseudo<(outs G8RC:$dst), (ins CRRC:$cond, G8RC:$T, G8RC:$F,
389 def SELECT_CC_F4 : Pseudo<(outs F4RC:$dst), (ins CRRC:$cond, F4RC:$T, F4RC:$F,
392 def SELECT_CC_F8 : Pseudo<(outs F8RC:$dst), (ins CRRC:$cond, F8RC:$T, F8RC:$F,
395 def SELECT_CC_VRRC: Pseudo<(outs VRRC:$dst), (ins CRRC:$cond, VRRC:$T, VRRC:$F,
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 97 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
204 def ATOMIC_LOAD_ADD_I64 : Pseudo<
207 def ATOMIC_LOAD_SUB_I64 : Pseudo<
210 def ATOMIC_LOAD_OR_I64 : Pseudo<
213 def ATOMIC_LOAD_XOR_I64 : Pseudo<
216 def ATOMIC_LOAD_AND_I64 : Pseudo<
219 def ATOMIC_LOAD_NAND_I64 : Pseudo<
222 def ATOMIC_LOAD_MIN_I64 : Pseudo<
225 def ATOMIC_LOAD_MAX_I64 : Pseudo<
228 def ATOMIC_LOAD_UMIN_I64 : Pseudo<
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| D | SparcInstrInfo.td | 207 // Pseudo instructions.
208 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
213 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
217 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
220 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
242 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
244 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
247 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
258 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
263 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
[all …]
|
| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrFormats.td | 28 // Pseudo instructions
29 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | ValueTypes.td | 152 // Pseudo valuetype mapped to the current pointer size to any address space.
156 // Pseudo valuetype to represent "vector of any size"
159 // Pseudo valuetype to represent "float of any format"
162 // Pseudo valuetype to represent "integer of any bit width"
165 // Pseudo valuetype mapped to the current pointer size.
168 // Pseudo valuetype to represent "any type of any size".
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonPseudo.td | 26 def A2_iconst : Pseudo<(outs IntRegs:$Rd32),
83 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
87 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
204 : Pseudo<(outs), iops, "">, PredRel {
246 def PS_tailcall_i : Pseudo<(outs), (ins a30_2Imm:$dst), "", []>;
249 def PS_aligna : Pseudo<(outs IntRegs:$Rd), (ins u32_0Imm:$A), "", []>;
260 def PS_fi : Pseudo<(outs IntRegs:$Rd),
263 def PS_fia : Pseudo<(outs IntRegs:$Rd),
313 def PS_alloca: Pseudo <(outs IntRegs:$Rd),
423 def PS_vstorerq_ai: Pseudo<(outs),
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 268 class LD_IMM64<bits<4> Pseudo, string OpcodeStr>
279 let Inst{55-52} = Pseudo;
477 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
480 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
486 def Select : Pseudo<(outs GPR:$dst),
491 def Select_Ri : Pseudo<(outs GPR:$dst),
496 def Select_64_32 : Pseudo<(outs GPR32:$dst),
501 def Select_Ri_64_32 : Pseudo<(outs GPR32:$dst),
506 def Select_32 : Pseudo<(outs GPR32:$dst),
511 def Select_Ri_32 : Pseudo<(outs GPR32:$dst),
[all …]
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.td | 132 // Pseudo instructions.
133 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
137 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
140 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
203 // Pseudo-instruction for loading a general 32-bit constant.
204 def LOAD32imm: Pseudo<(outs GR:$dst), (ins i32imm:$src),
208 def LOAD32sym: Pseudo<(outs GR:$dst), (ins i32imm:$src),
234 // Pseudo-instruction for loading a stack slot
235 def LOAD32fi: Pseudo<(outs DP:$dst), (ins MEMii:$mem),
240 def LOAD16fi: Pseudo<(outs D16:$dst), (ins MEMii:$mem),
[all …]
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