Q3 (reference) in projects: external - OpenGrok search results

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Searched refs:Q3 (Results 1 – 25 of 344) sorted by relevance

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/external/libxaac/decoder/armv7/
D	ixheaacd_post_twiddle_overlap.s	`199 VLD2.32 {Q2, Q3}, [R8]! 308 VMULL.U16 Q3, D2, D13 317 VSHR.U32 Q3, Q3, #16 320 VMLAL.S16 Q3, D3, D13 360 VQSHL.S32 Q3, Q3, Q8 363 VQSUB.S32 Q3, Q3, Q13 403 VQSHL.S32 Q3, Q3, #2 409 VQADD.S32 Q3, Q3, Q10 415 VSHR.S32 Q3, Q3, #16 422 VLD2.32 {Q2, Q3}, [R8]! [all …]`
D	ixheaacd_dct3_32.s	`64 VLD1.32 {Q3}, [R9]! 68 VSHR.S32 Q3, Q3, #7 81 VSUB.I32 Q5, Q3, Q4 114 VLD1.32 {Q3}, [R9]! 117 VSHR.S32 Q3, Q3, #7 125 VSUB.I32 Q5, Q3, Q4 145 VLD1.32 {Q3}, [R9]! 160 VSHR.S32 Q3, Q3, #7 166 VSUB.I32 Q5, Q3, Q4 206 VSHR.S32 Q3, Q3, #7 [all …]`
D	ixheaacd_dec_DCT2_64_asm.s	`87 VLD2.32 {Q2, Q3}, [R5]! 91 VREV64.32 Q3, Q3 96 VSUB.I32 Q11, Q3, Q1 98 VADD.I32 Q10, Q3, Q1 118 VLD2.32 {Q2, Q3}, [R5]! 125 VREV64.32 Q3, Q3 143 VSUB.I32 Q11, Q3, Q1 145 VADD.I32 Q10, Q3, Q1 162 VLD2.32 {Q2, Q3}, [R5]! 168 VREV64.32 Q3, Q3 [all …]`
D	ixheaacd_post_twiddle.s	`185 VMULL.U16 Q3, D16, D10 195 VSHR.U32 Q3, Q3, #16 199 VMLAL.S16 Q3, D17, D10 205 VNEG.S32 Q8, Q3 293 VMULL.U16 Q3, D16, D10 303 VSHR.U32 Q3, Q3, #16 307 VMLAL.S16 Q3, D17, D10 311 VNEG.S32 Q8, Q3 393 VMULL.U16 Q3, D16, D10 403 VSHR.U32 Q3, Q3, #16 [all …]`
D	ixheaacd_no_lap1.s	`52 VQNEG.S32 Q3, Q3 59 VQSHL.S32 Q12, Q3, Q1 84 VQNEG.S32 Q3, Q3 91 VQSHL.S32 Q12, Q3, Q1`
D	ixheaacd_overlap_add1.s	`49 VREV64.32 Q3, Q3 51 VQNEG.S32 Q0, Q3 106 VREV64.32 Q3, Q3 108 VQNEG.S32 Q0, Q3 149 VREV64.32 Q3, Q3 161 VQNEG.S32 Q0, Q3 212 VREV64.32 Q3, Q3 213 VQNEG.S32 Q0, Q3`
D	ixheaacd_esbr_fwd_modulation.s	`43 VSHR.S32 Q3, Q3, #4 52 VQSUB.S32 Q5, Q1, Q3 55 VADD.S32 Q7, Q1, Q3 91 VQSUB.S64 Q1, Q3, Q4`
D	ixheaacd_calcmaxspectralline.s	`44 VORR Q3, Q0, Q3 46 VORR Q3, Q1, Q3`
D	ixheaacd_mps_synt_pre_twiddle.s	`39 VMULL.S32 Q3, D0, D3 44 VSHRN.I64 D6, Q3, #31`
D	ixheaacd_mps_synt_post_twiddle.s	`39 VMULL.S32 Q3, D13, D3 44 VSHRN.I64 D6, Q3, #31`
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/Support/
D	BranchProbabilityTest.cpp	`123 BP Q3(3, 4); in TEST() local 128 EXPECT_EQ(Q + H, Q3); in TEST() 129 EXPECT_EQ(Q + Q3, O); in TEST() 130 EXPECT_EQ(H + Q3, O); in TEST() 131 EXPECT_EQ(Q3 + Q3, O); in TEST() 136 EXPECT_EQ(O - Q, Q3); in TEST() 137 EXPECT_EQ(Q3 - H, Q); in TEST() 139 EXPECT_EQ(Q - Q3, Z); in TEST() 148 EXPECT_EQ(Q * 3, Q3); in TEST() 150 EXPECT_EQ(Q3 * 2, O); in TEST() [all …]`
/external/libhevc/common/arm/
D	ihevc_resi_trans_32x32_a9q.s	202 VSUBL.U8 Q3,D11,D15 @ Get residue 25-32 row 2 209 VREV64.S16 Q3,Q3 @ Rev 25-32 row 2 213 VSWP D6,D7 @ Q3: 32 31 30 29 28 27 26 25 row 2 218 VADD.S16 Q8, Q12,Q3 @ e[k] = resi_tmp_1 + resi_tmp_2 k -> 1-8 row 2 220 VSUB.S16 Q10, Q12,Q3 @ o[k] = resi_tmp_1 - resi_tmp_2 k -> 1-8 row 2 -- dual issue 230 VSUB.S16 Q3, Q8, Q9 @ eo[k] = e[k] - e[16-k] k->1-8 row 2 861 VADD.S32 Q11, Q3, Q4 @e[k] = resi_tmp_1 + resi_tmp_2 k -> 13-16 R1-- dual issue 876 VSUB.S32 Q15, Q3, Q4 @o[k] = resi_tmp_1 - resi_tmp_2 k -> 13-16 R1 882 VSUB.S32 Q3, Q9, Q10 @eo[k] = e[k] - e[15 - k] row R1, k-> 4-7 938 VMLA.S32 Q8,Q7,Q3 @g_ai4_ihevc_trans_16[2][4-7]*eo[0][4-7] R1 [all …]
D	ihevc_resi_trans.s	`1006 VLD2.U8 {Q2,Q3},[R0],R4 @LOAD 1-16 src row 2 1007 VLD2.U8 {Q3,Q4},[R1],R5 @LOAD 1-16 pred row 2 1094 VMULL.S16 Q3,D27,D0 @g_ai2_ihevc_trans_16[6][0-4] * eo[0-4] R1 1120 VTRN.32 Q1, Q3 @R1 transpose1 -- 2 cycles 1136 VADD.S32 Q3,Q3,Q7 @R1 add 1141 VADD.S32 Q5,Q5,Q3 @R1 add 1225 VMULL.S16 Q3,D18,D4 @o[4][0-3]* R1 1226 VMLAL.S16 Q3,D19,D5 @o[4][4-7]* R1 1267 VTRN.32 Q3 ,Q5 @ 2-cycle instruction 1281 VADD.S32 Q5 ,Q5 ,Q3 [all …]`
/external/llvm/lib/Target/AArch64/
D	AArch64CallingConvention.td	`68 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 106 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 108 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 110 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 113 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 115 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
D	AArch64CallingConvention.td	`72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 74 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 76 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 79 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 81 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 112 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 114 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 116 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 119 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>, 121 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>> [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D	cttz_vector.ll	`68 ; CHECK: vneg.s8 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 69 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] 115 ; CHECK: vneg.s16 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 116 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] 156 ; CHECK: vneg.s32 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 157 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] 192 ; CHECK: vmov.i64 [[Q3:q[0-9]+]], #0xffffffffffffffff 195 ; CHECK: vadd.i64 [[Q2]], [[Q2]], [[Q3]] 252 ; CHECK: vneg.s8 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 253 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] [all …]`
/external/llvm/test/CodeGen/ARM/
D	cttz_vector.ll	`68 ; CHECK: vneg.s8 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 69 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] 115 ; CHECK: vneg.s16 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 116 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] 156 ; CHECK: vneg.s32 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 157 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] 192 ; CHECK: vmov.i64 [[Q3:q[0-9]+]], #0xffffffffffffffff 195 ; CHECK: vadd.i64 [[Q1]], [[Q1]], [[Q3]] 252 ; CHECK: vneg.s8 [[Q3:q[0-9]+]], [[Q1:q[0-9]+]] 253 ; CHECK: vand [[Q1]], [[Q1]], [[Q3]] [all …]`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
D	ARMCallingConv.td	75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, 84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, 94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, 141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>, 142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> 216 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, [all …]
/external/llvm/lib/Target/ARM/
D	ARMCallingConv.td	75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>, 84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>, 94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, 138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>, 139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>, 141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>, 142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>> 215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>, [all …]
/external/icu/icu4c/source/data/locales/
D	sv_FI.txt	`27 "Q3", 35 "Q3",`
D	lrc.txt	`244 "Q3", 256 "Q3", 264 "Q3",`
/external/clang/test/CodeGen/
D	partial-reinitialization1.c	`34 struct Q3 { struct 47 (struct Q3){ { 1, 2, 3 }, { 4, 5, 6 } },`
/external/fonttools/Lib/fontTools/misc/
D	bezierTools.py	`505 Q3 = QQQ 507 Q3 = 0 if abs(Q3) < epsilon else Q3 509 R2_Q3 = R2 - Q3 511 if R2 == 0. and Q3 == 0.: 516 theta = acos(max(min(R/sqrt(Q3), 1.0), -1.0))`
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
D	HexagonVectorPrint.cpp	`77 \|\| (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3); in isVecReg() 88 if (R >= Hexagon::Q0 && R <= Hexagon::Q3) { in getStringReg() 192 } else if (Reg >= Hexagon::Q0 && Reg <= Hexagon::Q3) { in runOnMachineFunction()`
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
D	AArch64GenCallingConv.inc	192 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 205 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 218 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 237 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 254 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 436 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 449 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 462 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 481 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… 497 …AArch64::Q0, AArch64::Q1, AArch64::Q2, AArch64::Q3, AArch64::Q4, AArch64::Q5, AArch64::Q6, AArch64… [all …]

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