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Searched refs:QIXIS_BASE_PHYS (Results 1 – 25 of 27) sorted by relevance

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/external/u-boot/board/freescale/t4qds/
Dlaw.c21 #ifdef QIXIS_BASE_PHYS
22 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Dtlb.c123 #ifdef QIXIS_BASE_PHYS
124 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
/external/u-boot/board/freescale/t208xqds/
Dlaw.c21 #ifdef QIXIS_BASE_PHYS
22 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Dtlb.c129 #ifdef QIXIS_BASE_PHYS
130 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
/external/u-boot/board/freescale/t1040qds/
Dlaw.c20 #ifdef QIXIS_BASE_PHYS
21 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Dtlb.c100 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
/external/u-boot/board/freescale/t102xqds/
Dlaw.c20 #ifdef QIXIS_BASE_PHYS
21 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Dtlb.c97 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
/external/u-boot/include/configs/
DB4860QDS.h273 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) macro
275 #define QIXIS_BASE_PHYS QIXIS_BASE macro
288 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
DT102xQDS.h285 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) macro
287 #define QIXIS_BASE_PHYS QIXIS_BASE macro
301 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
Dls1043aqds.h212 #define QIXIS_BASE_PHYS QIXIS_BASE macro
232 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
Dls1046aqds.h246 #define QIXIS_BASE_PHYS QIXIS_BASE macro
266 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
Dls1021aqds.h219 #define QIXIS_BASE_PHYS QIXIS_BASE macro
241 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
Dls2080a_common.h124 #define QIXIS_BASE_PHYS 0x20000000 macro
DT4240QDS.h198 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) macro
201 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
Dls1088a_common.h118 #define QIXIS_BASE_PHYS 0x20000000 macro
DT1040QDS.h212 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) macro
225 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
DT208xQDS.h274 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE) macro
277 #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
Dls1088ardb.h175 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
Dls2080ardb.h181 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
Dls2080aqds.h179 #define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
Dls1088aqds.h193 #define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
/external/u-boot/board/freescale/b4860qds/
Dlaw.c18 SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
Dtlb.c113 SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
/external/u-boot/board/freescale/ls2080aqds/
Dls2080aqds.c46 addr = QIXIS_BASE_PHYS; in get_qixis_addr()

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