1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2015 Freescale Semiconductor
4 */
5 #include <common.h>
6 #include <malloc.h>
7 #include <errno.h>
8 #include <netdev.h>
9 #include <fsl_ifc.h>
10 #include <fsl_ddr.h>
11 #include <asm/io.h>
12 #include <fdt_support.h>
13 #include <linux/libfdt.h>
14 #include <fsl-mc/fsl_mc.h>
15 #include <environment.h>
16 #include <i2c.h>
17 #include <rtc.h>
18 #include <asm/arch/soc.h>
19 #include <hwconfig.h>
20 #include <fsl_sec.h>
21 #include <asm/arch/ppa.h>
22
23
24 #include "../common/qixis.h"
25 #include "ls2080aqds_qixis.h"
26 #include "../common/vid.h"
27
28 #define PIN_MUX_SEL_SDHC 0x00
29 #define PIN_MUX_SEL_DSPI 0x0a
30 #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
31
32 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
33
34 DECLARE_GLOBAL_DATA_PTR;
35
36 enum {
37 MUX_TYPE_SDHC,
38 MUX_TYPE_DSPI,
39 };
40
get_qixis_addr(void)41 unsigned long long get_qixis_addr(void)
42 {
43 unsigned long long addr;
44
45 if (gd->flags & GD_FLG_RELOC)
46 addr = QIXIS_BASE_PHYS;
47 else
48 addr = QIXIS_BASE_PHYS_EARLY;
49
50 /*
51 * IFC address under 256MB is mapped to 0x30000000, any address above
52 * is mapped to 0x5_10000000 up to 4GB.
53 */
54 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
55
56 return addr;
57 }
58
checkboard(void)59 int checkboard(void)
60 {
61 char buf[64];
62 u8 sw;
63 static const char *const freq[] = {"100", "125", "156.25",
64 "100 separate SSCG"};
65 int clock;
66
67 cpu_name(buf);
68 printf("Board: %s-QDS, ", buf);
69
70 sw = QIXIS_READ(arch);
71 printf("Board Arch: V%d, ", sw >> 4);
72 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
73
74 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
75
76 sw = QIXIS_READ(brdcfg[0]);
77 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
78
79 if (sw < 0x8)
80 printf("vBank: %d\n", sw);
81 else if (sw == 0x8)
82 puts("PromJet\n");
83 else if (sw == 0x9)
84 puts("NAND\n");
85 else if (sw == 0xf)
86 puts("QSPI\n");
87 else if (sw == 0x15)
88 printf("IFCCard\n");
89 else
90 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
91
92 printf("FPGA: v%d (%s), build %d",
93 (int)QIXIS_READ(scver), qixis_read_tag(buf),
94 (int)qixis_read_minor());
95 /* the timestamp string contains "\n" at the end */
96 printf(" on %s", qixis_read_time(buf));
97
98 /*
99 * Display the actual SERDES reference clocks as configured by the
100 * dip switches on the board. Note that the SWx registers could
101 * technically be set to force the reference clocks to match the
102 * values that the SERDES expects (or vice versa). For now, however,
103 * we just display both values and hope the user notices when they
104 * don't match.
105 */
106 puts("SERDES1 Reference : ");
107 sw = QIXIS_READ(brdcfg[2]);
108 clock = (sw >> 6) & 3;
109 printf("Clock1 = %sMHz ", freq[clock]);
110 clock = (sw >> 4) & 3;
111 printf("Clock2 = %sMHz", freq[clock]);
112
113 puts("\nSERDES2 Reference : ");
114 clock = (sw >> 2) & 3;
115 printf("Clock1 = %sMHz ", freq[clock]);
116 clock = (sw >> 0) & 3;
117 printf("Clock2 = %sMHz\n", freq[clock]);
118
119 return 0;
120 }
121
get_board_sys_clk(void)122 unsigned long get_board_sys_clk(void)
123 {
124 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
125
126 switch (sysclk_conf & 0x0F) {
127 case QIXIS_SYSCLK_83:
128 return 83333333;
129 case QIXIS_SYSCLK_100:
130 return 100000000;
131 case QIXIS_SYSCLK_125:
132 return 125000000;
133 case QIXIS_SYSCLK_133:
134 return 133333333;
135 case QIXIS_SYSCLK_150:
136 return 150000000;
137 case QIXIS_SYSCLK_160:
138 return 160000000;
139 case QIXIS_SYSCLK_166:
140 return 166666666;
141 }
142 return 66666666;
143 }
144
get_board_ddr_clk(void)145 unsigned long get_board_ddr_clk(void)
146 {
147 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
148
149 switch ((ddrclk_conf & 0x30) >> 4) {
150 case QIXIS_DDRCLK_100:
151 return 100000000;
152 case QIXIS_DDRCLK_125:
153 return 125000000;
154 case QIXIS_DDRCLK_133:
155 return 133333333;
156 }
157 return 66666666;
158 }
159
select_i2c_ch_pca9547(u8 ch)160 int select_i2c_ch_pca9547(u8 ch)
161 {
162 int ret;
163
164 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
165 if (ret) {
166 puts("PCA: failed to select proper channel\n");
167 return ret;
168 }
169
170 return 0;
171 }
172
config_board_mux(int ctrl_type)173 int config_board_mux(int ctrl_type)
174 {
175 u8 reg5;
176
177 reg5 = QIXIS_READ(brdcfg[5]);
178
179 switch (ctrl_type) {
180 case MUX_TYPE_SDHC:
181 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
182 break;
183 case MUX_TYPE_DSPI:
184 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
185 break;
186 default:
187 printf("Wrong mux interface type\n");
188 return -1;
189 }
190
191 QIXIS_WRITE(brdcfg[5], reg5);
192
193 return 0;
194 }
195
board_init(void)196 int board_init(void)
197 {
198 char *env_hwconfig;
199 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
200 u32 val;
201
202 init_final_memctl_regs();
203
204 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
205
206 env_hwconfig = env_get("hwconfig");
207
208 if (hwconfig_f("dspi", env_hwconfig) &&
209 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
210 config_board_mux(MUX_TYPE_DSPI);
211 else
212 config_board_mux(MUX_TYPE_SDHC);
213
214 #if defined(CONFIG_NAND) && defined(CONFIG_FSL_QSPI)
215 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
216
217 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
218 QIXIS_WRITE(brdcfg[9],
219 (QIXIS_READ(brdcfg[9]) & 0xf8) |
220 FSL_QIXIS_BRDCFG9_QSPI);
221 #endif
222
223 #ifdef CONFIG_ENV_IS_NOWHERE
224 gd->env_addr = (ulong)&default_environment[0];
225 #endif
226 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
227 rtc_enable_32khz_output();
228 #ifdef CONFIG_FSL_CAAM
229 sec_init();
230 #endif
231
232 #ifdef CONFIG_FSL_LS_PPA
233 ppa_init();
234 #endif
235
236 return 0;
237 }
238
board_early_init_f(void)239 int board_early_init_f(void)
240 {
241 #ifdef CONFIG_SYS_I2C_EARLY_INIT
242 i2c_early_init_f();
243 #endif
244 fsl_lsch3_early_init_f();
245 #ifdef CONFIG_FSL_QSPI
246 /* input clk: 1/2 platform clk, output: input/20 */
247 out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
248 #endif
249 return 0;
250 }
251
misc_init_r(void)252 int misc_init_r(void)
253 {
254 if (adjust_vdd(0))
255 printf("Warning: Adjusting core voltage failed.\n");
256
257 return 0;
258 }
259
detail_board_ddr_info(void)260 void detail_board_ddr_info(void)
261 {
262 puts("\nDDR ");
263 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
264 print_ddr_info(0);
265 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
266 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
267 puts("\nDP-DDR ");
268 print_size(gd->bd->bi_dram[2].size, "");
269 print_ddr_info(CONFIG_DP_DDR_CTRL);
270 }
271 #endif
272 }
273
274 #if defined(CONFIG_ARCH_MISC_INIT)
arch_misc_init(void)275 int arch_misc_init(void)
276 {
277 return 0;
278 }
279 #endif
280
281 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
fdt_fixup_board_enet(void * fdt)282 void fdt_fixup_board_enet(void *fdt)
283 {
284 int offset;
285
286 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
287
288 if (offset < 0)
289 offset = fdt_path_offset(fdt, "/fsl-mc");
290
291 if (offset < 0) {
292 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
293 __func__, offset);
294 return;
295 }
296
297 if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
298 fdt_status_okay(fdt, offset);
299 else
300 fdt_status_fail(fdt, offset);
301 }
302
board_quiesce_devices(void)303 void board_quiesce_devices(void)
304 {
305 fsl_mc_ldpaa_exit(gd->bd);
306 }
307 #endif
308
309 #ifdef CONFIG_OF_BOARD_SETUP
ft_board_setup(void * blob,bd_t * bd)310 int ft_board_setup(void *blob, bd_t *bd)
311 {
312 u64 base[CONFIG_NR_DRAM_BANKS];
313 u64 size[CONFIG_NR_DRAM_BANKS];
314
315 ft_cpu_setup(blob, bd);
316
317 /* fixup DT for the two GPP DDR banks */
318 base[0] = gd->bd->bi_dram[0].start;
319 size[0] = gd->bd->bi_dram[0].size;
320 base[1] = gd->bd->bi_dram[1].start;
321 size[1] = gd->bd->bi_dram[1].size;
322
323 #ifdef CONFIG_RESV_RAM
324 /* reduce size if reserved memory is within this bank */
325 if (gd->arch.resv_ram >= base[0] &&
326 gd->arch.resv_ram < base[0] + size[0])
327 size[0] = gd->arch.resv_ram - base[0];
328 else if (gd->arch.resv_ram >= base[1] &&
329 gd->arch.resv_ram < base[1] + size[1])
330 size[1] = gd->arch.resv_ram - base[1];
331 #endif
332
333 fdt_fixup_memory_banks(blob, base, size, 2);
334
335 fsl_fdt_fixup_dr_usb(blob, bd);
336
337 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
338 fdt_fixup_board_enet(blob);
339 #endif
340
341 return 0;
342 }
343 #endif
344
qixis_dump_switch(void)345 void qixis_dump_switch(void)
346 {
347 int i, nr_of_cfgsw;
348
349 QIXIS_WRITE(cms[0], 0x00);
350 nr_of_cfgsw = QIXIS_READ(cms[1]);
351
352 puts("DIP switch settings dump:\n");
353 for (i = 1; i <= nr_of_cfgsw; i++) {
354 QIXIS_WRITE(cms[0], i);
355 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
356 }
357 }
358