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Searched refs:RegClasses (Results 1 – 9 of 9) sorted by relevance

/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.cpp464 ArrayRef<CodeGenRegisterClass*> RegClasses = RegBank.getRegClasses(); in computeSubClasses() local
467 for (unsigned rci = RegClasses.size(); rci; --rci) { in computeSubClasses()
468 CodeGenRegisterClass &RC = *RegClasses[rci - 1]; in computeSubClasses()
469 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
473 for (unsigned s = rci; s != RegClasses.size(); ++s) { in computeSubClasses()
476 CodeGenRegisterClass *SubRC = RegClasses[s]; in computeSubClasses()
485 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s) in computeSubClasses()
490 for (unsigned rci = 0; rci != RegClasses.size(); ++rci) { in computeSubClasses()
491 const BitVector &SC = RegClasses[rci]->getSubClasses(); in computeSubClasses()
495 RegClasses[s]->SuperClasses.push_back(RegClasses[rci]); in computeSubClasses()
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DCodeGenRegisters.h232 std::vector<CodeGenRegisterClass*> RegClasses; variable
274 return RegClasses; in getRegClasses()
/external/swiftshader/third_party/llvm-7.0/llvm/utils/TableGen/
DCodeGenRegisters.cpp931 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses() local
934 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
936 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
942 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { in computeSubClasses()
959 for (auto &RC : RegClasses) { in computeSubClasses()
961 auto I = RegClasses.begin(); in computeSubClasses()
975 for (auto &RC : RegClasses) in computeSubClasses()
988 auto &RegClasses = RegBank.getRegClasses(); in getMatchingSubClassWithSubRegs() local
997 for (auto &RC : RegClasses) in getMatchingSubClassWithSubRegs()
1005 for (auto &RC: RegClasses) { in getMatchingSubClassWithSubRegs()
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DCodeGenRegisters.h544 std::list<CodeGenRegisterClass> RegClasses; variable
582 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
696 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
699 return RegClasses; in getRegClasses()
/external/llvm/utils/TableGen/
DCodeGenRegisters.cpp851 auto &RegClasses = RegBank.getRegClasses(); in computeSubClasses() local
854 for (auto I = RegClasses.rbegin(), E = RegClasses.rend(); I != E; ++I) { in computeSubClasses()
856 RC.SubClasses.resize(RegClasses.size()); in computeSubClasses()
860 for (auto I2 = I.base(), E2 = RegClasses.end(); I2 != E2; ++I2) { in computeSubClasses()
877 for (auto &RC : RegClasses) { in computeSubClasses()
879 auto I = RegClasses.begin(); in computeSubClasses()
893 for (auto &RC : RegClasses) in computeSubClasses()
996 RegClasses.emplace_back(*this, RC); in CodeGenRegBank()
997 addToMaps(&RegClasses.back()); in CodeGenRegBank()
1004 RegClasses.sort(TopoOrderRC); in CodeGenRegBank()
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DCodeGenRegisters.h502 std::list<CodeGenRegisterClass> RegClasses; variable
536 inferMatchingSuperRegClass(RC, RegClasses.begin()); in inferMatchingSuperRegClass()
649 std::list<CodeGenRegisterClass> &getRegClasses() { return RegClasses; } in getRegClasses()
652 return RegClasses; in getRegClasses()
/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py199 RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32), variable
203 for _, RegClass in RegClasses:
208 for _, RegClass in RegClasses:
223 for Name, RegClass in RegClasses:
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSchedule.td471 // a list of register classes (see field `RegClasses`). An empty list of
475 // A register R can be renamed if its register class appears in the `RegClasses`
480 // However, V is only renamed if its register class is part of `RegClasses`.
491 // register class that is in `RegClasses`.
512 list<RegisterClass> RegClasses = Classes;
/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringARM32.cpp1557 const RegClassType RegClasses[] = { in addProlog() local
1562 for (const auto &RegClass : RegClasses) { in addProlog()