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Searched refs:RegList16 (Results 1 – 5 of 5) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenCallingConv.inc236 static const MCPhysReg RegList16[] = {
239 if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
480 static const MCPhysReg RegList16[] = {
483 if (unsigned Reg = State.AllocateReg(RegList15, RegList16)) {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRISelLowering.cpp934 static const MCPhysReg RegList16[] = {AVR::R25R24, AVR::R23R22, AVR::R21R20, in analyzeStandardArguments() local
971 const MCPhysReg *RegList = (LocVT == MVT::i16) ? RegList16 : RegList8; in analyzeStandardArguments()
/external/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td535 let Name = "RegList16";
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsInstrInfo.td542 let Name = "RegList16";
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenAsmMatcher.inc3675 // 'RegList16' class