1/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ 2|* *| 3|* Assembly Matcher Source Fragment *| 4|* *| 5|* Automatically generated file, do not edit! *| 6|* *| 7\*===----------------------------------------------------------------------===*/ 8 9 10#ifdef GET_ASSEMBLER_HEADER 11#undef GET_ASSEMBLER_HEADER 12 // This should be included into the middle of the declaration of 13 // your subclasses implementation of MCTargetAsmParser. 14 uint64_t ComputeAvailableFeatures(const FeatureBitset& FB) const; 15 void convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 16 const OperandVector &Operands); 17 void convertToMapAndConstraints(unsigned Kind, 18 const OperandVector &Operands) override; 19 unsigned MatchInstructionImpl(const OperandVector &Operands, 20 MCInst &Inst, 21 uint64_t &ErrorInfo, 22 bool matchingInlineAsm, 23 unsigned VariantID = 0); 24 OperandMatchResultTy MatchOperandParserImpl( 25 OperandVector &Operands, 26 StringRef Mnemonic, 27 bool ParseForAllFeatures = false); 28 OperandMatchResultTy tryCustomParseOperand( 29 OperandVector &Operands, 30 unsigned MCK); 31 32#endif // GET_ASSEMBLER_HEADER_INFO 33 34 35#ifdef GET_OPERAND_DIAGNOSTIC_TYPES 36#undef GET_OPERAND_DIAGNOSTIC_TYPES 37 38 Match_Immz, 39 Match_MemSImm10, 40 Match_MemSImm10Lsl1, 41 Match_MemSImm10Lsl2, 42 Match_MemSImm10Lsl3, 43 Match_MemSImm11, 44 Match_MemSImm12, 45 Match_MemSImm16, 46 Match_MemSImm9, 47 Match_MemSImmPtr, 48 Match_SImm10_0, 49 Match_SImm10_Lsl1, 50 Match_SImm10_Lsl2, 51 Match_SImm10_Lsl3, 52 Match_SImm11_0, 53 Match_SImm16, 54 Match_SImm16_Relaxed, 55 Match_SImm19_Lsl2, 56 Match_SImm32, 57 Match_SImm32_Relaxed, 58 Match_SImm4_0, 59 Match_SImm5_0, 60 Match_SImm6_0, 61 Match_SImm7_Lsl2, 62 Match_SImm9_0, 63 Match_UImm10_0, 64 Match_UImm16, 65 Match_UImm16_AltRelaxed, 66 Match_UImm16_Relaxed, 67 Match_UImm1_0, 68 Match_UImm20_0, 69 Match_UImm26_0, 70 Match_UImm2_0, 71 Match_UImm2_1, 72 Match_UImm32_Coerced, 73 Match_UImm3_0, 74 Match_UImm4_0, 75 Match_UImm5_0, 76 Match_UImm5_0_Report_UImm6, 77 Match_UImm5_1, 78 Match_UImm5_32, 79 Match_UImm5_33, 80 Match_UImm5_Lsl2, 81 Match_UImm6_0, 82 Match_UImm6_Lsl2, 83 Match_UImm7_0, 84 Match_UImm7_N1, 85 Match_UImm8_0, 86 Match_UImmRange2_64, 87 END_OPERAND_DIAGNOSTIC_TYPES 88#endif // GET_OPERAND_DIAGNOSTIC_TYPES 89 90 91#ifdef GET_REGISTER_MATCHER 92#undef GET_REGISTER_MATCHER 93 94// Flags for subtarget features that participate in instruction matching. 95enum SubtargetFeatureFlag : uint64_t { 96 Feature_HasMips2 = (1ULL << 10), 97 Feature_HasMips3_32 = (1ULL << 16), 98 Feature_HasMips3_32r2 = (1ULL << 17), 99 Feature_HasMips3 = (1ULL << 11), 100 Feature_NotMips3 = (1ULL << 44), 101 Feature_HasMips4_32 = (1ULL << 18), 102 Feature_NotMips4_32 = (1ULL << 46), 103 Feature_HasMips4_32r2 = (1ULL << 19), 104 Feature_HasMips5_32r2 = (1ULL << 20), 105 Feature_HasMips32 = (1ULL << 12), 106 Feature_HasMips32r2 = (1ULL << 13), 107 Feature_HasMips32r5 = (1ULL << 14), 108 Feature_HasMips32r6 = (1ULL << 15), 109 Feature_NotMips32r6 = (1ULL << 45), 110 Feature_IsGP64bit = (1ULL << 31), 111 Feature_IsGP32bit = (1ULL << 30), 112 Feature_IsPTR64bit = (1ULL << 35), 113 Feature_IsPTR32bit = (1ULL << 34), 114 Feature_HasMips64 = (1ULL << 21), 115 Feature_NotMips64 = (1ULL << 47), 116 Feature_HasMips64r2 = (1ULL << 22), 117 Feature_HasMips64r5 = (1ULL << 23), 118 Feature_HasMips64r6 = (1ULL << 24), 119 Feature_NotMips64r6 = (1ULL << 48), 120 Feature_InMips16Mode = (1ULL << 28), 121 Feature_NotInMips16Mode = (1ULL << 43), 122 Feature_HasCnMips = (1ULL << 1), 123 Feature_NotCnMips = (1ULL << 40), 124 Feature_IsSym32 = (1ULL << 37), 125 Feature_IsSym64 = (1ULL << 38), 126 Feature_HasStdEnc = (1ULL << 25), 127 Feature_InMicroMips = (1ULL << 27), 128 Feature_NotInMicroMips = (1ULL << 42), 129 Feature_HasEVA = (1ULL << 5), 130 Feature_HasMSA = (1ULL << 7), 131 Feature_HasMadd4 = (1ULL << 9), 132 Feature_HasMT = (1ULL << 8), 133 Feature_UseIndirectJumpsHazard = (1ULL << 49), 134 Feature_NoIndirectJumpGuards = (1ULL << 39), 135 Feature_HasCRC = (1ULL << 0), 136 Feature_HasVirt = (1ULL << 26), 137 Feature_HasGINV = (1ULL << 6), 138 Feature_IsFP64bit = (1ULL << 29), 139 Feature_NotFP64bit = (1ULL << 41), 140 Feature_IsSingleFloat = (1ULL << 36), 141 Feature_IsNotSingleFloat = (1ULL << 32), 142 Feature_IsNotSoftFloat = (1ULL << 33), 143 Feature_HasDSP = (1ULL << 2), 144 Feature_HasDSPR2 = (1ULL << 3), 145 Feature_HasDSPR3 = (1ULL << 4), 146 Feature_None = 0 147}; 148 149#endif // GET_REGISTER_MATCHER 150 151 152#ifdef GET_SUBTARGET_FEATURE_NAME 153#undef GET_SUBTARGET_FEATURE_NAME 154 155// User-level names for subtarget features that participate in 156// instruction matching. 157static const char *getSubtargetFeatureName(uint64_t Val) { 158 switch(Val) { 159 case Feature_HasMips2: return ""; 160 case Feature_HasMips3_32: return ""; 161 case Feature_HasMips3_32r2: return ""; 162 case Feature_HasMips3: return ""; 163 case Feature_NotMips3: return ""; 164 case Feature_HasMips4_32: return ""; 165 case Feature_NotMips4_32: return ""; 166 case Feature_HasMips4_32r2: return ""; 167 case Feature_HasMips5_32r2: return ""; 168 case Feature_HasMips32: return ""; 169 case Feature_HasMips32r2: return ""; 170 case Feature_HasMips32r5: return ""; 171 case Feature_HasMips32r6: return ""; 172 case Feature_NotMips32r6: return ""; 173 case Feature_IsGP64bit: return ""; 174 case Feature_IsGP32bit: return ""; 175 case Feature_IsPTR64bit: return ""; 176 case Feature_IsPTR32bit: return ""; 177 case Feature_HasMips64: return ""; 178 case Feature_NotMips64: return ""; 179 case Feature_HasMips64r2: return ""; 180 case Feature_HasMips64r5: return ""; 181 case Feature_HasMips64r6: return ""; 182 case Feature_NotMips64r6: return ""; 183 case Feature_InMips16Mode: return ""; 184 case Feature_NotInMips16Mode: return ""; 185 case Feature_HasCnMips: return ""; 186 case Feature_NotCnMips: return ""; 187 case Feature_IsSym32: return ""; 188 case Feature_IsSym64: return ""; 189 case Feature_HasStdEnc: return ""; 190 case Feature_InMicroMips: return ""; 191 case Feature_NotInMicroMips: return ""; 192 case Feature_HasEVA: return ""; 193 case Feature_HasMSA: return ""; 194 case Feature_HasMadd4: return ""; 195 case Feature_HasMT: return ""; 196 case Feature_UseIndirectJumpsHazard: return ""; 197 case Feature_NoIndirectJumpGuards: return ""; 198 case Feature_HasCRC: return ""; 199 case Feature_HasVirt: return ""; 200 case Feature_HasGINV: return ""; 201 case Feature_IsFP64bit: return ""; 202 case Feature_NotFP64bit: return ""; 203 case Feature_IsSingleFloat: return ""; 204 case Feature_IsNotSingleFloat: return ""; 205 case Feature_IsNotSoftFloat: return ""; 206 case Feature_HasDSP: return ""; 207 case Feature_HasDSPR2: return ""; 208 case Feature_HasDSPR3: return ""; 209 default: return "(unknown)"; 210 } 211} 212 213#endif // GET_SUBTARGET_FEATURE_NAME 214 215 216#ifdef GET_MATCHER_IMPLEMENTATION 217#undef GET_MATCHER_IMPLEMENTATION 218 219enum { 220 Tie0_1_1, 221 Tie0_1_2, 222}; 223 224static const uint8_t TiedAsmOperandTable[][3] = { 225 /* Tie0_1_1 */ { 0, 1, 1 }, 226 /* Tie0_1_2 */ { 0, 1, 2 }, 227}; 228 229namespace { 230enum OperatorConversionKind { 231 CVT_Done, 232 CVT_Reg, 233 CVT_Tied, 234 CVT_95_addGPR32AsmRegOperands, 235 CVT_95_addAFGR64AsmRegOperands, 236 CVT_95_addFGR64AsmRegOperands, 237 CVT_95_addFGR32AsmRegOperands, 238 CVT_95_addSImmOperands_LT_32_GT_, 239 CVT_95_addMSA128AsmRegOperands, 240 CVT_95_addSImmOperands_LT_16_GT_, 241 CVT_95_Reg, 242 CVT_95_addImmOperands, 243 CVT_95_addGPRMM16AsmRegOperands, 244 CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 245 CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 246 CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 247 CVT_95_addUImmOperands_LT_16_GT_, 248 CVT_95_addGPR64AsmRegOperands, 249 CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 250 CVT_regZERO, 251 CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 252 CVT_regFCC0, 253 CVT_95_addFCCAsmRegOperands, 254 CVT_95_addCOP2AsmRegOperands, 255 CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 256 CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 257 CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 258 CVT_imm_95_0, 259 CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 260 CVT_95_addMemOperands, 261 CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 262 CVT_95_addCCRAsmRegOperands, 263 CVT_95_addMSACtrlAsmRegOperands, 264 CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 265 CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 266 CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 267 CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 268 CVT_95_addGPR32NonZeroAsmRegOperands, 269 CVT_95_addGPR32ZeroAsmRegOperands, 270 CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 271 CVT_95_addCOP0AsmRegOperands, 272 CVT_regZERO_64, 273 CVT_95_addACC64DSPAsmRegOperands, 274 CVT_95_addConstantUImmOperands_LT_1_GT_, 275 CVT_regRA, 276 CVT_regRA_64, 277 CVT_95_addMicroMipsMemOperands, 278 CVT_95_addCOP3AsmRegOperands, 279 CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 280 CVT_95_addConstantUImmOperands_LT_32_GT_, 281 CVT_95_addStrictlyAFGR64AsmRegOperands, 282 CVT_95_addStrictlyFGR64AsmRegOperands, 283 CVT_95_addStrictlyFGR32AsmRegOperands, 284 CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 285 CVT_95_addRegListOperands, 286 CVT_ConvertXWPOperands, 287 CVT_regAC0, 288 CVT_95_addMovePRegPairOperands, 289 CVT_95_addGPRMM16AsmRegMovePOperands, 290 CVT_95_addHI32DSPAsmRegOperands, 291 CVT_95_addLO32DSPAsmRegOperands, 292 CVT_regS0, 293 CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 294 CVT_95_addHWRegsAsmRegOperands, 295 CVT_95_addGPRMM16AsmRegZeroOperands, 296 CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 297 CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 298 CVT_imm_95_2, 299 CVT_imm_95_6, 300 CVT_imm_95_4, 301 CVT_imm_95_5, 302 CVT_imm_95_31, 303 CVT_NUM_CONVERTERS 304}; 305 306enum InstructionConversionKind { 307 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 308 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, 309 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, 310 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, 311 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 312 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, 313 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 314 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, 315 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, 316 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, 317 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, 318 Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, 319 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, 320 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 321 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, 322 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 323 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, 324 Convert__SImm161_1, 325 Convert__Reg1_0__SImm161_1, 326 Convert__Reg1_0__SImm161_2, 327 Convert__Reg1_0__Reg1_1__SImm161_2, 328 Convert__Reg1_0__Tie0_1_1__SImm161_1, 329 Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, 330 Convert__GPRMM16AsmReg1_0__Imm1_1, 331 Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, 332 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, 333 Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, 334 Convert__Imm1_0, 335 Convert__Reg1_0__Reg1_1__Reg1_2, 336 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, 337 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, 338 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, 339 Convert__GPR32AsmReg1_0__SImm161_1, 340 Convert__Reg1_0__Tie0_1_1__Reg1_1, 341 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, 342 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, 343 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, 344 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, 345 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, 346 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, 347 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, 348 Convert__regZERO__regZERO__JumpTarget1_0, 349 Convert__JumpTarget1_0, 350 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, 351 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, 352 Convert__regZERO__JumpTarget1_0, 353 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, 354 Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, 355 Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, 356 Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, 357 Convert__FGR64AsmReg1_0__JumpTarget1_1, 358 Convert__regFCC0__JumpTarget1_0, 359 Convert__FCCAsmReg1_0__JumpTarget1_1, 360 Convert__COP2AsmReg1_0__JumpTarget1_1, 361 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, 362 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, 363 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, 364 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 365 Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 366 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, 367 Convert__Reg1_0__JumpTarget1_1, 368 Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, 369 Convert__GPRMM16AsmReg1_0__JumpTarget1_1, 370 Convert__GPR32AsmReg1_0__JumpTarget1_1, 371 Convert__GPR64AsmReg1_0__JumpTarget1_1, 372 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, 373 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, 374 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, 375 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, 376 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, 377 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, 378 Convert__MSA128AsmReg1_0__JumpTarget1_1, 379 Convert__imm_95_0__imm_95_0, 380 Convert_NoOperands, 381 Convert__ConstantUImm10_01_0__imm_95_0, 382 Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, 383 Convert__ConstantUImm4_01_0, 384 Convert__SImm161_0, 385 Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, 386 Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, 387 Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, 388 Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, 389 Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, 390 Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, 391 Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, 392 Convert__Mem2_1__ConstantUImm5_01_0, 393 Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, 394 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, 395 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, 396 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, 397 Convert__GPR32AsmReg1_0__CCRAsmReg1_1, 398 Convert__GPR32AsmReg1_0__COP2AsmReg1_1, 399 Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, 400 Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, 401 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, 402 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, 403 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, 404 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, 405 Convert__Reg1_0__Reg1_1, 406 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, 407 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, 408 Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, 409 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, 410 Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, 411 Convert__CCRAsmReg1_1__GPR32AsmReg1_0, 412 Convert__COP2AsmReg1_1__GPR32AsmReg1_0, 413 Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, 414 Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, 415 Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, 416 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, 417 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, 418 Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, 419 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, 420 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, 421 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, 422 Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, 423 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, 424 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, 425 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, 426 Convert__regZERO, 427 Convert__GPR32AsmReg1_0, 428 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, 429 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, 430 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, 431 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, 432 Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, 433 Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, 434 Convert__Reg1_1__Reg1_2, 435 Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, 436 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, 437 Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 438 Convert__GPR64AsmReg1_0__Imm1_1, 439 Convert__GPR64AsmReg1_0__Mem2_1, 440 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, 441 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, 442 Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, 443 Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, 444 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 445 Convert__GPR64AsmReg1_0__UImm161_1, 446 Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, 447 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 448 Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, 449 Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, 450 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 451 Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, 452 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, 453 Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, 454 Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, 455 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 456 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, 457 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, 458 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, 459 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, 460 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, 461 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, 462 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, 463 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, 464 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, 465 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, 466 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, 467 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, 468 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, 469 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, 470 Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, 471 Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, 472 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, 473 Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, 474 Convert__imm_95_0, 475 Convert__ConstantUImm10_01_0, 476 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, 477 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, 478 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, 479 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, 480 Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, 481 Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, 482 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 483 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 484 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 485 Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, 486 Convert__regRA__GPR32AsmReg1_0, 487 Convert__regRA_64__GPR64AsmReg1_0, 488 Convert__Reg1_0, 489 Convert__GPR32AsmReg1_0__imm_95_0, 490 Convert__GPR64AsmReg1_0__imm_95_0, 491 Convert__regZERO__GPR32AsmReg1_0, 492 Convert__GPR64AsmReg1_0, 493 Convert__regZERO_64__GPR64AsmReg1_0, 494 Convert__UImm5Lsl21_0, 495 Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, 496 Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, 497 Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, 498 Convert__GPR32AsmReg1_0__Imm1_1, 499 Convert__GPR32AsmReg1_0__Mem2_1, 500 Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, 501 Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, 502 Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, 503 Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, 504 Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 505 Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, 506 Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, 507 Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, 508 Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, 509 Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, 510 Convert__COP2AsmReg1_0__MemOffsetSimm112_1, 511 Convert__COP2AsmReg1_0__MemOffsetSimm162_1, 512 Convert__COP3AsmReg1_0__Mem2_1, 513 Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, 514 Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, 515 Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 516 Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 517 Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 518 Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, 519 Convert__StrictlyFGR64AsmReg1_0__Imm1_1, 520 Convert__StrictlyFGR32AsmReg1_0__Imm1_1, 521 Convert__GPRMM16AsmReg1_0__UImm7_N11_1, 522 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, 523 Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, 524 Convert__GPR32AsmReg1_0__UImm161_1, 525 Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, 526 Convert__Reg1_0__Imm1_1__imm_95_0, 527 Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, 528 Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, 529 Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, 530 Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, 531 Convert__RegList1_0__Mem2_1, 532 Convert__RegList161_0__MemOffsetUimm42_1, 533 ConvertCustom_ConvertXWPOperands, 534 Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, 535 Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, 536 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, 537 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, 538 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, 539 Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, 540 Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, 541 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, 542 Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, 543 Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, 544 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, 545 Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, 546 Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, 547 Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, 548 Convert__GPR32AsmReg1_0__regAC0, 549 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, 550 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, 551 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, 552 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, 553 Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, 554 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 555 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 556 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 557 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, 558 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 559 Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 560 Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 561 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, 562 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 563 Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, 564 Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, 565 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, 566 Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, 567 Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, 568 Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, 569 Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, 570 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, 571 Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, 572 Convert__regAC0__GPR32AsmReg1_0, 573 Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, 574 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, 575 Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, 576 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 577 Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, 578 Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, 579 Convert__regZERO__regZERO__imm_95_0, 580 Convert__regZERO__regS0, 581 Convert__regZERO__regZERO, 582 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, 583 Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, 584 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, 585 Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, 586 Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, 587 Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, 588 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, 589 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, 590 Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, 591 Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, 592 Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, 593 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, 594 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, 595 Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, 596 Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, 597 Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, 598 Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, 599 Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, 600 Convert__ConstantUImm20_01_0, 601 Convert__Reg1_0__Tie0_1_1, 602 Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, 603 Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, 604 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, 605 Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, 606 Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, 607 Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, 608 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, 609 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, 610 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, 611 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, 612 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, 613 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, 614 Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, 615 Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, 616 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, 617 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, 618 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, 619 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, 620 Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, 621 Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 622 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 623 Convert__ConstantUImm5_01_0, 624 Convert__MemOffsetSimm162_0, 625 Convert__imm_95_2, 626 Convert__imm_95_6, 627 Convert__imm_95_4, 628 Convert__imm_95_5, 629 Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, 630 Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, 631 Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, 632 Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, 633 Convert__GPR32AsmReg1_0__imm_95_31, 634 CVT_NUM_SIGNATURES 635}; 636 637} // end anonymous namespace 638 639static const uint8_t ConversionTable[CVT_NUM_SIGNATURES][11] = { 640 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1 641 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 642 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1 643 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 644 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1 645 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 646 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1 647 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 648 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1 649 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 650 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1 651 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, 652 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 653 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 654 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2 655 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, 656 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 657 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, 658 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 659 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 660 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 661 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 662 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1 663 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 664 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2 665 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, 666 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1 667 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 668 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1 669 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 670 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2 671 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 672 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2 673 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 674 // Convert__SImm161_1 675 { CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 676 // Convert__Reg1_0__SImm161_1 677 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 678 // Convert__Reg1_0__SImm161_2 679 { CVT_95_Reg, 1, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 680 // Convert__Reg1_0__Reg1_1__SImm161_2 681 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 682 // Convert__Reg1_0__Tie0_1_1__SImm161_1 683 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 684 // Convert__GPR32AsmReg1_0__Simm19_Lsl21_1 685 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 686 // Convert__GPRMM16AsmReg1_0__Imm1_1 687 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 688 // Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1 689 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 690 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2 691 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 692 // Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1 693 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_, 2, CVT_Done }, 694 // Convert__Imm1_0 695 { CVT_95_addImmOperands, 1, CVT_Done }, 696 // Convert__Reg1_0__Reg1_1__Reg1_2 697 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 698 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2 699 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_95_addGPRMM16AsmRegOperands, 3, CVT_Done }, 700 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2 701 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 702 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3 703 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 704 // Convert__GPR32AsmReg1_0__SImm161_1 705 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 706 // Convert__Reg1_0__Tie0_1_1__Reg1_1 707 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_95_Reg, 2, CVT_Done }, 708 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1 709 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 710 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1 711 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 712 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2 713 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, 714 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2 715 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 716 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1 717 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 718 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2 719 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, 720 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1 721 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 722 // Convert__regZERO__regZERO__JumpTarget1_0 723 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, 724 // Convert__JumpTarget1_0 725 { CVT_95_addImmOperands, 1, CVT_Done }, 726 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1 727 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 728 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2 729 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, 730 // Convert__regZERO__JumpTarget1_0 731 { CVT_regZERO, 0, CVT_95_addImmOperands, 1, CVT_Done }, 732 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1 733 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 734 // Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2 735 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, 736 // Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2 737 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, 738 // Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2 739 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addImmOperands, 3, CVT_Done }, 740 // Convert__FGR64AsmReg1_0__JumpTarget1_1 741 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 742 // Convert__regFCC0__JumpTarget1_0 743 { CVT_regFCC0, 0, CVT_95_addImmOperands, 1, CVT_Done }, 744 // Convert__FCCAsmReg1_0__JumpTarget1_1 745 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 746 // Convert__COP2AsmReg1_0__JumpTarget1_1 747 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 748 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2 749 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 750 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2 751 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, 752 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2 753 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 754 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2 755 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 756 // Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2 757 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 758 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2 759 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 760 // Convert__Reg1_0__JumpTarget1_1 761 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_Done }, 762 // Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1 763 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addImmOperands, 2, CVT_Done }, 764 // Convert__GPRMM16AsmReg1_0__JumpTarget1_1 765 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 766 // Convert__GPR32AsmReg1_0__JumpTarget1_1 767 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 768 // Convert__GPR64AsmReg1_0__JumpTarget1_1 769 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 770 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2 771 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addMSA128AsmRegOperands, 3, CVT_Done }, 772 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2 773 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 774 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2 775 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, 776 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2 777 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 778 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2 779 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 780 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2 781 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, 782 // Convert__MSA128AsmReg1_0__JumpTarget1_1 783 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 784 // Convert__imm_95_0__imm_95_0 785 { CVT_imm_95_0, 0, CVT_imm_95_0, 0, CVT_Done }, 786 // Convert_NoOperands 787 { CVT_Done }, 788 // Convert__ConstantUImm10_01_0__imm_95_0 789 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_imm_95_0, 0, CVT_Done }, 790 // Convert__ConstantUImm10_01_0__ConstantUImm10_01_1 791 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 792 // Convert__ConstantUImm4_01_0 793 { CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 1, CVT_Done }, 794 // Convert__SImm161_0 795 { CVT_95_addSImmOperands_LT_16_GT_, 1, CVT_Done }, 796 // Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1 797 { CVT_regFCC0, 0, CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 798 // Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1 799 { CVT_regFCC0, 0, CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 800 // Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2 801 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_Done }, 802 // Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 803 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 804 // Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1 805 { CVT_regFCC0, 0, CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 806 // Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2 807 { CVT_95_addFCCAsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 808 // Convert__MemOffsetSimm92_1__ConstantUImm5_01_0 809 { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 810 // Convert__Mem2_1__ConstantUImm5_01_0 811 { CVT_95_addMemOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 812 // Convert__FGR64AsmReg1_0__FGR32AsmReg1_1 813 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 814 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1 815 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 816 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1 817 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 818 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2 819 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 820 // Convert__GPR32AsmReg1_0__CCRAsmReg1_1 821 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCCRAsmRegOperands, 2, CVT_Done }, 822 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1 823 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_Done }, 824 // Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1 825 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSACtrlAsmRegOperands, 2, CVT_Done }, 826 // Convert__GPR32AsmReg1_0__FGR32AsmReg1_1 827 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 828 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2 829 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 830 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2 831 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 832 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3 833 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, 834 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3 835 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 4, CVT_Done }, 836 // Convert__Reg1_0__Reg1_1 837 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_Done }, 838 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2 839 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 840 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 841 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, 842 // Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 843 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, 844 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 845 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 846 // Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 847 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 848 // Convert__CCRAsmReg1_1__GPR32AsmReg1_0 849 { CVT_95_addCCRAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 850 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0 851 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 852 // Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1 853 { CVT_95_addMSACtrlAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 854 // Convert__FGR32AsmReg1_1__GPR32AsmReg1_0 855 { CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 856 // Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1 857 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_Done }, 858 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1 859 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_16_GT_, 2, CVT_Done }, 860 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2 861 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 862 // Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2 863 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_2, CVT_95_addSImmOperands_LT_16_GT_, 3, CVT_Done }, 864 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3 865 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 866 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2 867 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addUImmOperands_LT_16_GT_, 3, CVT_Done }, 868 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1 869 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 870 // Convert__GPR64AsmReg1_1__GPR64AsmReg1_2 871 { CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_Done }, 872 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3 873 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_, 4, CVT_Done }, 874 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3 875 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, 876 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3 877 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, 878 // Convert__regZERO 879 { CVT_regZERO, 0, CVT_Done }, 880 // Convert__GPR32AsmReg1_0 881 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 882 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1 883 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addImmOperands, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 884 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1 885 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 886 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1 887 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 888 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1 889 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, 890 // Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1 891 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 892 // Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1 893 { CVT_95_addGPR32ZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 894 // Convert__Reg1_1__Reg1_2 895 { CVT_95_Reg, 2, CVT_95_Reg, 3, CVT_Done }, 896 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_2 897 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 898 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2 899 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, 900 // Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 901 { CVT_95_addGPR32NonZeroAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 902 // Convert__GPR64AsmReg1_0__Imm1_1 903 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 904 // Convert__GPR64AsmReg1_0__Mem2_1 905 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 906 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3 907 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, 908 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0 909 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 910 // Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 911 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 912 // Convert__GPR64AsmReg1_0__FGR64AsmReg1_1 913 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 914 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0 915 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 916 // Convert__GPR64AsmReg1_0__UImm161_1 917 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 918 // Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 919 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 920 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0 921 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 922 // Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 923 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 924 // Convert__FGR64AsmReg1_1__GPR64AsmReg1_0 925 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 926 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0 927 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 928 // Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2 929 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 930 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2 931 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addSImmOperands_LT_32_GT_, 3, CVT_Done }, 932 // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0 933 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 934 // Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1 935 { CVT_95_addGPR64AsmRegOperands, 1, CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 936 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 937 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 938 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0 939 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 940 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1 941 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addSImmOperands_LT_32_GT_, 2, CVT_Done }, 942 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1 943 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 2, CVT_Done }, 944 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2 945 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_, 3, CVT_Done }, 946 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1 947 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, 948 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2 949 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 950 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2 951 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 952 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1 953 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 954 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1 955 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 956 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2 957 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 958 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3 959 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Done }, 960 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2 961 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 962 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2 963 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 964 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1 965 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_Done }, 966 // Convert__MSA128AsmReg1_0__GPR32AsmReg1_1 967 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 968 // Convert__MSA128AsmReg1_0__GPR64AsmReg1_1 969 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_Done }, 970 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2 971 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 972 // Convert__GPR32AsmReg1_0__ConstantUImm2_01_1 973 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 2, CVT_Done }, 974 // Convert__imm_95_0 975 { CVT_imm_95_0, 0, CVT_Done }, 976 // Convert__ConstantUImm10_01_0 977 { CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 1, CVT_Done }, 978 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1 979 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_, 4, CVT_Tied, Tie0_1_1, CVT_Done }, 980 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2 981 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 982 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2 983 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR64AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_Done }, 984 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2 985 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 986 // Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2 987 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_Done }, 988 // Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1 989 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 990 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6 991 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 992 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6 993 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 994 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6 995 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 996 // Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6 997 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 3, CVT_95_addMSA128AsmRegOperands, 5, CVT_95_addConstantUImmOperands_LT_1_GT_, 7, CVT_Done }, 998 // Convert__regRA__GPR32AsmReg1_0 999 { CVT_regRA, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1000 // Convert__regRA_64__GPR64AsmReg1_0 1001 { CVT_regRA_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 1002 // Convert__Reg1_0 1003 { CVT_95_Reg, 1, CVT_Done }, 1004 // Convert__GPR32AsmReg1_0__imm_95_0 1005 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1006 // Convert__GPR64AsmReg1_0__imm_95_0 1007 { CVT_95_addGPR64AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1008 // Convert__regZERO__GPR32AsmReg1_0 1009 { CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1010 // Convert__GPR64AsmReg1_0 1011 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 1012 // Convert__regZERO_64__GPR64AsmReg1_0 1013 { CVT_regZERO_64, 0, CVT_95_addGPR64AsmRegOperands, 1, CVT_Done }, 1014 // Convert__UImm5Lsl21_0 1015 { CVT_95_addImmOperands, 1, CVT_Done }, 1016 // Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1 1017 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1018 // Convert__FGR64AsmReg1_0__MemOffsetSimm162_1 1019 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1020 // Convert__FGR32AsmReg1_0__MemOffsetSimm162_1 1021 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1022 // Convert__GPR32AsmReg1_0__Imm1_1 1023 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1024 // Convert__GPR32AsmReg1_0__Mem2_1 1025 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1026 // Convert__GPR32AsmReg1_0__MemOffsetSimm162_1 1027 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1028 // Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1 1029 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1030 // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1 1031 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1032 // Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1 1033 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, 1034 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1035 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1036 // Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1 1037 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1038 // Convert__MSA128AsmReg1_0__MemOffsetSimm102_1 1039 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1040 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1 1041 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1042 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1 1043 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1044 // Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1 1045 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1046 // Convert__COP2AsmReg1_0__MemOffsetSimm112_1 1047 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1048 // Convert__COP2AsmReg1_0__MemOffsetSimm162_1 1049 { CVT_95_addCOP2AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1050 // Convert__COP3AsmReg1_0__Mem2_1 1051 { CVT_95_addCOP3AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1052 // Convert__MSA128AsmReg1_0__ConstantSImm10_01_1 1053 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1054 // Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1 1055 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1056 // Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1057 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1058 // Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1059 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1060 // Convert__GPR32AsmReg1_0__UImm32_Coerced1_1 1061 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_32_GT_, 2, CVT_Done }, 1062 // Convert__StrictlyAFGR64AsmReg1_0__Imm1_1 1063 { CVT_95_addStrictlyAFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1064 // Convert__StrictlyFGR64AsmReg1_0__Imm1_1 1065 { CVT_95_addStrictlyFGR64AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1066 // Convert__StrictlyFGR32AsmReg1_0__Imm1_1 1067 { CVT_95_addStrictlyFGR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1068 // Convert__GPRMM16AsmReg1_0__UImm7_N11_1 1069 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_, 2, CVT_Done }, 1070 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3 1071 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, 1072 // Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3 1073 { CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_, 4, CVT_Done }, 1074 // Convert__GPR32AsmReg1_0__UImm161_1 1075 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 1076 // Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1 1077 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addUImmOperands_LT_16_GT_, 2, CVT_Done }, 1078 // Convert__Reg1_0__Imm1_1__imm_95_0 1079 { CVT_95_Reg, 1, CVT_95_addImmOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1080 // Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1 1081 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1082 // Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1 1083 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1084 // Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1 1085 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1086 // Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1 1087 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1088 // Convert__RegList1_0__Mem2_1 1089 { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1090 // Convert__RegList161_0__MemOffsetUimm42_1 1091 { CVT_95_addRegListOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1092 // ConvertCustom_ConvertXWPOperands 1093 { CVT_ConvertXWPOperands, 0, CVT_Done }, 1094 // Convert__GPR32AsmReg1_0__MemOffsetSimm122_1 1095 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addMemOperands, 2, CVT_Done }, 1096 // Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1 1097 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1098 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3 1099 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addAFGR64AsmRegOperands, 3, CVT_95_addAFGR64AsmRegOperands, 4, CVT_Done }, 1100 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3 1101 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_95_addFGR64AsmRegOperands, 4, CVT_Done }, 1102 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3 1103 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_95_addFGR32AsmRegOperands, 4, CVT_Done }, 1104 // Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2 1105 { CVT_95_addFGR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFGR64AsmRegOperands, 3, CVT_Done }, 1106 // Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2 1107 { CVT_95_addFGR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFGR32AsmRegOperands, 3, CVT_Done }, 1108 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0 1109 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1110 // Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2 1111 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1112 // Convert__GPR32AsmReg1_0__FGR64AsmReg1_1 1113 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_Done }, 1114 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0 1115 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1116 // Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2 1117 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1118 // Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1 1119 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_Done }, 1120 // Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1 1121 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addACC64DSPAsmRegOperands, 2, CVT_Done }, 1122 // Convert__GPR32AsmReg1_0__regAC0 1123 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regAC0, 0, CVT_Done }, 1124 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0 1125 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1126 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 1127 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, 1128 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO 1129 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_regZERO, 0, CVT_Done }, 1130 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64 1131 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_regZERO_64, 0, CVT_Done }, 1132 // Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2 1133 { CVT_95_addMovePRegPairOperands, 1, CVT_95_addGPRMM16AsmRegMovePOperands, 2, CVT_95_addGPRMM16AsmRegMovePOperands, 3, CVT_Done }, 1134 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1135 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1136 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1137 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1138 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1139 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1140 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1 1141 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addFCCAsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1142 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1143 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1144 // Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1145 { CVT_95_addAFGR64AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1146 // Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1147 { CVT_95_addFGR64AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1148 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1 1149 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Tied, Tie0_1_1, CVT_Done }, 1150 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0 1151 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1152 // Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 1153 { CVT_95_addCOP0AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1154 // Convert__FGR64AsmReg1_1__GPR32AsmReg1_0 1155 { CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1156 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0 1157 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_0, 0, CVT_Done }, 1158 // Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2 1159 { CVT_95_addCOP2AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1160 // Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 1161 { CVT_95_addAFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1162 // Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0 1163 { CVT_95_addFGR64AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1164 // Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0 1165 { CVT_95_addHI32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1166 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1 1167 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_Done }, 1168 // Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0 1169 { CVT_95_addLO32DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1170 // Convert__regAC0__GPR32AsmReg1_0 1171 { CVT_regAC0, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1172 // Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0 1173 { CVT_95_addACC64DSPAsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1174 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0 1175 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1176 // Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4 1177 { CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 3, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 5, CVT_Done }, 1178 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2 1179 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1180 // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0 1181 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1182 // Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1 1183 { CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1184 // Convert__regZERO__regZERO__imm_95_0 1185 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_imm_95_0, 0, CVT_Done }, 1186 // Convert__regZERO__regS0 1187 { CVT_regZERO, 0, CVT_regS0, 0, CVT_Done }, 1188 // Convert__regZERO__regZERO 1189 { CVT_regZERO, 0, CVT_regZERO, 0, CVT_Done }, 1190 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO 1191 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_regZERO, 0, CVT_Done }, 1192 // Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1 1193 { CVT_95_addGPRMM16AsmRegOperands, 1, CVT_95_addGPRMM16AsmRegOperands, 2, CVT_Done }, 1194 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0 1195 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1196 // Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0 1197 { CVT_95_addGPR32AsmRegOperands, 4, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 1198 // Convert__GPR32AsmReg1_0__ConstantUImm7_01_1 1199 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_, 2, CVT_Done }, 1200 // Convert__GPR32AsmReg1_0__ConstantUImm10_01_1 1201 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1202 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0 1203 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_imm_95_0, 0, CVT_Done }, 1204 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2 1205 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1206 // Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2 1207 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addHWRegsAsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 3, CVT_Done }, 1208 // Convert__GPR32AsmReg1_0__ConstantSImm10_01_1 1209 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1210 // Convert__GPR32AsmReg1_0__ConstantUImm8_01_1 1211 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_, 2, CVT_Done }, 1212 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1 1213 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 2, CVT_Done }, 1214 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2 1215 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 1216 // Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1 1217 { CVT_95_addGPRMM16AsmRegZeroOperands, 1, CVT_95_addMicroMipsMemOperands, 2, CVT_Done }, 1218 // Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1 1219 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1220 // Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1 1221 { CVT_95_addGPR32AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1222 // Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1 1223 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1224 // Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1 1225 { CVT_95_addGPR64AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMemOperands, 2, CVT_Done }, 1226 // Convert__ConstantUImm20_01_0 1227 { CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_, 1, CVT_Done }, 1228 // Convert__Reg1_0__Tie0_1_1 1229 { CVT_95_Reg, 1, CVT_Tied, Tie0_1_1, CVT_Done }, 1230 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1 1231 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 2, CVT_Done }, 1232 // Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2 1233 { CVT_95_addGPR64AsmRegOperands, 1, CVT_95_addGPR64AsmRegOperands, 2, CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, 1234 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0 1235 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 1, CVT_Done }, 1236 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1 1237 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 3, CVT_95_addGPR32AsmRegOperands, 2, CVT_Done }, 1238 // Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1 1239 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1240 // Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1 1241 { CVT_95_addACC64DSPAsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_Tied, Tie0_1_1, CVT_Done }, 1242 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2 1243 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 3, CVT_Done }, 1244 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2 1245 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 3, CVT_Done }, 1246 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3 1247 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, 1248 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3 1249 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, 1250 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3 1251 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, 1252 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3 1253 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 1254 // Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3 1255 { CVT_95_addMSA128AsmRegOperands, 1, CVT_Tied, Tie0_1_1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 1256 // Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2 1257 { CVT_95_Reg, 1, CVT_95_Reg, 2, CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 3, CVT_Done }, 1258 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3 1259 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 4, CVT_Done }, 1260 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3 1261 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_, 4, CVT_Done }, 1262 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3 1263 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_, 4, CVT_Done }, 1264 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3 1265 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_, 4, CVT_Done }, 1266 // Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3 1267 { CVT_95_addMSA128AsmRegOperands, 1, CVT_95_addMSA128AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_, 4, CVT_Done }, 1268 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1 1269 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addImmOperands, 2, CVT_Done }, 1270 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2 1271 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addImmOperands, 3, CVT_Done }, 1272 // Convert__ConstantUImm5_01_0 1273 { CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_, 1, CVT_Done }, 1274 // Convert__MemOffsetSimm162_0 1275 { CVT_95_addMemOperands, 1, CVT_Done }, 1276 // Convert__imm_95_2 1277 { CVT_imm_95_2, 0, CVT_Done }, 1278 // Convert__imm_95_6 1279 { CVT_imm_95_6, 0, CVT_Done }, 1280 // Convert__imm_95_4 1281 { CVT_imm_95_4, 0, CVT_Done }, 1282 // Convert__imm_95_5 1283 { CVT_imm_95_5, 0, CVT_Done }, 1284 // Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2 1285 { CVT_95_addGPR32AsmRegOperands, 1, CVT_95_addGPR32AsmRegOperands, 2, CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_, 3, CVT_Done }, 1286 // Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2 1287 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addAFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1288 // Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2 1289 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR64AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1290 // Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2 1291 { CVT_95_addFGR32AsmRegOperands, 1, CVT_95_addFGR32AsmRegOperands, 2, CVT_95_addGPR32AsmRegOperands, 3, CVT_Done }, 1292 // Convert__GPR32AsmReg1_0__imm_95_31 1293 { CVT_95_addGPR32AsmRegOperands, 1, CVT_imm_95_31, 0, CVT_Done }, 1294}; 1295 1296void MipsAsmParser:: 1297convertToMCInst(unsigned Kind, MCInst &Inst, unsigned Opcode, 1298 const OperandVector &Operands) { 1299 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1300 const uint8_t *Converter = ConversionTable[Kind]; 1301 unsigned OpIdx; 1302 Inst.setOpcode(Opcode); 1303 for (const uint8_t *p = Converter; *p; p+= 2) { 1304 OpIdx = *(p + 1); 1305 switch (*p) { 1306 default: llvm_unreachable("invalid conversion entry!"); 1307 case CVT_Reg: 1308 static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1309 break; 1310 case CVT_Tied: { 1311 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 1312 std::begin(TiedAsmOperandTable)) && 1313 "Tied operand not found"); 1314 unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0]; 1315 if (TiedResOpnd != (uint8_t) -1) 1316 Inst.addOperand(Inst.getOperand(TiedResOpnd)); 1317 break; 1318 } 1319 case CVT_95_addGPR32AsmRegOperands: 1320 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32AsmRegOperands(Inst, 1); 1321 break; 1322 case CVT_95_addAFGR64AsmRegOperands: 1323 static_cast<MipsOperand&>(*Operands[OpIdx]).addAFGR64AsmRegOperands(Inst, 1); 1324 break; 1325 case CVT_95_addFGR64AsmRegOperands: 1326 static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR64AsmRegOperands(Inst, 1); 1327 break; 1328 case CVT_95_addFGR32AsmRegOperands: 1329 static_cast<MipsOperand&>(*Operands[OpIdx]).addFGR32AsmRegOperands(Inst, 1); 1330 break; 1331 case CVT_95_addSImmOperands_LT_32_GT_: 1332 static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<32>(Inst, 1); 1333 break; 1334 case CVT_95_addMSA128AsmRegOperands: 1335 static_cast<MipsOperand&>(*Operands[OpIdx]).addMSA128AsmRegOperands(Inst, 1); 1336 break; 1337 case CVT_95_addSImmOperands_LT_16_GT_: 1338 static_cast<MipsOperand&>(*Operands[OpIdx]).addSImmOperands<16>(Inst, 1); 1339 break; 1340 case CVT_95_Reg: 1341 static_cast<MipsOperand&>(*Operands[OpIdx]).addRegOperands(Inst, 1); 1342 break; 1343 case CVT_95_addImmOperands: 1344 static_cast<MipsOperand&>(*Operands[OpIdx]).addImmOperands(Inst, 1); 1345 break; 1346 case CVT_95_addGPRMM16AsmRegOperands: 1347 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegOperands(Inst, 1); 1348 break; 1349 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: 1350 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<4, 0>(Inst, 1); 1351 break; 1352 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: 1353 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 0>(Inst, 1); 1354 break; 1355 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: 1356 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 0>(Inst, 1); 1357 break; 1358 case CVT_95_addUImmOperands_LT_16_GT_: 1359 static_cast<MipsOperand&>(*Operands[OpIdx]).addUImmOperands<16>(Inst, 1); 1360 break; 1361 case CVT_95_addGPR64AsmRegOperands: 1362 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR64AsmRegOperands(Inst, 1); 1363 break; 1364 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: 1365 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<8, 0>(Inst, 1); 1366 break; 1367 case CVT_regZERO: 1368 Inst.addOperand(MCOperand::createReg(Mips::ZERO)); 1369 break; 1370 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: 1371 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32, -32>(Inst, 1); 1372 break; 1373 case CVT_regFCC0: 1374 Inst.addOperand(MCOperand::createReg(Mips::FCC0)); 1375 break; 1376 case CVT_95_addFCCAsmRegOperands: 1377 static_cast<MipsOperand&>(*Operands[OpIdx]).addFCCAsmRegOperands(Inst, 1); 1378 break; 1379 case CVT_95_addCOP2AsmRegOperands: 1380 static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP2AsmRegOperands(Inst, 1); 1381 break; 1382 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: 1383 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<3, 0>(Inst, 1); 1384 break; 1385 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: 1386 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<6, 0>(Inst, 1); 1387 break; 1388 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: 1389 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<4, 0>(Inst, 1); 1390 break; 1391 case CVT_imm_95_0: 1392 Inst.addOperand(MCOperand::createImm(0)); 1393 break; 1394 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: 1395 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<10, 0>(Inst, 1); 1396 break; 1397 case CVT_95_addMemOperands: 1398 static_cast<MipsOperand&>(*Operands[OpIdx]).addMemOperands(Inst, 2); 1399 break; 1400 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: 1401 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<5, 0>(Inst, 1); 1402 break; 1403 case CVT_95_addCCRAsmRegOperands: 1404 static_cast<MipsOperand&>(*Operands[OpIdx]).addCCRAsmRegOperands(Inst, 1); 1405 break; 1406 case CVT_95_addMSACtrlAsmRegOperands: 1407 static_cast<MipsOperand&>(*Operands[OpIdx]).addMSACtrlAsmRegOperands(Inst, 1); 1408 break; 1409 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: 1410 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1, 0>(Inst, 1); 1411 break; 1412 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: 1413 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 33>(Inst, 1); 1414 break; 1415 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: 1416 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 32>(Inst, 1); 1417 break; 1418 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: 1419 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<5, 1>(Inst, 1); 1420 break; 1421 case CVT_95_addGPR32NonZeroAsmRegOperands: 1422 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32NonZeroAsmRegOperands(Inst, 1); 1423 break; 1424 case CVT_95_addGPR32ZeroAsmRegOperands: 1425 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPR32ZeroAsmRegOperands(Inst, 1); 1426 break; 1427 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: 1428 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<2, 1>(Inst, 1); 1429 break; 1430 case CVT_95_addCOP0AsmRegOperands: 1431 static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP0AsmRegOperands(Inst, 1); 1432 break; 1433 case CVT_regZERO_64: 1434 Inst.addOperand(MCOperand::createReg(Mips::ZERO_64)); 1435 break; 1436 case CVT_95_addACC64DSPAsmRegOperands: 1437 static_cast<MipsOperand&>(*Operands[OpIdx]).addACC64DSPAsmRegOperands(Inst, 1); 1438 break; 1439 case CVT_95_addConstantUImmOperands_LT_1_GT_: 1440 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<1>(Inst, 1); 1441 break; 1442 case CVT_regRA: 1443 Inst.addOperand(MCOperand::createReg(Mips::RA)); 1444 break; 1445 case CVT_regRA_64: 1446 Inst.addOperand(MCOperand::createReg(Mips::RA_64)); 1447 break; 1448 case CVT_95_addMicroMipsMemOperands: 1449 static_cast<MipsOperand&>(*Operands[OpIdx]).addMicroMipsMemOperands(Inst, 2); 1450 break; 1451 case CVT_95_addCOP3AsmRegOperands: 1452 static_cast<MipsOperand&>(*Operands[OpIdx]).addCOP3AsmRegOperands(Inst, 1); 1453 break; 1454 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: 1455 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<10, 0>(Inst, 1); 1456 break; 1457 case CVT_95_addConstantUImmOperands_LT_32_GT_: 1458 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<32>(Inst, 1); 1459 break; 1460 case CVT_95_addStrictlyAFGR64AsmRegOperands: 1461 static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyAFGR64AsmRegOperands(Inst, 1); 1462 break; 1463 case CVT_95_addStrictlyFGR64AsmRegOperands: 1464 static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR64AsmRegOperands(Inst, 1); 1465 break; 1466 case CVT_95_addStrictlyFGR32AsmRegOperands: 1467 static_cast<MipsOperand&>(*Operands[OpIdx]).addStrictlyFGR32AsmRegOperands(Inst, 1); 1468 break; 1469 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: 1470 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, -1>(Inst, 1); 1471 break; 1472 case CVT_95_addRegListOperands: 1473 static_cast<MipsOperand&>(*Operands[OpIdx]).addRegListOperands(Inst, 1); 1474 break; 1475 case CVT_ConvertXWPOperands: 1476 ConvertXWPOperands(Inst, Operands); 1477 break; 1478 case CVT_regAC0: 1479 Inst.addOperand(MCOperand::createReg(Mips::AC0)); 1480 break; 1481 case CVT_95_addMovePRegPairOperands: 1482 static_cast<MipsOperand&>(*Operands[OpIdx]).addMovePRegPairOperands(Inst, 2); 1483 break; 1484 case CVT_95_addGPRMM16AsmRegMovePOperands: 1485 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegMovePOperands(Inst, 1); 1486 break; 1487 case CVT_95_addHI32DSPAsmRegOperands: 1488 static_cast<MipsOperand&>(*Operands[OpIdx]).addHI32DSPAsmRegOperands(Inst, 1); 1489 break; 1490 case CVT_95_addLO32DSPAsmRegOperands: 1491 static_cast<MipsOperand&>(*Operands[OpIdx]).addLO32DSPAsmRegOperands(Inst, 1); 1492 break; 1493 case CVT_regS0: 1494 Inst.addOperand(MCOperand::createReg(Mips::S0)); 1495 break; 1496 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: 1497 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<7, 0>(Inst, 1); 1498 break; 1499 case CVT_95_addHWRegsAsmRegOperands: 1500 static_cast<MipsOperand&>(*Operands[OpIdx]).addHWRegsAsmRegOperands(Inst, 1); 1501 break; 1502 case CVT_95_addGPRMM16AsmRegZeroOperands: 1503 static_cast<MipsOperand&>(*Operands[OpIdx]).addGPRMM16AsmRegZeroOperands(Inst, 1); 1504 break; 1505 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: 1506 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantUImmOperands<20, 0>(Inst, 1); 1507 break; 1508 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: 1509 static_cast<MipsOperand&>(*Operands[OpIdx]).addConstantSImmOperands<6, 0>(Inst, 1); 1510 break; 1511 case CVT_imm_95_2: 1512 Inst.addOperand(MCOperand::createImm(2)); 1513 break; 1514 case CVT_imm_95_6: 1515 Inst.addOperand(MCOperand::createImm(6)); 1516 break; 1517 case CVT_imm_95_4: 1518 Inst.addOperand(MCOperand::createImm(4)); 1519 break; 1520 case CVT_imm_95_5: 1521 Inst.addOperand(MCOperand::createImm(5)); 1522 break; 1523 case CVT_imm_95_31: 1524 Inst.addOperand(MCOperand::createImm(31)); 1525 break; 1526 } 1527 } 1528} 1529 1530void MipsAsmParser:: 1531convertToMapAndConstraints(unsigned Kind, 1532 const OperandVector &Operands) { 1533 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 1534 unsigned NumMCOperands = 0; 1535 const uint8_t *Converter = ConversionTable[Kind]; 1536 for (const uint8_t *p = Converter; *p; p+= 2) { 1537 switch (*p) { 1538 default: llvm_unreachable("invalid conversion entry!"); 1539 case CVT_Reg: 1540 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1541 Operands[*(p + 1)]->setConstraint("r"); 1542 ++NumMCOperands; 1543 break; 1544 case CVT_Tied: 1545 ++NumMCOperands; 1546 break; 1547 case CVT_95_addGPR32AsmRegOperands: 1548 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1549 Operands[*(p + 1)]->setConstraint("m"); 1550 NumMCOperands += 1; 1551 break; 1552 case CVT_95_addAFGR64AsmRegOperands: 1553 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1554 Operands[*(p + 1)]->setConstraint("m"); 1555 NumMCOperands += 1; 1556 break; 1557 case CVT_95_addFGR64AsmRegOperands: 1558 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1559 Operands[*(p + 1)]->setConstraint("m"); 1560 NumMCOperands += 1; 1561 break; 1562 case CVT_95_addFGR32AsmRegOperands: 1563 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1564 Operands[*(p + 1)]->setConstraint("m"); 1565 NumMCOperands += 1; 1566 break; 1567 case CVT_95_addSImmOperands_LT_32_GT_: 1568 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1569 Operands[*(p + 1)]->setConstraint("m"); 1570 NumMCOperands += 1; 1571 break; 1572 case CVT_95_addMSA128AsmRegOperands: 1573 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1574 Operands[*(p + 1)]->setConstraint("m"); 1575 NumMCOperands += 1; 1576 break; 1577 case CVT_95_addSImmOperands_LT_16_GT_: 1578 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1579 Operands[*(p + 1)]->setConstraint("m"); 1580 NumMCOperands += 1; 1581 break; 1582 case CVT_95_Reg: 1583 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1584 Operands[*(p + 1)]->setConstraint("r"); 1585 NumMCOperands += 1; 1586 break; 1587 case CVT_95_addImmOperands: 1588 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1589 Operands[*(p + 1)]->setConstraint("m"); 1590 NumMCOperands += 1; 1591 break; 1592 case CVT_95_addGPRMM16AsmRegOperands: 1593 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1594 Operands[*(p + 1)]->setConstraint("m"); 1595 NumMCOperands += 1; 1596 break; 1597 case CVT_95_addConstantSImmOperands_LT_4_44__32_0_GT_: 1598 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1599 Operands[*(p + 1)]->setConstraint("m"); 1600 NumMCOperands += 1; 1601 break; 1602 case CVT_95_addConstantUImmOperands_LT_5_44__32_0_GT_: 1603 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1604 Operands[*(p + 1)]->setConstraint("m"); 1605 NumMCOperands += 1; 1606 break; 1607 case CVT_95_addConstantUImmOperands_LT_2_44__32_0_GT_: 1608 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1609 Operands[*(p + 1)]->setConstraint("m"); 1610 NumMCOperands += 1; 1611 break; 1612 case CVT_95_addUImmOperands_LT_16_GT_: 1613 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1614 Operands[*(p + 1)]->setConstraint("m"); 1615 NumMCOperands += 1; 1616 break; 1617 case CVT_95_addGPR64AsmRegOperands: 1618 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1619 Operands[*(p + 1)]->setConstraint("m"); 1620 NumMCOperands += 1; 1621 break; 1622 case CVT_95_addConstantUImmOperands_LT_8_44__32_0_GT_: 1623 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1624 Operands[*(p + 1)]->setConstraint("m"); 1625 NumMCOperands += 1; 1626 break; 1627 case CVT_regZERO: 1628 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1629 Operands[*(p + 1)]->setConstraint("m"); 1630 ++NumMCOperands; 1631 break; 1632 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_44__32__MINUS_32_GT_: 1633 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1634 Operands[*(p + 1)]->setConstraint("m"); 1635 NumMCOperands += 1; 1636 break; 1637 case CVT_regFCC0: 1638 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1639 Operands[*(p + 1)]->setConstraint("m"); 1640 ++NumMCOperands; 1641 break; 1642 case CVT_95_addFCCAsmRegOperands: 1643 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1644 Operands[*(p + 1)]->setConstraint("m"); 1645 NumMCOperands += 1; 1646 break; 1647 case CVT_95_addCOP2AsmRegOperands: 1648 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1649 Operands[*(p + 1)]->setConstraint("m"); 1650 NumMCOperands += 1; 1651 break; 1652 case CVT_95_addConstantUImmOperands_LT_3_44__32_0_GT_: 1653 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1654 Operands[*(p + 1)]->setConstraint("m"); 1655 NumMCOperands += 1; 1656 break; 1657 case CVT_95_addConstantUImmOperands_LT_6_44__32_0_GT_: 1658 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1659 Operands[*(p + 1)]->setConstraint("m"); 1660 NumMCOperands += 1; 1661 break; 1662 case CVT_95_addConstantUImmOperands_LT_4_44__32_0_GT_: 1663 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1664 Operands[*(p + 1)]->setConstraint("m"); 1665 NumMCOperands += 1; 1666 break; 1667 case CVT_imm_95_0: 1668 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1669 Operands[*(p + 1)]->setConstraint(""); 1670 ++NumMCOperands; 1671 break; 1672 case CVT_95_addConstantUImmOperands_LT_10_44__32_0_GT_: 1673 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1674 Operands[*(p + 1)]->setConstraint("m"); 1675 NumMCOperands += 1; 1676 break; 1677 case CVT_95_addMemOperands: 1678 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1679 Operands[*(p + 1)]->setConstraint("m"); 1680 NumMCOperands += 2; 1681 break; 1682 case CVT_95_addConstantSImmOperands_LT_5_44__32_0_GT_: 1683 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1684 Operands[*(p + 1)]->setConstraint("m"); 1685 NumMCOperands += 1; 1686 break; 1687 case CVT_95_addCCRAsmRegOperands: 1688 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1689 Operands[*(p + 1)]->setConstraint("m"); 1690 NumMCOperands += 1; 1691 break; 1692 case CVT_95_addMSACtrlAsmRegOperands: 1693 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1694 Operands[*(p + 1)]->setConstraint("m"); 1695 NumMCOperands += 1; 1696 break; 1697 case CVT_95_addConstantUImmOperands_LT_1_44__32_0_GT_: 1698 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1699 Operands[*(p + 1)]->setConstraint("m"); 1700 NumMCOperands += 1; 1701 break; 1702 case CVT_95_addConstantUImmOperands_LT_5_44__32_33_GT_: 1703 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1704 Operands[*(p + 1)]->setConstraint("m"); 1705 NumMCOperands += 1; 1706 break; 1707 case CVT_95_addConstantUImmOperands_LT_5_44__32_32_GT_: 1708 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1709 Operands[*(p + 1)]->setConstraint("m"); 1710 NumMCOperands += 1; 1711 break; 1712 case CVT_95_addConstantUImmOperands_LT_5_44__32_1_GT_: 1713 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1714 Operands[*(p + 1)]->setConstraint("m"); 1715 NumMCOperands += 1; 1716 break; 1717 case CVT_95_addGPR32NonZeroAsmRegOperands: 1718 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1719 Operands[*(p + 1)]->setConstraint("m"); 1720 NumMCOperands += 1; 1721 break; 1722 case CVT_95_addGPR32ZeroAsmRegOperands: 1723 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1724 Operands[*(p + 1)]->setConstraint("m"); 1725 NumMCOperands += 1; 1726 break; 1727 case CVT_95_addConstantUImmOperands_LT_2_44__32_1_GT_: 1728 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1729 Operands[*(p + 1)]->setConstraint("m"); 1730 NumMCOperands += 1; 1731 break; 1732 case CVT_95_addCOP0AsmRegOperands: 1733 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1734 Operands[*(p + 1)]->setConstraint("m"); 1735 NumMCOperands += 1; 1736 break; 1737 case CVT_regZERO_64: 1738 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1739 Operands[*(p + 1)]->setConstraint("m"); 1740 ++NumMCOperands; 1741 break; 1742 case CVT_95_addACC64DSPAsmRegOperands: 1743 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1744 Operands[*(p + 1)]->setConstraint("m"); 1745 NumMCOperands += 1; 1746 break; 1747 case CVT_95_addConstantUImmOperands_LT_1_GT_: 1748 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1749 Operands[*(p + 1)]->setConstraint("m"); 1750 NumMCOperands += 1; 1751 break; 1752 case CVT_regRA: 1753 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1754 Operands[*(p + 1)]->setConstraint("m"); 1755 ++NumMCOperands; 1756 break; 1757 case CVT_regRA_64: 1758 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1759 Operands[*(p + 1)]->setConstraint("m"); 1760 ++NumMCOperands; 1761 break; 1762 case CVT_95_addMicroMipsMemOperands: 1763 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1764 Operands[*(p + 1)]->setConstraint("m"); 1765 NumMCOperands += 2; 1766 break; 1767 case CVT_95_addCOP3AsmRegOperands: 1768 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1769 Operands[*(p + 1)]->setConstraint("m"); 1770 NumMCOperands += 1; 1771 break; 1772 case CVT_95_addConstantSImmOperands_LT_10_44__32_0_GT_: 1773 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1774 Operands[*(p + 1)]->setConstraint("m"); 1775 NumMCOperands += 1; 1776 break; 1777 case CVT_95_addConstantUImmOperands_LT_32_GT_: 1778 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1779 Operands[*(p + 1)]->setConstraint("m"); 1780 NumMCOperands += 1; 1781 break; 1782 case CVT_95_addStrictlyAFGR64AsmRegOperands: 1783 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1784 Operands[*(p + 1)]->setConstraint("m"); 1785 NumMCOperands += 1; 1786 break; 1787 case CVT_95_addStrictlyFGR64AsmRegOperands: 1788 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1789 Operands[*(p + 1)]->setConstraint("m"); 1790 NumMCOperands += 1; 1791 break; 1792 case CVT_95_addStrictlyFGR32AsmRegOperands: 1793 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1794 Operands[*(p + 1)]->setConstraint("m"); 1795 NumMCOperands += 1; 1796 break; 1797 case CVT_95_addConstantUImmOperands_LT_7_44__32__MINUS_1_GT_: 1798 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1799 Operands[*(p + 1)]->setConstraint("m"); 1800 NumMCOperands += 1; 1801 break; 1802 case CVT_95_addRegListOperands: 1803 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1804 Operands[*(p + 1)]->setConstraint("m"); 1805 NumMCOperands += 1; 1806 break; 1807 case CVT_regAC0: 1808 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1809 Operands[*(p + 1)]->setConstraint("m"); 1810 ++NumMCOperands; 1811 break; 1812 case CVT_95_addMovePRegPairOperands: 1813 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1814 Operands[*(p + 1)]->setConstraint("m"); 1815 NumMCOperands += 2; 1816 break; 1817 case CVT_95_addGPRMM16AsmRegMovePOperands: 1818 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1819 Operands[*(p + 1)]->setConstraint("m"); 1820 NumMCOperands += 1; 1821 break; 1822 case CVT_95_addHI32DSPAsmRegOperands: 1823 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1824 Operands[*(p + 1)]->setConstraint("m"); 1825 NumMCOperands += 1; 1826 break; 1827 case CVT_95_addLO32DSPAsmRegOperands: 1828 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1829 Operands[*(p + 1)]->setConstraint("m"); 1830 NumMCOperands += 1; 1831 break; 1832 case CVT_regS0: 1833 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1834 Operands[*(p + 1)]->setConstraint("m"); 1835 ++NumMCOperands; 1836 break; 1837 case CVT_95_addConstantUImmOperands_LT_7_44__32_0_GT_: 1838 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1839 Operands[*(p + 1)]->setConstraint("m"); 1840 NumMCOperands += 1; 1841 break; 1842 case CVT_95_addHWRegsAsmRegOperands: 1843 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1844 Operands[*(p + 1)]->setConstraint("m"); 1845 NumMCOperands += 1; 1846 break; 1847 case CVT_95_addGPRMM16AsmRegZeroOperands: 1848 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1849 Operands[*(p + 1)]->setConstraint("m"); 1850 NumMCOperands += 1; 1851 break; 1852 case CVT_95_addConstantUImmOperands_LT_20_44__32_0_GT_: 1853 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1854 Operands[*(p + 1)]->setConstraint("m"); 1855 NumMCOperands += 1; 1856 break; 1857 case CVT_95_addConstantSImmOperands_LT_6_44__32_0_GT_: 1858 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1859 Operands[*(p + 1)]->setConstraint("m"); 1860 NumMCOperands += 1; 1861 break; 1862 case CVT_imm_95_2: 1863 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1864 Operands[*(p + 1)]->setConstraint(""); 1865 ++NumMCOperands; 1866 break; 1867 case CVT_imm_95_6: 1868 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1869 Operands[*(p + 1)]->setConstraint(""); 1870 ++NumMCOperands; 1871 break; 1872 case CVT_imm_95_4: 1873 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1874 Operands[*(p + 1)]->setConstraint(""); 1875 ++NumMCOperands; 1876 break; 1877 case CVT_imm_95_5: 1878 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1879 Operands[*(p + 1)]->setConstraint(""); 1880 ++NumMCOperands; 1881 break; 1882 case CVT_imm_95_31: 1883 Operands[*(p + 1)]->setMCOperandNum(NumMCOperands); 1884 Operands[*(p + 1)]->setConstraint(""); 1885 ++NumMCOperands; 1886 break; 1887 } 1888 } 1889} 1890 1891namespace { 1892 1893/// MatchClassKind - The kinds of classes which participate in 1894/// instruction matching. 1895enum MatchClassKind { 1896 InvalidMatchClass = 0, 1897 OptionalMatchClass = 1, 1898 MCK__35_, // '#' 1899 MCK__40_, // '(' 1900 MCK__41_, // ')' 1901 MCK_0, // '0' 1902 MCK_16, // '16' 1903 MCK__91_, // '[' 1904 MCK__93_, // ']' 1905 MCK_bit, // 'bit' 1906 MCK_inst, // 'inst' 1907 MCK_LAST_TOKEN = MCK_inst, 1908 MCK_Reg15, // derived register class 1909 MCK_Reg29, // derived register class 1910 MCK_ACC128, // register class 'ACC128' 1911 MCK_ACC64, // register class 'ACC64' 1912 MCK_CPURAReg, // register class 'CPURAReg,RA' 1913 MCK_CPUSPReg, // register class 'CPUSPReg,SP32,SP' 1914 MCK_DSPCC, // register class 'DSPCC' 1915 MCK_GP32, // register class 'GP32' 1916 MCK_GP64, // register class 'GP64' 1917 MCK_GPR32ZERO, // register class 'GPR32ZERO,ZERO' 1918 MCK_HI32, // register class 'HI32' 1919 MCK_HI64, // register class 'HI64' 1920 MCK_LO32, // register class 'LO32' 1921 MCK_LO64, // register class 'LO64' 1922 MCK_PC, // register class 'PC' 1923 MCK_SP64, // register class 'SP64' 1924 MCK_Reg11, // derived register class 1925 MCK_Reg26, // derived register class 1926 MCK_OCTEON_MPL, // register class 'OCTEON_MPL' 1927 MCK_OCTEON_P, // register class 'OCTEON_P' 1928 MCK_Reg4, // derived register class 1929 MCK_Reg9, // derived register class 1930 MCK_Reg19, // derived register class 1931 MCK_Reg24, // derived register class 1932 MCK_ACC64DSP, // register class 'ACC64DSP' 1933 MCK_HI32DSP, // register class 'HI32DSP' 1934 MCK_LO32DSP, // register class 'LO32DSP' 1935 MCK_Reg8, // derived register class 1936 MCK_Reg10, // derived register class 1937 MCK_Reg23, // derived register class 1938 MCK_Reg25, // derived register class 1939 MCK_Reg17, // derived register class 1940 MCK_Reg18, // derived register class 1941 MCK_Reg21, // derived register class 1942 MCK_Reg36, // derived register class 1943 MCK_CPU16Regs, // register class 'CPU16Regs,GPRMM16' 1944 MCK_FCC, // register class 'FCC' 1945 MCK_GPRMM16MoveP, // register class 'GPRMM16MoveP' 1946 MCK_GPRMM16Zero, // register class 'GPRMM16Zero' 1947 MCK_MSACtrl, // register class 'MSACtrl' 1948 MCK_Reg22, // derived register class 1949 MCK_CPU16RegsPlusSP, // register class 'CPU16RegsPlusSP' 1950 MCK_Reg31, // derived register class 1951 MCK_Reg34, // derived register class 1952 MCK_Reg39, // derived register class 1953 MCK_Reg42, // derived register class 1954 MCK_AFGR64, // register class 'AFGR64' 1955 MCK_MSA128WEvens, // register class 'MSA128WEvens' 1956 MCK_Reg37, // derived register class 1957 MCK_Reg20, // derived register class 1958 MCK_GPR32NONZERO, // register class 'GPR32NONZERO' 1959 MCK_CCR, // register class 'CCR' 1960 MCK_COP0, // register class 'COP0' 1961 MCK_COP2, // register class 'COP2' 1962 MCK_COP3, // register class 'COP3' 1963 MCK_DSPR, // register class 'DSPR,GPR32' 1964 MCK_FGR32, // register class 'FGR32,FGRCC' 1965 MCK_FGR64, // register class 'FGR64' 1966 MCK_FGRH32, // register class 'FGRH32' 1967 MCK_GPR64, // register class 'GPR64' 1968 MCK_HWRegs, // register class 'HWRegs' 1969 MCK_MSA128F16, // register class 'MSA128F16,MSA128B,MSA128D,MSA128H,MSA128W' 1970 MCK_OddSP, // register class 'OddSP' 1971 MCK_LAST_REGISTER = MCK_OddSP, 1972 MCK_ACC64DSPAsmReg, // user defined class 'ACC64DSPAsmOperand' 1973 MCK_AFGR64AsmReg, // user defined class 'AFGR64AsmOperand' 1974 MCK_CCRAsmReg, // user defined class 'CCRAsmOperand' 1975 MCK_COP0AsmReg, // user defined class 'COP0AsmOperand' 1976 MCK_COP2AsmReg, // user defined class 'COP2AsmOperand' 1977 MCK_COP3AsmReg, // user defined class 'COP3AsmOperand' 1978 MCK_FCCAsmReg, // user defined class 'FCCRegsAsmOperand' 1979 MCK_FGR32AsmReg, // user defined class 'FGR32AsmOperand' 1980 MCK_FGR64AsmReg, // user defined class 'FGR64AsmOperand' 1981 MCK_FGRH32AsmReg, // user defined class 'FGRH32AsmOperand' 1982 MCK_GPR32AsmReg, // user defined class 'GPR32AsmOperand' 1983 MCK_GPR32NonZeroAsmReg, // user defined class 'GPR32NonZeroAsmOperand' 1984 MCK_GPR32ZeroAsmReg, // user defined class 'GPR32ZeroAsmOperand' 1985 MCK_GPR64AsmReg, // user defined class 'GPR64AsmOperand' 1986 MCK_GPRMM16AsmReg, // user defined class 'GPRMM16AsmOperand' 1987 MCK_GPRMM16AsmRegMoveP, // user defined class 'GPRMM16AsmOperandMoveP' 1988 MCK_GPRMM16AsmRegZero, // user defined class 'GPRMM16AsmOperandZero' 1989 MCK_HI32DSPAsmReg, // user defined class 'HI32DSPAsmOperand' 1990 MCK_HWRegsAsmReg, // user defined class 'HWRegsAsmOperand' 1991 MCK_Imm, // user defined class 'ImmAsmOperand' 1992 MCK_LO32DSPAsmReg, // user defined class 'LO32DSPAsmOperand' 1993 MCK_MSA128AsmReg, // user defined class 'MSA128AsmOperand' 1994 MCK_MSACtrlAsmReg, // user defined class 'MSACtrlAsmOperand' 1995 MCK_MicroMipsMemGP, // user defined class 'MicroMipsMemGPAsmOperand' 1996 MCK_MicroMipsMem, // user defined class 'MicroMipsMemGPRMM16AsmOperand' 1997 MCK_MicroMipsMemSP, // user defined class 'MicroMipsMemSPAsmOperand' 1998 MCK_InvNum, // user defined class 'MipsInvertedImmoperand' 1999 MCK_JumpTarget, // user defined class 'MipsJumpTargetAsmOperand' 2000 MCK_MemOffsetSimm10, // user defined class 'MipsMemSimm10AsmOperand' 2001 MCK_MemOffsetSimm10_1, // user defined class 'MipsMemSimm10Lsl1AsmOperand' 2002 MCK_MemOffsetSimm10_2, // user defined class 'MipsMemSimm10Lsl2AsmOperand' 2003 MCK_MemOffsetSimm10_3, // user defined class 'MipsMemSimm10Lsl3AsmOperand' 2004 MCK_MemOffsetSimm11, // user defined class 'MipsMemSimm11AsmOperand' 2005 MCK_MemOffsetSimm12, // user defined class 'MipsMemSimm12AsmOperand' 2006 MCK_MemOffsetSimm16, // user defined class 'MipsMemSimm16AsmOperand' 2007 MCK_MemOffsetSimm9, // user defined class 'MipsMemSimm9AsmOperand' 2008 MCK_MemOffsetSimmPtr, // user defined class 'MipsMemSimmPtrAsmOperand' 2009 MCK_MemOffsetUimm4, // user defined class 'MipsMemUimm4AsmOperand' 2010 MCK_Mem, // user defined class 'MipsMemAsmOperand' 2011 MCK_MovePRegPair, // user defined class 'MovePRegPairAsmOperand' 2012 MCK_RegList16, // user defined class 'RegList16AsmOperand' 2013 MCK_RegList, // user defined class 'RegListAsmOperand' 2014 MCK_Simm19_Lsl2, // user defined class 'Simm19Lsl2AsmOperand' 2015 MCK_StrictlyAFGR64AsmReg, // user defined class 'StrictlyAFGR64AsmOperand' 2016 MCK_StrictlyFGR32AsmReg, // user defined class 'StrictlyFGR32AsmOperand' 2017 MCK_StrictlyFGR64AsmReg, // user defined class 'StrictlyFGR64AsmOperand' 2018 MCK_ConstantImmz, // user defined class 'ConstantImmzAsmOperandClass' 2019 MCK_ConstantUImm1_0, // user defined class 'ConstantUImm1AsmOperandClass' 2020 MCK_ConstantUImm2_0, // user defined class 'ConstantUImm2AsmOperandClass' 2021 MCK_ConstantUImm2_1, // user defined class 'ConstantUImm2Plus1AsmOperandClass' 2022 MCK_ConstantUImm3_0, // user defined class 'ConstantUImm3AsmOperandClass' 2023 MCK_ConstantSImm4_0, // user defined class 'ConstantSImm4AsmOperandClass' 2024 MCK_ConstantUImm4_0, // user defined class 'ConstantUImm4AsmOperandClass' 2025 MCK_ConstantSImm5_0, // user defined class 'ConstantSImm5AsmOperandClass' 2026 MCK_ConstantUImm5_0, // user defined class 'ConstantUImm5AsmOperandClass' 2027 MCK_ConstantUImm5_1, // user defined class 'ConstantUImm5Plus1AsmOperandClass' 2028 MCK_ConstantUImm5_Plus1_Report_UImm6, // user defined class 'ConstantUImm5Plus1ReportUImm6AsmOperandClass' 2029 MCK_ConstantUImm5_32_Norm, // user defined class 'ConstantUImm5Plus32NormalizeAsmOperandClass' 2030 MCK_ConstantUImm5_32, // user defined class 'ConstantUImm5Plus32AsmOperandClass' 2031 MCK_ConstantUImm5_0_Report_UImm6, // user defined class 'ConstantUImm5ReportUImm6AsmOperandClass' 2032 MCK_ConstantUImm5_33, // user defined class 'ConstantUImm5Plus33AsmOperandClass' 2033 MCK_ConstantUImmRange2_64, // user defined class 'ConstantUImm5_Range2_64AsmOperandClass' 2034 MCK_UImm5Lsl2, // user defined class 'ConstantUImm5Lsl2AsmOperandClass' 2035 MCK_ConstantSImm6_0, // user defined class 'ConstantSImm6AsmOperandClass' 2036 MCK_ConstantUImm6_0, // user defined class 'ConstantUImm6AsmOperandClass' 2037 MCK_UImm6Lsl2, // user defined class 'ConstantUImm6Lsl2AsmOperandClass' 2038 MCK_ConstantUImm7_0, // user defined class 'ConstantUImm7AsmOperandClass' 2039 MCK_UImm7_N1, // user defined class 'ConstantUImm7Sub1AsmOperandClass' 2040 MCK_ConstantUImm8_0, // user defined class 'ConstantUImm8AsmOperandClass' 2041 MCK_SImm7Lsl2, // user defined class 'ConstantSImm7Lsl2AsmOperandClass' 2042 MCK_ConstantSImm9_0, // user defined class 'ConstantSImm9AsmOperandClass' 2043 MCK_ConstantSImm10_0, // user defined class 'ConstantSImm10AsmOperandClass' 2044 MCK_ConstantUImm10_0, // user defined class 'ConstantUImm10AsmOperandClass' 2045 MCK_SImm10Lsl1, // user defined class 'ConstantSImm10Lsl1AsmOperandClass' 2046 MCK_ConstantSImm11_0, // user defined class 'ConstantSImm11AsmOperandClass' 2047 MCK_SImm10Lsl2, // user defined class 'ConstantSImm10Lsl2AsmOperandClass' 2048 MCK_SImm10Lsl3, // user defined class 'ConstantSImm10Lsl3AsmOperandClass' 2049 MCK_SImm16, // user defined class 'SImm16AsmOperandClass' 2050 MCK_SImm16_Relaxed, // user defined class 'SImm16RelaxedAsmOperandClass' 2051 MCK_UImm16_AltRelaxed, // user defined class 'UImm16AltRelaxedAsmOperandClass' 2052 MCK_UImm16, // user defined class 'UImm16AsmOperandClass' 2053 MCK_SImm19Lsl2, // user defined class 'ConstantSImm19Lsl2AsmOperandClass' 2054 MCK_UImm16_Relaxed, // user defined class 'UImm16RelaxedAsmOperandClass' 2055 MCK_ConstantUImm20_0, // user defined class 'ConstantUImm20AsmOperandClass' 2056 MCK_ConstantUImm26_0, // user defined class 'ConstantUImm26AsmOperandClass' 2057 MCK_SImm32, // user defined class 'SImm32AsmOperandClass' 2058 MCK_SImm32_Relaxed, // user defined class 'SImm32RelaxedAsmOperandClass' 2059 MCK_UImm32_Coerced, // user defined class 'UImm32CoercedAsmOperandClass' 2060 NumMatchClassKinds 2061}; 2062 2063} 2064 2065static unsigned getDiagKindFromRegisterClass(MatchClassKind RegisterClass) { 2066 return MCTargetAsmParser::Match_InvalidOperand; 2067} 2068 2069static MatchClassKind matchTokenString(StringRef Name) { 2070 switch (Name.size()) { 2071 default: break; 2072 case 1: // 6 strings to match. 2073 switch (Name[0]) { 2074 default: break; 2075 case '#': // 1 string to match. 2076 return MCK__35_; // "#" 2077 case '(': // 1 string to match. 2078 return MCK__40_; // "(" 2079 case ')': // 1 string to match. 2080 return MCK__41_; // ")" 2081 case '0': // 1 string to match. 2082 return MCK_0; // "0" 2083 case '[': // 1 string to match. 2084 return MCK__91_; // "[" 2085 case ']': // 1 string to match. 2086 return MCK__93_; // "]" 2087 } 2088 break; 2089 case 2: // 1 string to match. 2090 if (memcmp(Name.data()+0, "16", 2) != 0) 2091 break; 2092 return MCK_16; // "16" 2093 case 3: // 1 string to match. 2094 if (memcmp(Name.data()+0, "bit", 3) != 0) 2095 break; 2096 return MCK_bit; // "bit" 2097 case 4: // 1 string to match. 2098 if (memcmp(Name.data()+0, "inst", 4) != 0) 2099 break; 2100 return MCK_inst; // "inst" 2101 } 2102 return InvalidMatchClass; 2103} 2104 2105/// isSubclass - Compute whether \p A is a subclass of \p B. 2106static bool isSubclass(MatchClassKind A, MatchClassKind B) { 2107 if (A == B) 2108 return true; 2109 2110 switch (A) { 2111 default: 2112 return false; 2113 2114 case MCK_Reg15: 2115 switch (B) { 2116 default: return false; 2117 case MCK_Reg19: return true; 2118 case MCK_Reg17: return true; 2119 case MCK_Reg18: return true; 2120 case MCK_GPR64: return true; 2121 } 2122 2123 case MCK_Reg29: 2124 switch (B) { 2125 default: return false; 2126 case MCK_Reg20: return true; 2127 case MCK_GPR64: return true; 2128 } 2129 2130 case MCK_ACC64: 2131 return B == MCK_ACC64DSP; 2132 2133 case MCK_CPURAReg: 2134 switch (B) { 2135 default: return false; 2136 case MCK_GPR32NONZERO: return true; 2137 case MCK_DSPR: return true; 2138 } 2139 2140 case MCK_CPUSPReg: 2141 switch (B) { 2142 default: return false; 2143 case MCK_CPU16RegsPlusSP: return true; 2144 case MCK_GPR32NONZERO: return true; 2145 case MCK_DSPR: return true; 2146 } 2147 2148 case MCK_GP32: 2149 switch (B) { 2150 default: return false; 2151 case MCK_GPR32NONZERO: return true; 2152 case MCK_DSPR: return true; 2153 } 2154 2155 case MCK_GP64: 2156 switch (B) { 2157 default: return false; 2158 case MCK_Reg20: return true; 2159 case MCK_GPR64: return true; 2160 } 2161 2162 case MCK_GPR32ZERO: 2163 switch (B) { 2164 default: return false; 2165 case MCK_Reg4: return true; 2166 case MCK_GPRMM16MoveP: return true; 2167 case MCK_GPRMM16Zero: return true; 2168 case MCK_DSPR: return true; 2169 } 2170 2171 case MCK_HI32: 2172 return B == MCK_HI32DSP; 2173 2174 case MCK_LO32: 2175 return B == MCK_LO32DSP; 2176 2177 case MCK_SP64: 2178 switch (B) { 2179 default: return false; 2180 case MCK_Reg22: return true; 2181 case MCK_Reg20: return true; 2182 case MCK_GPR64: return true; 2183 } 2184 2185 case MCK_Reg11: 2186 switch (B) { 2187 default: return false; 2188 case MCK_Reg4: return true; 2189 case MCK_Reg9: return true; 2190 case MCK_Reg8: return true; 2191 case MCK_Reg10: return true; 2192 case MCK_CPU16Regs: return true; 2193 case MCK_GPRMM16MoveP: return true; 2194 case MCK_GPRMM16Zero: return true; 2195 case MCK_CPU16RegsPlusSP: return true; 2196 case MCK_GPR32NONZERO: return true; 2197 case MCK_DSPR: return true; 2198 } 2199 2200 case MCK_Reg26: 2201 switch (B) { 2202 default: return false; 2203 case MCK_Reg19: return true; 2204 case MCK_Reg24: return true; 2205 case MCK_Reg23: return true; 2206 case MCK_Reg25: return true; 2207 case MCK_Reg17: return true; 2208 case MCK_Reg18: return true; 2209 case MCK_Reg21: return true; 2210 case MCK_Reg22: return true; 2211 case MCK_Reg20: return true; 2212 case MCK_GPR64: return true; 2213 } 2214 2215 case MCK_Reg4: 2216 switch (B) { 2217 default: return false; 2218 case MCK_GPRMM16MoveP: return true; 2219 case MCK_GPRMM16Zero: return true; 2220 case MCK_DSPR: return true; 2221 } 2222 2223 case MCK_Reg9: 2224 switch (B) { 2225 default: return false; 2226 case MCK_Reg10: return true; 2227 case MCK_CPU16Regs: return true; 2228 case MCK_GPRMM16MoveP: return true; 2229 case MCK_CPU16RegsPlusSP: return true; 2230 case MCK_GPR32NONZERO: return true; 2231 case MCK_DSPR: return true; 2232 } 2233 2234 case MCK_Reg19: 2235 switch (B) { 2236 default: return false; 2237 case MCK_Reg17: return true; 2238 case MCK_Reg18: return true; 2239 case MCK_GPR64: return true; 2240 } 2241 2242 case MCK_Reg24: 2243 switch (B) { 2244 default: return false; 2245 case MCK_Reg25: return true; 2246 case MCK_Reg18: return true; 2247 case MCK_Reg21: return true; 2248 case MCK_Reg22: return true; 2249 case MCK_Reg20: return true; 2250 case MCK_GPR64: return true; 2251 } 2252 2253 case MCK_Reg8: 2254 switch (B) { 2255 default: return false; 2256 case MCK_CPU16Regs: return true; 2257 case MCK_GPRMM16Zero: return true; 2258 case MCK_CPU16RegsPlusSP: return true; 2259 case MCK_GPR32NONZERO: return true; 2260 case MCK_DSPR: return true; 2261 } 2262 2263 case MCK_Reg10: 2264 switch (B) { 2265 default: return false; 2266 case MCK_GPRMM16MoveP: return true; 2267 case MCK_GPR32NONZERO: return true; 2268 case MCK_DSPR: return true; 2269 } 2270 2271 case MCK_Reg23: 2272 switch (B) { 2273 default: return false; 2274 case MCK_Reg17: return true; 2275 case MCK_Reg21: return true; 2276 case MCK_Reg22: return true; 2277 case MCK_Reg20: return true; 2278 case MCK_GPR64: return true; 2279 } 2280 2281 case MCK_Reg25: 2282 switch (B) { 2283 default: return false; 2284 case MCK_Reg18: return true; 2285 case MCK_Reg20: return true; 2286 case MCK_GPR64: return true; 2287 } 2288 2289 case MCK_Reg17: 2290 return B == MCK_GPR64; 2291 2292 case MCK_Reg18: 2293 return B == MCK_GPR64; 2294 2295 case MCK_Reg21: 2296 switch (B) { 2297 default: return false; 2298 case MCK_Reg22: return true; 2299 case MCK_Reg20: return true; 2300 case MCK_GPR64: return true; 2301 } 2302 2303 case MCK_Reg36: 2304 switch (B) { 2305 default: return false; 2306 case MCK_AFGR64: return true; 2307 case MCK_Reg37: return true; 2308 case MCK_OddSP: return true; 2309 } 2310 2311 case MCK_CPU16Regs: 2312 switch (B) { 2313 default: return false; 2314 case MCK_CPU16RegsPlusSP: return true; 2315 case MCK_GPR32NONZERO: return true; 2316 case MCK_DSPR: return true; 2317 } 2318 2319 case MCK_GPRMM16MoveP: 2320 return B == MCK_DSPR; 2321 2322 case MCK_GPRMM16Zero: 2323 return B == MCK_DSPR; 2324 2325 case MCK_Reg22: 2326 switch (B) { 2327 default: return false; 2328 case MCK_Reg20: return true; 2329 case MCK_GPR64: return true; 2330 } 2331 2332 case MCK_CPU16RegsPlusSP: 2333 switch (B) { 2334 default: return false; 2335 case MCK_GPR32NONZERO: return true; 2336 case MCK_DSPR: return true; 2337 } 2338 2339 case MCK_Reg31: 2340 switch (B) { 2341 default: return false; 2342 case MCK_FGR32: return true; 2343 case MCK_OddSP: return true; 2344 } 2345 2346 case MCK_Reg34: 2347 switch (B) { 2348 default: return false; 2349 case MCK_FGRH32: return true; 2350 case MCK_OddSP: return true; 2351 } 2352 2353 case MCK_Reg39: 2354 switch (B) { 2355 default: return false; 2356 case MCK_Reg37: return true; 2357 case MCK_FGR64: return true; 2358 case MCK_OddSP: return true; 2359 } 2360 2361 case MCK_Reg42: 2362 return B == MCK_MSA128F16; 2363 2364 case MCK_MSA128WEvens: 2365 return B == MCK_MSA128F16; 2366 2367 case MCK_Reg37: 2368 return B == MCK_OddSP; 2369 2370 case MCK_Reg20: 2371 return B == MCK_GPR64; 2372 2373 case MCK_GPR32NONZERO: 2374 return B == MCK_DSPR; 2375 2376 case MCK_MemOffsetSimm10: 2377 return B == MCK_Mem; 2378 2379 case MCK_MemOffsetSimm10_1: 2380 return B == MCK_Mem; 2381 2382 case MCK_MemOffsetSimm10_2: 2383 return B == MCK_Mem; 2384 2385 case MCK_MemOffsetSimm10_3: 2386 return B == MCK_Mem; 2387 2388 case MCK_MemOffsetSimm11: 2389 return B == MCK_Mem; 2390 2391 case MCK_MemOffsetSimm12: 2392 return B == MCK_Mem; 2393 2394 case MCK_MemOffsetSimm16: 2395 return B == MCK_Mem; 2396 2397 case MCK_MemOffsetSimm9: 2398 return B == MCK_Mem; 2399 2400 case MCK_MemOffsetSimmPtr: 2401 return B == MCK_Mem; 2402 2403 case MCK_MemOffsetUimm4: 2404 return B == MCK_Mem; 2405 2406 case MCK_ConstantImmz: 2407 switch (B) { 2408 default: return false; 2409 case MCK_ConstantUImm1_0: return true; 2410 case MCK_ConstantUImm2_0: return true; 2411 case MCK_ConstantUImm3_0: return true; 2412 case MCK_ConstantSImm4_0: return true; 2413 case MCK_ConstantUImm4_0: return true; 2414 case MCK_ConstantSImm5_0: return true; 2415 case MCK_ConstantUImm5_0: return true; 2416 case MCK_ConstantUImm5_1: return true; 2417 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2418 case MCK_ConstantUImm5_32_Norm: return true; 2419 case MCK_ConstantUImm5_32: return true; 2420 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2421 case MCK_ConstantUImm5_33: return true; 2422 case MCK_ConstantUImmRange2_64: return true; 2423 case MCK_UImm5Lsl2: return true; 2424 case MCK_ConstantSImm6_0: return true; 2425 case MCK_ConstantUImm6_0: return true; 2426 case MCK_UImm6Lsl2: return true; 2427 case MCK_ConstantUImm7_0: return true; 2428 case MCK_UImm7_N1: return true; 2429 case MCK_ConstantUImm8_0: return true; 2430 case MCK_SImm7Lsl2: return true; 2431 case MCK_ConstantSImm9_0: return true; 2432 case MCK_ConstantSImm10_0: return true; 2433 case MCK_ConstantUImm10_0: return true; 2434 case MCK_SImm10Lsl1: return true; 2435 case MCK_ConstantSImm11_0: return true; 2436 case MCK_SImm10Lsl2: return true; 2437 case MCK_SImm10Lsl3: return true; 2438 case MCK_SImm16: return true; 2439 case MCK_SImm16_Relaxed: return true; 2440 case MCK_UImm16_Relaxed: return true; 2441 case MCK_ConstantUImm20_0: return true; 2442 case MCK_ConstantUImm26_0: return true; 2443 case MCK_SImm32: return true; 2444 case MCK_SImm32_Relaxed: return true; 2445 case MCK_UImm32_Coerced: return true; 2446 } 2447 2448 case MCK_ConstantUImm1_0: 2449 switch (B) { 2450 default: return false; 2451 case MCK_ConstantUImm2_0: return true; 2452 case MCK_ConstantUImm3_0: return true; 2453 case MCK_ConstantSImm4_0: return true; 2454 case MCK_ConstantUImm4_0: return true; 2455 case MCK_ConstantSImm5_0: return true; 2456 case MCK_ConstantUImm5_0: return true; 2457 case MCK_ConstantUImm5_1: return true; 2458 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2459 case MCK_ConstantUImm5_32_Norm: return true; 2460 case MCK_ConstantUImm5_32: return true; 2461 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2462 case MCK_ConstantUImm5_33: return true; 2463 case MCK_ConstantUImmRange2_64: return true; 2464 case MCK_UImm5Lsl2: return true; 2465 case MCK_ConstantSImm6_0: return true; 2466 case MCK_ConstantUImm6_0: return true; 2467 case MCK_UImm6Lsl2: return true; 2468 case MCK_ConstantUImm7_0: return true; 2469 case MCK_UImm7_N1: return true; 2470 case MCK_ConstantUImm8_0: return true; 2471 case MCK_SImm7Lsl2: return true; 2472 case MCK_ConstantSImm9_0: return true; 2473 case MCK_ConstantSImm10_0: return true; 2474 case MCK_ConstantUImm10_0: return true; 2475 case MCK_SImm10Lsl1: return true; 2476 case MCK_ConstantSImm11_0: return true; 2477 case MCK_SImm10Lsl2: return true; 2478 case MCK_SImm10Lsl3: return true; 2479 case MCK_SImm16: return true; 2480 case MCK_SImm16_Relaxed: return true; 2481 case MCK_UImm16_Relaxed: return true; 2482 case MCK_ConstantUImm20_0: return true; 2483 case MCK_ConstantUImm26_0: return true; 2484 case MCK_SImm32: return true; 2485 case MCK_SImm32_Relaxed: return true; 2486 case MCK_UImm32_Coerced: return true; 2487 } 2488 2489 case MCK_ConstantUImm2_0: 2490 switch (B) { 2491 default: return false; 2492 case MCK_ConstantUImm3_0: return true; 2493 case MCK_ConstantSImm4_0: return true; 2494 case MCK_ConstantUImm4_0: return true; 2495 case MCK_ConstantSImm5_0: return true; 2496 case MCK_ConstantUImm5_0: return true; 2497 case MCK_ConstantUImm5_1: return true; 2498 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2499 case MCK_ConstantUImm5_32_Norm: return true; 2500 case MCK_ConstantUImm5_32: return true; 2501 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2502 case MCK_ConstantUImm5_33: return true; 2503 case MCK_ConstantUImmRange2_64: return true; 2504 case MCK_UImm5Lsl2: return true; 2505 case MCK_ConstantSImm6_0: return true; 2506 case MCK_ConstantUImm6_0: return true; 2507 case MCK_UImm6Lsl2: return true; 2508 case MCK_ConstantUImm7_0: return true; 2509 case MCK_UImm7_N1: return true; 2510 case MCK_ConstantUImm8_0: return true; 2511 case MCK_SImm7Lsl2: return true; 2512 case MCK_ConstantSImm9_0: return true; 2513 case MCK_ConstantSImm10_0: return true; 2514 case MCK_ConstantUImm10_0: return true; 2515 case MCK_SImm10Lsl1: return true; 2516 case MCK_ConstantSImm11_0: return true; 2517 case MCK_SImm10Lsl2: return true; 2518 case MCK_SImm10Lsl3: return true; 2519 case MCK_SImm16: return true; 2520 case MCK_SImm16_Relaxed: return true; 2521 case MCK_UImm16_Relaxed: return true; 2522 case MCK_ConstantUImm20_0: return true; 2523 case MCK_ConstantUImm26_0: return true; 2524 case MCK_SImm32: return true; 2525 case MCK_SImm32_Relaxed: return true; 2526 case MCK_UImm32_Coerced: return true; 2527 } 2528 2529 case MCK_ConstantUImm2_1: 2530 switch (B) { 2531 default: return false; 2532 case MCK_ConstantUImm3_0: return true; 2533 case MCK_ConstantSImm4_0: return true; 2534 case MCK_ConstantUImm4_0: return true; 2535 case MCK_ConstantSImm5_0: return true; 2536 case MCK_ConstantUImm5_0: return true; 2537 case MCK_ConstantUImm5_1: return true; 2538 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2539 case MCK_ConstantUImm5_32_Norm: return true; 2540 case MCK_ConstantUImm5_32: return true; 2541 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2542 case MCK_ConstantUImm5_33: return true; 2543 case MCK_ConstantUImmRange2_64: return true; 2544 case MCK_UImm5Lsl2: return true; 2545 case MCK_ConstantSImm6_0: return true; 2546 case MCK_ConstantUImm6_0: return true; 2547 case MCK_UImm6Lsl2: return true; 2548 case MCK_ConstantUImm7_0: return true; 2549 case MCK_UImm7_N1: return true; 2550 case MCK_ConstantUImm8_0: return true; 2551 case MCK_SImm7Lsl2: return true; 2552 case MCK_ConstantSImm9_0: return true; 2553 case MCK_ConstantSImm10_0: return true; 2554 case MCK_ConstantUImm10_0: return true; 2555 case MCK_SImm10Lsl1: return true; 2556 case MCK_ConstantSImm11_0: return true; 2557 case MCK_SImm10Lsl2: return true; 2558 case MCK_SImm10Lsl3: return true; 2559 case MCK_SImm16: return true; 2560 case MCK_SImm16_Relaxed: return true; 2561 case MCK_UImm16_Relaxed: return true; 2562 case MCK_ConstantUImm20_0: return true; 2563 case MCK_ConstantUImm26_0: return true; 2564 case MCK_SImm32: return true; 2565 case MCK_SImm32_Relaxed: return true; 2566 case MCK_UImm32_Coerced: return true; 2567 } 2568 2569 case MCK_ConstantUImm3_0: 2570 switch (B) { 2571 default: return false; 2572 case MCK_ConstantSImm4_0: return true; 2573 case MCK_ConstantUImm4_0: return true; 2574 case MCK_ConstantSImm5_0: return true; 2575 case MCK_ConstantUImm5_0: return true; 2576 case MCK_ConstantUImm5_1: return true; 2577 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2578 case MCK_ConstantUImm5_32_Norm: return true; 2579 case MCK_ConstantUImm5_32: return true; 2580 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2581 case MCK_ConstantUImm5_33: return true; 2582 case MCK_ConstantUImmRange2_64: return true; 2583 case MCK_UImm5Lsl2: return true; 2584 case MCK_ConstantSImm6_0: return true; 2585 case MCK_ConstantUImm6_0: return true; 2586 case MCK_UImm6Lsl2: return true; 2587 case MCK_ConstantUImm7_0: return true; 2588 case MCK_UImm7_N1: return true; 2589 case MCK_ConstantUImm8_0: return true; 2590 case MCK_SImm7Lsl2: return true; 2591 case MCK_ConstantSImm9_0: return true; 2592 case MCK_ConstantSImm10_0: return true; 2593 case MCK_ConstantUImm10_0: return true; 2594 case MCK_SImm10Lsl1: return true; 2595 case MCK_ConstantSImm11_0: return true; 2596 case MCK_SImm10Lsl2: return true; 2597 case MCK_SImm10Lsl3: return true; 2598 case MCK_SImm16: return true; 2599 case MCK_SImm16_Relaxed: return true; 2600 case MCK_UImm16_Relaxed: return true; 2601 case MCK_ConstantUImm20_0: return true; 2602 case MCK_ConstantUImm26_0: return true; 2603 case MCK_SImm32: return true; 2604 case MCK_SImm32_Relaxed: return true; 2605 case MCK_UImm32_Coerced: return true; 2606 } 2607 2608 case MCK_ConstantSImm4_0: 2609 switch (B) { 2610 default: return false; 2611 case MCK_ConstantUImm4_0: return true; 2612 case MCK_ConstantSImm5_0: return true; 2613 case MCK_ConstantUImm5_0: return true; 2614 case MCK_ConstantUImm5_1: return true; 2615 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2616 case MCK_ConstantUImm5_32_Norm: return true; 2617 case MCK_ConstantUImm5_32: return true; 2618 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2619 case MCK_ConstantUImm5_33: return true; 2620 case MCK_ConstantUImmRange2_64: return true; 2621 case MCK_UImm5Lsl2: return true; 2622 case MCK_ConstantSImm6_0: return true; 2623 case MCK_ConstantUImm6_0: return true; 2624 case MCK_UImm6Lsl2: return true; 2625 case MCK_ConstantUImm7_0: return true; 2626 case MCK_UImm7_N1: return true; 2627 case MCK_ConstantUImm8_0: return true; 2628 case MCK_SImm7Lsl2: return true; 2629 case MCK_ConstantSImm9_0: return true; 2630 case MCK_ConstantSImm10_0: return true; 2631 case MCK_ConstantUImm10_0: return true; 2632 case MCK_SImm10Lsl1: return true; 2633 case MCK_ConstantSImm11_0: return true; 2634 case MCK_SImm10Lsl2: return true; 2635 case MCK_SImm10Lsl3: return true; 2636 case MCK_SImm16: return true; 2637 case MCK_SImm16_Relaxed: return true; 2638 case MCK_UImm16_Relaxed: return true; 2639 case MCK_ConstantUImm20_0: return true; 2640 case MCK_ConstantUImm26_0: return true; 2641 case MCK_SImm32: return true; 2642 case MCK_SImm32_Relaxed: return true; 2643 case MCK_UImm32_Coerced: return true; 2644 } 2645 2646 case MCK_ConstantUImm4_0: 2647 switch (B) { 2648 default: return false; 2649 case MCK_ConstantSImm5_0: return true; 2650 case MCK_ConstantUImm5_0: return true; 2651 case MCK_ConstantUImm5_1: return true; 2652 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2653 case MCK_ConstantUImm5_32_Norm: return true; 2654 case MCK_ConstantUImm5_32: return true; 2655 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2656 case MCK_ConstantUImm5_33: return true; 2657 case MCK_ConstantUImmRange2_64: return true; 2658 case MCK_UImm5Lsl2: return true; 2659 case MCK_ConstantSImm6_0: return true; 2660 case MCK_ConstantUImm6_0: return true; 2661 case MCK_UImm6Lsl2: return true; 2662 case MCK_ConstantUImm7_0: return true; 2663 case MCK_UImm7_N1: return true; 2664 case MCK_ConstantUImm8_0: return true; 2665 case MCK_SImm7Lsl2: return true; 2666 case MCK_ConstantSImm9_0: return true; 2667 case MCK_ConstantSImm10_0: return true; 2668 case MCK_ConstantUImm10_0: return true; 2669 case MCK_SImm10Lsl1: return true; 2670 case MCK_ConstantSImm11_0: return true; 2671 case MCK_SImm10Lsl2: return true; 2672 case MCK_SImm10Lsl3: return true; 2673 case MCK_SImm16: return true; 2674 case MCK_SImm16_Relaxed: return true; 2675 case MCK_UImm16_Relaxed: return true; 2676 case MCK_ConstantUImm20_0: return true; 2677 case MCK_ConstantUImm26_0: return true; 2678 case MCK_SImm32: return true; 2679 case MCK_SImm32_Relaxed: return true; 2680 case MCK_UImm32_Coerced: return true; 2681 } 2682 2683 case MCK_ConstantSImm5_0: 2684 switch (B) { 2685 default: return false; 2686 case MCK_ConstantUImm5_0: return true; 2687 case MCK_ConstantUImm5_1: return true; 2688 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2689 case MCK_ConstantUImm5_32_Norm: return true; 2690 case MCK_ConstantUImm5_32: return true; 2691 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2692 case MCK_ConstantUImm5_33: return true; 2693 case MCK_ConstantUImmRange2_64: return true; 2694 case MCK_UImm5Lsl2: return true; 2695 case MCK_ConstantSImm6_0: return true; 2696 case MCK_ConstantUImm6_0: return true; 2697 case MCK_UImm6Lsl2: return true; 2698 case MCK_ConstantUImm7_0: return true; 2699 case MCK_UImm7_N1: return true; 2700 case MCK_ConstantUImm8_0: return true; 2701 case MCK_SImm7Lsl2: return true; 2702 case MCK_ConstantSImm9_0: return true; 2703 case MCK_ConstantSImm10_0: return true; 2704 case MCK_ConstantUImm10_0: return true; 2705 case MCK_SImm10Lsl1: return true; 2706 case MCK_ConstantSImm11_0: return true; 2707 case MCK_SImm10Lsl2: return true; 2708 case MCK_SImm10Lsl3: return true; 2709 case MCK_SImm16: return true; 2710 case MCK_SImm16_Relaxed: return true; 2711 case MCK_UImm16_Relaxed: return true; 2712 case MCK_ConstantUImm20_0: return true; 2713 case MCK_ConstantUImm26_0: return true; 2714 case MCK_SImm32: return true; 2715 case MCK_SImm32_Relaxed: return true; 2716 case MCK_UImm32_Coerced: return true; 2717 } 2718 2719 case MCK_ConstantUImm5_0: 2720 switch (B) { 2721 default: return false; 2722 case MCK_ConstantUImm5_1: return true; 2723 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2724 case MCK_ConstantUImm5_32_Norm: return true; 2725 case MCK_ConstantUImm5_32: return true; 2726 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2727 case MCK_ConstantUImm5_33: return true; 2728 case MCK_ConstantUImmRange2_64: return true; 2729 case MCK_UImm5Lsl2: return true; 2730 case MCK_ConstantSImm6_0: return true; 2731 case MCK_ConstantUImm6_0: return true; 2732 case MCK_UImm6Lsl2: return true; 2733 case MCK_ConstantUImm7_0: return true; 2734 case MCK_UImm7_N1: return true; 2735 case MCK_ConstantUImm8_0: return true; 2736 case MCK_SImm7Lsl2: return true; 2737 case MCK_ConstantSImm9_0: return true; 2738 case MCK_ConstantSImm10_0: return true; 2739 case MCK_ConstantUImm10_0: return true; 2740 case MCK_SImm10Lsl1: return true; 2741 case MCK_ConstantSImm11_0: return true; 2742 case MCK_SImm10Lsl2: return true; 2743 case MCK_SImm10Lsl3: return true; 2744 case MCK_SImm16: return true; 2745 case MCK_SImm16_Relaxed: return true; 2746 case MCK_UImm16_Relaxed: return true; 2747 case MCK_ConstantUImm20_0: return true; 2748 case MCK_ConstantUImm26_0: return true; 2749 case MCK_SImm32: return true; 2750 case MCK_SImm32_Relaxed: return true; 2751 case MCK_UImm32_Coerced: return true; 2752 } 2753 2754 case MCK_ConstantUImm5_1: 2755 switch (B) { 2756 default: return false; 2757 case MCK_ConstantUImm5_Plus1_Report_UImm6: return true; 2758 case MCK_ConstantUImm5_32_Norm: return true; 2759 case MCK_ConstantUImm5_32: return true; 2760 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2761 case MCK_ConstantUImm5_33: return true; 2762 case MCK_ConstantUImmRange2_64: return true; 2763 case MCK_UImm5Lsl2: return true; 2764 case MCK_ConstantSImm6_0: return true; 2765 case MCK_ConstantUImm6_0: return true; 2766 case MCK_UImm6Lsl2: return true; 2767 case MCK_ConstantUImm7_0: return true; 2768 case MCK_UImm7_N1: return true; 2769 case MCK_ConstantUImm8_0: return true; 2770 case MCK_SImm7Lsl2: return true; 2771 case MCK_ConstantSImm9_0: return true; 2772 case MCK_ConstantSImm10_0: return true; 2773 case MCK_ConstantUImm10_0: return true; 2774 case MCK_SImm10Lsl1: return true; 2775 case MCK_ConstantSImm11_0: return true; 2776 case MCK_SImm10Lsl2: return true; 2777 case MCK_SImm10Lsl3: return true; 2778 case MCK_SImm16: return true; 2779 case MCK_SImm16_Relaxed: return true; 2780 case MCK_UImm16_Relaxed: return true; 2781 case MCK_ConstantUImm20_0: return true; 2782 case MCK_ConstantUImm26_0: return true; 2783 case MCK_SImm32: return true; 2784 case MCK_SImm32_Relaxed: return true; 2785 case MCK_UImm32_Coerced: return true; 2786 } 2787 2788 case MCK_ConstantUImm5_Plus1_Report_UImm6: 2789 switch (B) { 2790 default: return false; 2791 case MCK_ConstantUImm5_32_Norm: return true; 2792 case MCK_ConstantUImm5_32: return true; 2793 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2794 case MCK_ConstantUImm5_33: return true; 2795 case MCK_ConstantUImmRange2_64: return true; 2796 case MCK_UImm5Lsl2: return true; 2797 case MCK_ConstantSImm6_0: return true; 2798 case MCK_ConstantUImm6_0: return true; 2799 case MCK_UImm6Lsl2: return true; 2800 case MCK_ConstantUImm7_0: return true; 2801 case MCK_UImm7_N1: return true; 2802 case MCK_ConstantUImm8_0: return true; 2803 case MCK_SImm7Lsl2: return true; 2804 case MCK_ConstantSImm9_0: return true; 2805 case MCK_ConstantSImm10_0: return true; 2806 case MCK_ConstantUImm10_0: return true; 2807 case MCK_SImm10Lsl1: return true; 2808 case MCK_ConstantSImm11_0: return true; 2809 case MCK_SImm10Lsl2: return true; 2810 case MCK_SImm10Lsl3: return true; 2811 case MCK_SImm16: return true; 2812 case MCK_SImm16_Relaxed: return true; 2813 case MCK_UImm16_Relaxed: return true; 2814 case MCK_ConstantUImm20_0: return true; 2815 case MCK_ConstantUImm26_0: return true; 2816 case MCK_SImm32: return true; 2817 case MCK_SImm32_Relaxed: return true; 2818 case MCK_UImm32_Coerced: return true; 2819 } 2820 2821 case MCK_ConstantUImm5_32_Norm: 2822 switch (B) { 2823 default: return false; 2824 case MCK_ConstantUImm5_32: return true; 2825 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2826 case MCK_ConstantUImm5_33: return true; 2827 case MCK_ConstantUImmRange2_64: return true; 2828 case MCK_UImm5Lsl2: return true; 2829 case MCK_ConstantSImm6_0: return true; 2830 case MCK_ConstantUImm6_0: return true; 2831 case MCK_UImm6Lsl2: return true; 2832 case MCK_ConstantUImm7_0: return true; 2833 case MCK_UImm7_N1: return true; 2834 case MCK_ConstantUImm8_0: return true; 2835 case MCK_SImm7Lsl2: return true; 2836 case MCK_ConstantSImm9_0: return true; 2837 case MCK_ConstantSImm10_0: return true; 2838 case MCK_ConstantUImm10_0: return true; 2839 case MCK_SImm10Lsl1: return true; 2840 case MCK_ConstantSImm11_0: return true; 2841 case MCK_SImm10Lsl2: return true; 2842 case MCK_SImm10Lsl3: return true; 2843 case MCK_SImm16: return true; 2844 case MCK_SImm16_Relaxed: return true; 2845 case MCK_UImm16_Relaxed: return true; 2846 case MCK_ConstantUImm20_0: return true; 2847 case MCK_ConstantUImm26_0: return true; 2848 case MCK_SImm32: return true; 2849 case MCK_SImm32_Relaxed: return true; 2850 case MCK_UImm32_Coerced: return true; 2851 } 2852 2853 case MCK_ConstantUImm5_32: 2854 switch (B) { 2855 default: return false; 2856 case MCK_ConstantUImm5_0_Report_UImm6: return true; 2857 case MCK_ConstantUImm5_33: return true; 2858 case MCK_ConstantUImmRange2_64: return true; 2859 case MCK_UImm5Lsl2: return true; 2860 case MCK_ConstantSImm6_0: return true; 2861 case MCK_ConstantUImm6_0: return true; 2862 case MCK_UImm6Lsl2: return true; 2863 case MCK_ConstantUImm7_0: return true; 2864 case MCK_UImm7_N1: return true; 2865 case MCK_ConstantUImm8_0: return true; 2866 case MCK_SImm7Lsl2: return true; 2867 case MCK_ConstantSImm9_0: return true; 2868 case MCK_ConstantSImm10_0: return true; 2869 case MCK_ConstantUImm10_0: return true; 2870 case MCK_SImm10Lsl1: return true; 2871 case MCK_ConstantSImm11_0: return true; 2872 case MCK_SImm10Lsl2: return true; 2873 case MCK_SImm10Lsl3: return true; 2874 case MCK_SImm16: return true; 2875 case MCK_SImm16_Relaxed: return true; 2876 case MCK_UImm16_Relaxed: return true; 2877 case MCK_ConstantUImm20_0: return true; 2878 case MCK_ConstantUImm26_0: return true; 2879 case MCK_SImm32: return true; 2880 case MCK_SImm32_Relaxed: return true; 2881 case MCK_UImm32_Coerced: return true; 2882 } 2883 2884 case MCK_ConstantUImm5_0_Report_UImm6: 2885 switch (B) { 2886 default: return false; 2887 case MCK_ConstantUImm5_33: return true; 2888 case MCK_ConstantUImmRange2_64: return true; 2889 case MCK_UImm5Lsl2: return true; 2890 case MCK_ConstantSImm6_0: return true; 2891 case MCK_ConstantUImm6_0: return true; 2892 case MCK_UImm6Lsl2: return true; 2893 case MCK_ConstantUImm7_0: return true; 2894 case MCK_UImm7_N1: return true; 2895 case MCK_ConstantUImm8_0: return true; 2896 case MCK_SImm7Lsl2: return true; 2897 case MCK_ConstantSImm9_0: return true; 2898 case MCK_ConstantSImm10_0: return true; 2899 case MCK_ConstantUImm10_0: return true; 2900 case MCK_SImm10Lsl1: return true; 2901 case MCK_ConstantSImm11_0: return true; 2902 case MCK_SImm10Lsl2: return true; 2903 case MCK_SImm10Lsl3: return true; 2904 case MCK_SImm16: return true; 2905 case MCK_SImm16_Relaxed: return true; 2906 case MCK_UImm16_Relaxed: return true; 2907 case MCK_ConstantUImm20_0: return true; 2908 case MCK_ConstantUImm26_0: return true; 2909 case MCK_SImm32: return true; 2910 case MCK_SImm32_Relaxed: return true; 2911 case MCK_UImm32_Coerced: return true; 2912 } 2913 2914 case MCK_ConstantUImm5_33: 2915 switch (B) { 2916 default: return false; 2917 case MCK_ConstantUImmRange2_64: return true; 2918 case MCK_UImm5Lsl2: return true; 2919 case MCK_ConstantSImm6_0: return true; 2920 case MCK_ConstantUImm6_0: return true; 2921 case MCK_UImm6Lsl2: return true; 2922 case MCK_ConstantUImm7_0: return true; 2923 case MCK_UImm7_N1: return true; 2924 case MCK_ConstantUImm8_0: return true; 2925 case MCK_SImm7Lsl2: return true; 2926 case MCK_ConstantSImm9_0: return true; 2927 case MCK_ConstantSImm10_0: return true; 2928 case MCK_ConstantUImm10_0: return true; 2929 case MCK_SImm10Lsl1: return true; 2930 case MCK_ConstantSImm11_0: return true; 2931 case MCK_SImm10Lsl2: return true; 2932 case MCK_SImm10Lsl3: return true; 2933 case MCK_SImm16: return true; 2934 case MCK_SImm16_Relaxed: return true; 2935 case MCK_UImm16_Relaxed: return true; 2936 case MCK_ConstantUImm20_0: return true; 2937 case MCK_ConstantUImm26_0: return true; 2938 case MCK_SImm32: return true; 2939 case MCK_SImm32_Relaxed: return true; 2940 case MCK_UImm32_Coerced: return true; 2941 } 2942 2943 case MCK_ConstantUImmRange2_64: 2944 switch (B) { 2945 default: return false; 2946 case MCK_UImm5Lsl2: return true; 2947 case MCK_ConstantSImm6_0: return true; 2948 case MCK_ConstantUImm6_0: return true; 2949 case MCK_UImm6Lsl2: return true; 2950 case MCK_ConstantUImm7_0: return true; 2951 case MCK_UImm7_N1: return true; 2952 case MCK_ConstantUImm8_0: return true; 2953 case MCK_SImm7Lsl2: return true; 2954 case MCK_ConstantSImm9_0: return true; 2955 case MCK_ConstantSImm10_0: return true; 2956 case MCK_ConstantUImm10_0: return true; 2957 case MCK_SImm10Lsl1: return true; 2958 case MCK_ConstantSImm11_0: return true; 2959 case MCK_SImm10Lsl2: return true; 2960 case MCK_SImm10Lsl3: return true; 2961 case MCK_SImm16: return true; 2962 case MCK_SImm16_Relaxed: return true; 2963 case MCK_UImm16_Relaxed: return true; 2964 case MCK_ConstantUImm20_0: return true; 2965 case MCK_ConstantUImm26_0: return true; 2966 case MCK_SImm32: return true; 2967 case MCK_SImm32_Relaxed: return true; 2968 case MCK_UImm32_Coerced: return true; 2969 } 2970 2971 case MCK_UImm5Lsl2: 2972 switch (B) { 2973 default: return false; 2974 case MCK_ConstantSImm6_0: return true; 2975 case MCK_ConstantUImm6_0: return true; 2976 case MCK_UImm6Lsl2: return true; 2977 case MCK_ConstantUImm7_0: return true; 2978 case MCK_UImm7_N1: return true; 2979 case MCK_ConstantUImm8_0: return true; 2980 case MCK_SImm7Lsl2: return true; 2981 case MCK_ConstantSImm9_0: return true; 2982 case MCK_ConstantSImm10_0: return true; 2983 case MCK_ConstantUImm10_0: return true; 2984 case MCK_SImm10Lsl1: return true; 2985 case MCK_ConstantSImm11_0: return true; 2986 case MCK_SImm10Lsl2: return true; 2987 case MCK_SImm10Lsl3: return true; 2988 case MCK_SImm16: return true; 2989 case MCK_SImm16_Relaxed: return true; 2990 case MCK_UImm16_Relaxed: return true; 2991 case MCK_ConstantUImm20_0: return true; 2992 case MCK_ConstantUImm26_0: return true; 2993 case MCK_SImm32: return true; 2994 case MCK_SImm32_Relaxed: return true; 2995 case MCK_UImm32_Coerced: return true; 2996 } 2997 2998 case MCK_ConstantSImm6_0: 2999 switch (B) { 3000 default: return false; 3001 case MCK_ConstantUImm6_0: return true; 3002 case MCK_UImm6Lsl2: return true; 3003 case MCK_ConstantUImm7_0: return true; 3004 case MCK_UImm7_N1: return true; 3005 case MCK_ConstantUImm8_0: return true; 3006 case MCK_SImm7Lsl2: return true; 3007 case MCK_ConstantSImm9_0: return true; 3008 case MCK_ConstantSImm10_0: return true; 3009 case MCK_ConstantUImm10_0: return true; 3010 case MCK_SImm10Lsl1: return true; 3011 case MCK_ConstantSImm11_0: return true; 3012 case MCK_SImm10Lsl2: return true; 3013 case MCK_SImm10Lsl3: return true; 3014 case MCK_SImm16: return true; 3015 case MCK_SImm16_Relaxed: return true; 3016 case MCK_UImm16_Relaxed: return true; 3017 case MCK_ConstantUImm20_0: return true; 3018 case MCK_ConstantUImm26_0: return true; 3019 case MCK_SImm32: return true; 3020 case MCK_SImm32_Relaxed: return true; 3021 case MCK_UImm32_Coerced: return true; 3022 } 3023 3024 case MCK_ConstantUImm6_0: 3025 switch (B) { 3026 default: return false; 3027 case MCK_UImm6Lsl2: return true; 3028 case MCK_ConstantUImm7_0: return true; 3029 case MCK_UImm7_N1: return true; 3030 case MCK_ConstantUImm8_0: return true; 3031 case MCK_SImm7Lsl2: return true; 3032 case MCK_ConstantSImm9_0: return true; 3033 case MCK_ConstantSImm10_0: return true; 3034 case MCK_ConstantUImm10_0: return true; 3035 case MCK_SImm10Lsl1: return true; 3036 case MCK_ConstantSImm11_0: return true; 3037 case MCK_SImm10Lsl2: return true; 3038 case MCK_SImm10Lsl3: return true; 3039 case MCK_SImm16: return true; 3040 case MCK_SImm16_Relaxed: return true; 3041 case MCK_UImm16_Relaxed: return true; 3042 case MCK_ConstantUImm20_0: return true; 3043 case MCK_ConstantUImm26_0: return true; 3044 case MCK_SImm32: return true; 3045 case MCK_SImm32_Relaxed: return true; 3046 case MCK_UImm32_Coerced: return true; 3047 } 3048 3049 case MCK_UImm6Lsl2: 3050 switch (B) { 3051 default: return false; 3052 case MCK_ConstantUImm7_0: return true; 3053 case MCK_UImm7_N1: return true; 3054 case MCK_ConstantUImm8_0: return true; 3055 case MCK_SImm7Lsl2: return true; 3056 case MCK_ConstantSImm9_0: return true; 3057 case MCK_ConstantSImm10_0: return true; 3058 case MCK_ConstantUImm10_0: return true; 3059 case MCK_SImm10Lsl1: return true; 3060 case MCK_ConstantSImm11_0: return true; 3061 case MCK_SImm10Lsl2: return true; 3062 case MCK_SImm10Lsl3: return true; 3063 case MCK_SImm16: return true; 3064 case MCK_SImm16_Relaxed: return true; 3065 case MCK_UImm16_Relaxed: return true; 3066 case MCK_ConstantUImm20_0: return true; 3067 case MCK_ConstantUImm26_0: return true; 3068 case MCK_SImm32: return true; 3069 case MCK_SImm32_Relaxed: return true; 3070 case MCK_UImm32_Coerced: return true; 3071 } 3072 3073 case MCK_ConstantUImm7_0: 3074 switch (B) { 3075 default: return false; 3076 case MCK_UImm7_N1: return true; 3077 case MCK_ConstantUImm8_0: return true; 3078 case MCK_SImm7Lsl2: return true; 3079 case MCK_ConstantSImm9_0: return true; 3080 case MCK_ConstantSImm10_0: return true; 3081 case MCK_ConstantUImm10_0: return true; 3082 case MCK_SImm10Lsl1: return true; 3083 case MCK_ConstantSImm11_0: return true; 3084 case MCK_SImm10Lsl2: return true; 3085 case MCK_SImm10Lsl3: return true; 3086 case MCK_SImm16: return true; 3087 case MCK_SImm16_Relaxed: return true; 3088 case MCK_UImm16_Relaxed: return true; 3089 case MCK_ConstantUImm20_0: return true; 3090 case MCK_ConstantUImm26_0: return true; 3091 case MCK_SImm32: return true; 3092 case MCK_SImm32_Relaxed: return true; 3093 case MCK_UImm32_Coerced: return true; 3094 } 3095 3096 case MCK_UImm7_N1: 3097 switch (B) { 3098 default: return false; 3099 case MCK_ConstantUImm8_0: return true; 3100 case MCK_SImm7Lsl2: return true; 3101 case MCK_ConstantSImm9_0: return true; 3102 case MCK_ConstantSImm10_0: return true; 3103 case MCK_ConstantUImm10_0: return true; 3104 case MCK_SImm10Lsl1: return true; 3105 case MCK_ConstantSImm11_0: return true; 3106 case MCK_SImm10Lsl2: return true; 3107 case MCK_SImm10Lsl3: return true; 3108 case MCK_SImm16: return true; 3109 case MCK_SImm16_Relaxed: return true; 3110 case MCK_UImm16_Relaxed: return true; 3111 case MCK_ConstantUImm20_0: return true; 3112 case MCK_ConstantUImm26_0: return true; 3113 case MCK_SImm32: return true; 3114 case MCK_SImm32_Relaxed: return true; 3115 case MCK_UImm32_Coerced: return true; 3116 } 3117 3118 case MCK_ConstantUImm8_0: 3119 switch (B) { 3120 default: return false; 3121 case MCK_SImm7Lsl2: return true; 3122 case MCK_ConstantSImm9_0: return true; 3123 case MCK_ConstantSImm10_0: return true; 3124 case MCK_ConstantUImm10_0: return true; 3125 case MCK_SImm10Lsl1: return true; 3126 case MCK_ConstantSImm11_0: return true; 3127 case MCK_SImm10Lsl2: return true; 3128 case MCK_SImm10Lsl3: return true; 3129 case MCK_SImm16: return true; 3130 case MCK_SImm16_Relaxed: return true; 3131 case MCK_UImm16_Relaxed: return true; 3132 case MCK_ConstantUImm20_0: return true; 3133 case MCK_ConstantUImm26_0: return true; 3134 case MCK_SImm32: return true; 3135 case MCK_SImm32_Relaxed: return true; 3136 case MCK_UImm32_Coerced: return true; 3137 } 3138 3139 case MCK_SImm7Lsl2: 3140 switch (B) { 3141 default: return false; 3142 case MCK_ConstantSImm9_0: return true; 3143 case MCK_ConstantSImm10_0: return true; 3144 case MCK_ConstantUImm10_0: return true; 3145 case MCK_SImm10Lsl1: return true; 3146 case MCK_ConstantSImm11_0: return true; 3147 case MCK_SImm10Lsl2: return true; 3148 case MCK_SImm10Lsl3: return true; 3149 case MCK_SImm16: return true; 3150 case MCK_SImm16_Relaxed: return true; 3151 case MCK_UImm16_Relaxed: return true; 3152 case MCK_ConstantUImm20_0: return true; 3153 case MCK_ConstantUImm26_0: return true; 3154 case MCK_SImm32: return true; 3155 case MCK_SImm32_Relaxed: return true; 3156 case MCK_UImm32_Coerced: return true; 3157 } 3158 3159 case MCK_ConstantSImm9_0: 3160 switch (B) { 3161 default: return false; 3162 case MCK_ConstantSImm10_0: return true; 3163 case MCK_ConstantUImm10_0: return true; 3164 case MCK_SImm10Lsl1: return true; 3165 case MCK_ConstantSImm11_0: return true; 3166 case MCK_SImm10Lsl2: return true; 3167 case MCK_SImm10Lsl3: return true; 3168 case MCK_SImm16: return true; 3169 case MCK_SImm16_Relaxed: return true; 3170 case MCK_UImm16_Relaxed: return true; 3171 case MCK_ConstantUImm20_0: return true; 3172 case MCK_ConstantUImm26_0: return true; 3173 case MCK_SImm32: return true; 3174 case MCK_SImm32_Relaxed: return true; 3175 case MCK_UImm32_Coerced: return true; 3176 } 3177 3178 case MCK_ConstantSImm10_0: 3179 switch (B) { 3180 default: return false; 3181 case MCK_ConstantUImm10_0: return true; 3182 case MCK_SImm10Lsl1: return true; 3183 case MCK_ConstantSImm11_0: return true; 3184 case MCK_SImm10Lsl2: return true; 3185 case MCK_SImm10Lsl3: return true; 3186 case MCK_SImm16: return true; 3187 case MCK_SImm16_Relaxed: return true; 3188 case MCK_UImm16_Relaxed: return true; 3189 case MCK_ConstantUImm20_0: return true; 3190 case MCK_ConstantUImm26_0: return true; 3191 case MCK_SImm32: return true; 3192 case MCK_SImm32_Relaxed: return true; 3193 case MCK_UImm32_Coerced: return true; 3194 } 3195 3196 case MCK_ConstantUImm10_0: 3197 switch (B) { 3198 default: return false; 3199 case MCK_SImm10Lsl1: return true; 3200 case MCK_ConstantSImm11_0: return true; 3201 case MCK_SImm10Lsl2: return true; 3202 case MCK_SImm10Lsl3: return true; 3203 case MCK_SImm16: return true; 3204 case MCK_SImm16_Relaxed: return true; 3205 case MCK_UImm16_Relaxed: return true; 3206 case MCK_ConstantUImm20_0: return true; 3207 case MCK_ConstantUImm26_0: return true; 3208 case MCK_SImm32: return true; 3209 case MCK_SImm32_Relaxed: return true; 3210 case MCK_UImm32_Coerced: return true; 3211 } 3212 3213 case MCK_SImm10Lsl1: 3214 switch (B) { 3215 default: return false; 3216 case MCK_ConstantSImm11_0: return true; 3217 case MCK_SImm10Lsl2: return true; 3218 case MCK_SImm10Lsl3: return true; 3219 case MCK_SImm16: return true; 3220 case MCK_SImm16_Relaxed: return true; 3221 case MCK_UImm16_Relaxed: return true; 3222 case MCK_ConstantUImm20_0: return true; 3223 case MCK_ConstantUImm26_0: return true; 3224 case MCK_SImm32: return true; 3225 case MCK_SImm32_Relaxed: return true; 3226 case MCK_UImm32_Coerced: return true; 3227 } 3228 3229 case MCK_ConstantSImm11_0: 3230 switch (B) { 3231 default: return false; 3232 case MCK_SImm10Lsl2: return true; 3233 case MCK_SImm10Lsl3: return true; 3234 case MCK_SImm16: return true; 3235 case MCK_SImm16_Relaxed: return true; 3236 case MCK_UImm16_Relaxed: return true; 3237 case MCK_ConstantUImm20_0: return true; 3238 case MCK_ConstantUImm26_0: return true; 3239 case MCK_SImm32: return true; 3240 case MCK_SImm32_Relaxed: return true; 3241 case MCK_UImm32_Coerced: return true; 3242 } 3243 3244 case MCK_SImm10Lsl2: 3245 switch (B) { 3246 default: return false; 3247 case MCK_SImm10Lsl3: return true; 3248 case MCK_SImm16: return true; 3249 case MCK_SImm16_Relaxed: return true; 3250 case MCK_UImm16_Relaxed: return true; 3251 case MCK_ConstantUImm20_0: return true; 3252 case MCK_ConstantUImm26_0: return true; 3253 case MCK_SImm32: return true; 3254 case MCK_SImm32_Relaxed: return true; 3255 case MCK_UImm32_Coerced: return true; 3256 } 3257 3258 case MCK_SImm10Lsl3: 3259 switch (B) { 3260 default: return false; 3261 case MCK_SImm16: return true; 3262 case MCK_SImm16_Relaxed: return true; 3263 case MCK_UImm16_Relaxed: return true; 3264 case MCK_ConstantUImm20_0: return true; 3265 case MCK_ConstantUImm26_0: return true; 3266 case MCK_SImm32: return true; 3267 case MCK_SImm32_Relaxed: return true; 3268 case MCK_UImm32_Coerced: return true; 3269 } 3270 3271 case MCK_SImm16: 3272 switch (B) { 3273 default: return false; 3274 case MCK_SImm16_Relaxed: return true; 3275 case MCK_UImm16_Relaxed: return true; 3276 case MCK_ConstantUImm20_0: return true; 3277 case MCK_ConstantUImm26_0: return true; 3278 case MCK_SImm32: return true; 3279 case MCK_SImm32_Relaxed: return true; 3280 case MCK_UImm32_Coerced: return true; 3281 } 3282 3283 case MCK_SImm16_Relaxed: 3284 switch (B) { 3285 default: return false; 3286 case MCK_UImm16_Relaxed: return true; 3287 case MCK_ConstantUImm20_0: return true; 3288 case MCK_ConstantUImm26_0: return true; 3289 case MCK_SImm32: return true; 3290 case MCK_SImm32_Relaxed: return true; 3291 case MCK_UImm32_Coerced: return true; 3292 } 3293 3294 case MCK_UImm16_AltRelaxed: 3295 switch (B) { 3296 default: return false; 3297 case MCK_UImm16_Relaxed: return true; 3298 case MCK_ConstantUImm20_0: return true; 3299 case MCK_ConstantUImm26_0: return true; 3300 case MCK_SImm32: return true; 3301 case MCK_SImm32_Relaxed: return true; 3302 case MCK_UImm32_Coerced: return true; 3303 } 3304 3305 case MCK_UImm16: 3306 switch (B) { 3307 default: return false; 3308 case MCK_UImm16_Relaxed: return true; 3309 case MCK_ConstantUImm20_0: return true; 3310 case MCK_ConstantUImm26_0: return true; 3311 case MCK_SImm32: return true; 3312 case MCK_SImm32_Relaxed: return true; 3313 case MCK_UImm32_Coerced: return true; 3314 } 3315 3316 case MCK_SImm19Lsl2: 3317 switch (B) { 3318 default: return false; 3319 case MCK_ConstantUImm20_0: return true; 3320 case MCK_ConstantUImm26_0: return true; 3321 case MCK_SImm32: return true; 3322 case MCK_SImm32_Relaxed: return true; 3323 case MCK_UImm32_Coerced: return true; 3324 } 3325 3326 case MCK_UImm16_Relaxed: 3327 switch (B) { 3328 default: return false; 3329 case MCK_ConstantUImm20_0: return true; 3330 case MCK_ConstantUImm26_0: return true; 3331 case MCK_SImm32: return true; 3332 case MCK_SImm32_Relaxed: return true; 3333 case MCK_UImm32_Coerced: return true; 3334 } 3335 3336 case MCK_ConstantUImm20_0: 3337 switch (B) { 3338 default: return false; 3339 case MCK_ConstantUImm26_0: return true; 3340 case MCK_SImm32: return true; 3341 case MCK_SImm32_Relaxed: return true; 3342 case MCK_UImm32_Coerced: return true; 3343 } 3344 3345 case MCK_ConstantUImm26_0: 3346 switch (B) { 3347 default: return false; 3348 case MCK_SImm32: return true; 3349 case MCK_SImm32_Relaxed: return true; 3350 case MCK_UImm32_Coerced: return true; 3351 } 3352 3353 case MCK_SImm32: 3354 switch (B) { 3355 default: return false; 3356 case MCK_SImm32_Relaxed: return true; 3357 case MCK_UImm32_Coerced: return true; 3358 } 3359 3360 case MCK_SImm32_Relaxed: 3361 return B == MCK_UImm32_Coerced; 3362 } 3363} 3364 3365static unsigned validateOperandClass(MCParsedAsmOperand &GOp, MatchClassKind Kind) { 3366 MipsOperand &Operand = (MipsOperand&)GOp; 3367 if (Kind == InvalidMatchClass) 3368 return MCTargetAsmParser::Match_InvalidOperand; 3369 3370 if (Operand.isToken() && Kind <= MCK_LAST_TOKEN) 3371 return isSubclass(matchTokenString(Operand.getToken()), Kind) ? 3372 MCTargetAsmParser::Match_Success : 3373 MCTargetAsmParser::Match_InvalidOperand; 3374 3375 switch (Kind) { 3376 default: break; 3377 // 'ACC64DSPAsmReg' class 3378 case MCK_ACC64DSPAsmReg: { 3379 DiagnosticPredicate DP(Operand.isACCAsmReg()); 3380 if (DP.isMatch()) 3381 return MCTargetAsmParser::Match_Success; 3382 break; 3383 } 3384 // 'AFGR64AsmReg' class 3385 case MCK_AFGR64AsmReg: { 3386 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3387 if (DP.isMatch()) 3388 return MCTargetAsmParser::Match_Success; 3389 break; 3390 } 3391 // 'CCRAsmReg' class 3392 case MCK_CCRAsmReg: { 3393 DiagnosticPredicate DP(Operand.isCCRAsmReg()); 3394 if (DP.isMatch()) 3395 return MCTargetAsmParser::Match_Success; 3396 break; 3397 } 3398 // 'COP0AsmReg' class 3399 case MCK_COP0AsmReg: { 3400 DiagnosticPredicate DP(Operand.isCOP0AsmReg()); 3401 if (DP.isMatch()) 3402 return MCTargetAsmParser::Match_Success; 3403 break; 3404 } 3405 // 'COP2AsmReg' class 3406 case MCK_COP2AsmReg: { 3407 DiagnosticPredicate DP(Operand.isCOP2AsmReg()); 3408 if (DP.isMatch()) 3409 return MCTargetAsmParser::Match_Success; 3410 break; 3411 } 3412 // 'COP3AsmReg' class 3413 case MCK_COP3AsmReg: { 3414 DiagnosticPredicate DP(Operand.isCOP3AsmReg()); 3415 if (DP.isMatch()) 3416 return MCTargetAsmParser::Match_Success; 3417 break; 3418 } 3419 // 'FCCAsmReg' class 3420 case MCK_FCCAsmReg: { 3421 DiagnosticPredicate DP(Operand.isFCCAsmReg()); 3422 if (DP.isMatch()) 3423 return MCTargetAsmParser::Match_Success; 3424 break; 3425 } 3426 // 'FGR32AsmReg' class 3427 case MCK_FGR32AsmReg: { 3428 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3429 if (DP.isMatch()) 3430 return MCTargetAsmParser::Match_Success; 3431 break; 3432 } 3433 // 'FGR64AsmReg' class 3434 case MCK_FGR64AsmReg: { 3435 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3436 if (DP.isMatch()) 3437 return MCTargetAsmParser::Match_Success; 3438 break; 3439 } 3440 // 'FGRH32AsmReg' class 3441 case MCK_FGRH32AsmReg: { 3442 DiagnosticPredicate DP(Operand.isFGRAsmReg()); 3443 if (DP.isMatch()) 3444 return MCTargetAsmParser::Match_Success; 3445 break; 3446 } 3447 // 'GPR32AsmReg' class 3448 case MCK_GPR32AsmReg: { 3449 DiagnosticPredicate DP(Operand.isGPRAsmReg()); 3450 if (DP.isMatch()) 3451 return MCTargetAsmParser::Match_Success; 3452 break; 3453 } 3454 // 'GPR32NonZeroAsmReg' class 3455 case MCK_GPR32NonZeroAsmReg: { 3456 DiagnosticPredicate DP(Operand.isGPRNonZeroAsmReg()); 3457 if (DP.isMatch()) 3458 return MCTargetAsmParser::Match_Success; 3459 break; 3460 } 3461 // 'GPR32ZeroAsmReg' class 3462 case MCK_GPR32ZeroAsmReg: { 3463 DiagnosticPredicate DP(Operand.isGPRZeroAsmReg()); 3464 if (DP.isMatch()) 3465 return MCTargetAsmParser::Match_Success; 3466 break; 3467 } 3468 // 'GPR64AsmReg' class 3469 case MCK_GPR64AsmReg: { 3470 DiagnosticPredicate DP(Operand.isGPRAsmReg()); 3471 if (DP.isMatch()) 3472 return MCTargetAsmParser::Match_Success; 3473 break; 3474 } 3475 // 'GPRMM16AsmReg' class 3476 case MCK_GPRMM16AsmReg: { 3477 DiagnosticPredicate DP(Operand.isMM16AsmReg()); 3478 if (DP.isMatch()) 3479 return MCTargetAsmParser::Match_Success; 3480 break; 3481 } 3482 // 'GPRMM16AsmRegMoveP' class 3483 case MCK_GPRMM16AsmRegMoveP: { 3484 DiagnosticPredicate DP(Operand.isMM16AsmRegMoveP()); 3485 if (DP.isMatch()) 3486 return MCTargetAsmParser::Match_Success; 3487 break; 3488 } 3489 // 'GPRMM16AsmRegZero' class 3490 case MCK_GPRMM16AsmRegZero: { 3491 DiagnosticPredicate DP(Operand.isMM16AsmRegZero()); 3492 if (DP.isMatch()) 3493 return MCTargetAsmParser::Match_Success; 3494 break; 3495 } 3496 // 'HI32DSPAsmReg' class 3497 case MCK_HI32DSPAsmReg: { 3498 DiagnosticPredicate DP(Operand.isACCAsmReg()); 3499 if (DP.isMatch()) 3500 return MCTargetAsmParser::Match_Success; 3501 break; 3502 } 3503 // 'HWRegsAsmReg' class 3504 case MCK_HWRegsAsmReg: { 3505 DiagnosticPredicate DP(Operand.isHWRegsAsmReg()); 3506 if (DP.isMatch()) 3507 return MCTargetAsmParser::Match_Success; 3508 break; 3509 } 3510 // 'Imm' class 3511 case MCK_Imm: { 3512 DiagnosticPredicate DP(Operand.isImm()); 3513 if (DP.isMatch()) 3514 return MCTargetAsmParser::Match_Success; 3515 break; 3516 } 3517 // 'LO32DSPAsmReg' class 3518 case MCK_LO32DSPAsmReg: { 3519 DiagnosticPredicate DP(Operand.isACCAsmReg()); 3520 if (DP.isMatch()) 3521 return MCTargetAsmParser::Match_Success; 3522 break; 3523 } 3524 // 'MSA128AsmReg' class 3525 case MCK_MSA128AsmReg: { 3526 DiagnosticPredicate DP(Operand.isMSA128AsmReg()); 3527 if (DP.isMatch()) 3528 return MCTargetAsmParser::Match_Success; 3529 break; 3530 } 3531 // 'MSACtrlAsmReg' class 3532 case MCK_MSACtrlAsmReg: { 3533 DiagnosticPredicate DP(Operand.isMSACtrlAsmReg()); 3534 if (DP.isMatch()) 3535 return MCTargetAsmParser::Match_Success; 3536 break; 3537 } 3538 // 'MicroMipsMemGP' class 3539 case MCK_MicroMipsMemGP: { 3540 DiagnosticPredicate DP(Operand.isMemWithSimmWordAlignedOffsetGP<9>()); 3541 if (DP.isMatch()) 3542 return MCTargetAsmParser::Match_Success; 3543 break; 3544 } 3545 // 'MicroMipsMem' class 3546 case MCK_MicroMipsMem: { 3547 DiagnosticPredicate DP(Operand.isMemWithGRPMM16Base()); 3548 if (DP.isMatch()) 3549 return MCTargetAsmParser::Match_Success; 3550 break; 3551 } 3552 // 'MicroMipsMemSP' class 3553 case MCK_MicroMipsMemSP: { 3554 DiagnosticPredicate DP(Operand.isMemWithUimmWordAlignedOffsetSP<7>()); 3555 if (DP.isMatch()) 3556 return MCTargetAsmParser::Match_Success; 3557 break; 3558 } 3559 // 'InvNum' class 3560 case MCK_InvNum: { 3561 DiagnosticPredicate DP(Operand.isInvNum()); 3562 if (DP.isMatch()) 3563 return MCTargetAsmParser::Match_Success; 3564 break; 3565 } 3566 // 'JumpTarget' class 3567 case MCK_JumpTarget: { 3568 DiagnosticPredicate DP(Operand.isImm()); 3569 if (DP.isMatch()) 3570 return MCTargetAsmParser::Match_Success; 3571 break; 3572 } 3573 // 'MemOffsetSimm10' class 3574 case MCK_MemOffsetSimm10: { 3575 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10>()); 3576 if (DP.isMatch()) 3577 return MCTargetAsmParser::Match_Success; 3578 if (DP.isNearMatch()) 3579 return MipsAsmParser::Match_MemSImm10; 3580 break; 3581 } 3582 // 'MemOffsetSimm10_1' class 3583 case MCK_MemOffsetSimm10_1: { 3584 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 1>()); 3585 if (DP.isMatch()) 3586 return MCTargetAsmParser::Match_Success; 3587 if (DP.isNearMatch()) 3588 return MipsAsmParser::Match_MemSImm10Lsl1; 3589 break; 3590 } 3591 // 'MemOffsetSimm10_2' class 3592 case MCK_MemOffsetSimm10_2: { 3593 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 2>()); 3594 if (DP.isMatch()) 3595 return MCTargetAsmParser::Match_Success; 3596 if (DP.isNearMatch()) 3597 return MipsAsmParser::Match_MemSImm10Lsl2; 3598 break; 3599 } 3600 // 'MemOffsetSimm10_3' class 3601 case MCK_MemOffsetSimm10_3: { 3602 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<10, 3>()); 3603 if (DP.isMatch()) 3604 return MCTargetAsmParser::Match_Success; 3605 if (DP.isNearMatch()) 3606 return MipsAsmParser::Match_MemSImm10Lsl3; 3607 break; 3608 } 3609 // 'MemOffsetSimm11' class 3610 case MCK_MemOffsetSimm11: { 3611 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<11>()); 3612 if (DP.isMatch()) 3613 return MCTargetAsmParser::Match_Success; 3614 if (DP.isNearMatch()) 3615 return MipsAsmParser::Match_MemSImm11; 3616 break; 3617 } 3618 // 'MemOffsetSimm12' class 3619 case MCK_MemOffsetSimm12: { 3620 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<12>()); 3621 if (DP.isMatch()) 3622 return MCTargetAsmParser::Match_Success; 3623 if (DP.isNearMatch()) 3624 return MipsAsmParser::Match_MemSImm12; 3625 break; 3626 } 3627 // 'MemOffsetSimm16' class 3628 case MCK_MemOffsetSimm16: { 3629 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<16>()); 3630 if (DP.isMatch()) 3631 return MCTargetAsmParser::Match_Success; 3632 if (DP.isNearMatch()) 3633 return MipsAsmParser::Match_MemSImm16; 3634 break; 3635 } 3636 // 'MemOffsetSimm9' class 3637 case MCK_MemOffsetSimm9: { 3638 DiagnosticPredicate DP(Operand.isMemWithSimmOffset<9>()); 3639 if (DP.isMatch()) 3640 return MCTargetAsmParser::Match_Success; 3641 if (DP.isNearMatch()) 3642 return MipsAsmParser::Match_MemSImm9; 3643 break; 3644 } 3645 // 'MemOffsetSimmPtr' class 3646 case MCK_MemOffsetSimmPtr: { 3647 DiagnosticPredicate DP(Operand.isMemWithPtrSizeOffset()); 3648 if (DP.isMatch()) 3649 return MCTargetAsmParser::Match_Success; 3650 if (DP.isNearMatch()) 3651 return MipsAsmParser::Match_MemSImmPtr; 3652 break; 3653 } 3654 // 'MemOffsetUimm4' class 3655 case MCK_MemOffsetUimm4: { 3656 DiagnosticPredicate DP(Operand.isMemWithUimmOffsetSP<6>()); 3657 if (DP.isMatch()) 3658 return MCTargetAsmParser::Match_Success; 3659 break; 3660 } 3661 // 'Mem' class 3662 case MCK_Mem: { 3663 DiagnosticPredicate DP(Operand.isMem()); 3664 if (DP.isMatch()) 3665 return MCTargetAsmParser::Match_Success; 3666 break; 3667 } 3668 // 'MovePRegPair' class 3669 case MCK_MovePRegPair: { 3670 DiagnosticPredicate DP(Operand.isMovePRegPair()); 3671 if (DP.isMatch()) 3672 return MCTargetAsmParser::Match_Success; 3673 break; 3674 } 3675 // 'RegList16' class 3676 case MCK_RegList16: { 3677 DiagnosticPredicate DP(Operand.isRegList16()); 3678 if (DP.isMatch()) 3679 return MCTargetAsmParser::Match_Success; 3680 break; 3681 } 3682 // 'RegList' class 3683 case MCK_RegList: { 3684 DiagnosticPredicate DP(Operand.isRegList()); 3685 if (DP.isMatch()) 3686 return MCTargetAsmParser::Match_Success; 3687 break; 3688 } 3689 // 'Simm19_Lsl2' class 3690 case MCK_Simm19_Lsl2: { 3691 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); 3692 if (DP.isMatch()) 3693 return MCTargetAsmParser::Match_Success; 3694 if (DP.isNearMatch()) 3695 return MipsAsmParser::Match_SImm19_Lsl2; 3696 break; 3697 } 3698 // 'StrictlyAFGR64AsmReg' class 3699 case MCK_StrictlyAFGR64AsmReg: { 3700 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); 3701 if (DP.isMatch()) 3702 return MCTargetAsmParser::Match_Success; 3703 break; 3704 } 3705 // 'StrictlyFGR32AsmReg' class 3706 case MCK_StrictlyFGR32AsmReg: { 3707 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); 3708 if (DP.isMatch()) 3709 return MCTargetAsmParser::Match_Success; 3710 break; 3711 } 3712 // 'StrictlyFGR64AsmReg' class 3713 case MCK_StrictlyFGR64AsmReg: { 3714 DiagnosticPredicate DP(Operand.isStrictlyFGRAsmReg()); 3715 if (DP.isMatch()) 3716 return MCTargetAsmParser::Match_Success; 3717 break; 3718 } 3719 // 'ConstantImmz' class 3720 case MCK_ConstantImmz: { 3721 DiagnosticPredicate DP(Operand.isConstantImmz()); 3722 if (DP.isMatch()) 3723 return MCTargetAsmParser::Match_Success; 3724 if (DP.isNearMatch()) 3725 return MipsAsmParser::Match_Immz; 3726 break; 3727 } 3728 // 'ConstantUImm1_0' class 3729 case MCK_ConstantUImm1_0: { 3730 DiagnosticPredicate DP(Operand.isConstantUImm<1, 0>()); 3731 if (DP.isMatch()) 3732 return MCTargetAsmParser::Match_Success; 3733 if (DP.isNearMatch()) 3734 return MipsAsmParser::Match_UImm1_0; 3735 break; 3736 } 3737 // 'ConstantUImm2_0' class 3738 case MCK_ConstantUImm2_0: { 3739 DiagnosticPredicate DP(Operand.isConstantUImm<2, 0>()); 3740 if (DP.isMatch()) 3741 return MCTargetAsmParser::Match_Success; 3742 if (DP.isNearMatch()) 3743 return MipsAsmParser::Match_UImm2_0; 3744 break; 3745 } 3746 // 'ConstantUImm2_1' class 3747 case MCK_ConstantUImm2_1: { 3748 DiagnosticPredicate DP(Operand.isConstantUImm<2, 1>()); 3749 if (DP.isMatch()) 3750 return MCTargetAsmParser::Match_Success; 3751 if (DP.isNearMatch()) 3752 return MipsAsmParser::Match_UImm2_1; 3753 break; 3754 } 3755 // 'ConstantUImm3_0' class 3756 case MCK_ConstantUImm3_0: { 3757 DiagnosticPredicate DP(Operand.isConstantUImm<3, 0>()); 3758 if (DP.isMatch()) 3759 return MCTargetAsmParser::Match_Success; 3760 if (DP.isNearMatch()) 3761 return MipsAsmParser::Match_UImm3_0; 3762 break; 3763 } 3764 // 'ConstantSImm4_0' class 3765 case MCK_ConstantSImm4_0: { 3766 DiagnosticPredicate DP(Operand.isConstantSImm<4, 0>()); 3767 if (DP.isMatch()) 3768 return MCTargetAsmParser::Match_Success; 3769 if (DP.isNearMatch()) 3770 return MipsAsmParser::Match_SImm4_0; 3771 break; 3772 } 3773 // 'ConstantUImm4_0' class 3774 case MCK_ConstantUImm4_0: { 3775 DiagnosticPredicate DP(Operand.isConstantUImm<4, 0>()); 3776 if (DP.isMatch()) 3777 return MCTargetAsmParser::Match_Success; 3778 if (DP.isNearMatch()) 3779 return MipsAsmParser::Match_UImm4_0; 3780 break; 3781 } 3782 // 'ConstantSImm5_0' class 3783 case MCK_ConstantSImm5_0: { 3784 DiagnosticPredicate DP(Operand.isConstantSImm<5, 0>()); 3785 if (DP.isMatch()) 3786 return MCTargetAsmParser::Match_Success; 3787 if (DP.isNearMatch()) 3788 return MipsAsmParser::Match_SImm5_0; 3789 break; 3790 } 3791 // 'ConstantUImm5_0' class 3792 case MCK_ConstantUImm5_0: { 3793 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); 3794 if (DP.isMatch()) 3795 return MCTargetAsmParser::Match_Success; 3796 if (DP.isNearMatch()) 3797 return MipsAsmParser::Match_UImm5_0; 3798 break; 3799 } 3800 // 'ConstantUImm5_1' class 3801 case MCK_ConstantUImm5_1: { 3802 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); 3803 if (DP.isMatch()) 3804 return MCTargetAsmParser::Match_Success; 3805 if (DP.isNearMatch()) 3806 return MipsAsmParser::Match_UImm5_1; 3807 break; 3808 } 3809 // 'ConstantUImm5_Plus1_Report_UImm6' class 3810 case MCK_ConstantUImm5_Plus1_Report_UImm6: { 3811 DiagnosticPredicate DP(Operand.isConstantUImm<5, 1>()); 3812 if (DP.isMatch()) 3813 return MCTargetAsmParser::Match_Success; 3814 if (DP.isNearMatch()) 3815 return MipsAsmParser::Match_UImm5_1; 3816 break; 3817 } 3818 // 'ConstantUImm5_32_Norm' class 3819 case MCK_ConstantUImm5_32_Norm: { 3820 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); 3821 if (DP.isMatch()) 3822 return MCTargetAsmParser::Match_Success; 3823 if (DP.isNearMatch()) 3824 return MipsAsmParser::Match_UImm5_32; 3825 break; 3826 } 3827 // 'ConstantUImm5_32' class 3828 case MCK_ConstantUImm5_32: { 3829 DiagnosticPredicate DP(Operand.isConstantUImm<5, 32>()); 3830 if (DP.isMatch()) 3831 return MCTargetAsmParser::Match_Success; 3832 if (DP.isNearMatch()) 3833 return MipsAsmParser::Match_UImm5_32; 3834 break; 3835 } 3836 // 'ConstantUImm5_0_Report_UImm6' class 3837 case MCK_ConstantUImm5_0_Report_UImm6: { 3838 DiagnosticPredicate DP(Operand.isConstantUImm<5, 0>()); 3839 if (DP.isMatch()) 3840 return MCTargetAsmParser::Match_Success; 3841 if (DP.isNearMatch()) 3842 return MipsAsmParser::Match_UImm5_0_Report_UImm6; 3843 break; 3844 } 3845 // 'ConstantUImm5_33' class 3846 case MCK_ConstantUImm5_33: { 3847 DiagnosticPredicate DP(Operand.isConstantUImm<5, 33>()); 3848 if (DP.isMatch()) 3849 return MCTargetAsmParser::Match_Success; 3850 if (DP.isNearMatch()) 3851 return MipsAsmParser::Match_UImm5_33; 3852 break; 3853 } 3854 // 'ConstantUImmRange2_64' class 3855 case MCK_ConstantUImmRange2_64: { 3856 DiagnosticPredicate DP(Operand.isConstantUImmRange<2, 64>()); 3857 if (DP.isMatch()) 3858 return MCTargetAsmParser::Match_Success; 3859 if (DP.isNearMatch()) 3860 return MipsAsmParser::Match_UImmRange2_64; 3861 break; 3862 } 3863 // 'UImm5Lsl2' class 3864 case MCK_UImm5Lsl2: { 3865 DiagnosticPredicate DP(Operand.isScaledUImm<5, 2>()); 3866 if (DP.isMatch()) 3867 return MCTargetAsmParser::Match_Success; 3868 if (DP.isNearMatch()) 3869 return MipsAsmParser::Match_UImm5_Lsl2; 3870 break; 3871 } 3872 // 'ConstantSImm6_0' class 3873 case MCK_ConstantSImm6_0: { 3874 DiagnosticPredicate DP(Operand.isConstantSImm<6, 0>()); 3875 if (DP.isMatch()) 3876 return MCTargetAsmParser::Match_Success; 3877 if (DP.isNearMatch()) 3878 return MipsAsmParser::Match_SImm6_0; 3879 break; 3880 } 3881 // 'ConstantUImm6_0' class 3882 case MCK_ConstantUImm6_0: { 3883 DiagnosticPredicate DP(Operand.isConstantUImm<6, 0>()); 3884 if (DP.isMatch()) 3885 return MCTargetAsmParser::Match_Success; 3886 if (DP.isNearMatch()) 3887 return MipsAsmParser::Match_UImm6_0; 3888 break; 3889 } 3890 // 'UImm6Lsl2' class 3891 case MCK_UImm6Lsl2: { 3892 DiagnosticPredicate DP(Operand.isScaledUImm<6, 2>()); 3893 if (DP.isMatch()) 3894 return MCTargetAsmParser::Match_Success; 3895 if (DP.isNearMatch()) 3896 return MipsAsmParser::Match_UImm6_Lsl2; 3897 break; 3898 } 3899 // 'ConstantUImm7_0' class 3900 case MCK_ConstantUImm7_0: { 3901 DiagnosticPredicate DP(Operand.isConstantUImm<7, 0>()); 3902 if (DP.isMatch()) 3903 return MCTargetAsmParser::Match_Success; 3904 if (DP.isNearMatch()) 3905 return MipsAsmParser::Match_UImm7_0; 3906 break; 3907 } 3908 // 'UImm7_N1' class 3909 case MCK_UImm7_N1: { 3910 DiagnosticPredicate DP(Operand.isConstantUImm<7, -1>()); 3911 if (DP.isMatch()) 3912 return MCTargetAsmParser::Match_Success; 3913 if (DP.isNearMatch()) 3914 return MipsAsmParser::Match_UImm7_N1; 3915 break; 3916 } 3917 // 'ConstantUImm8_0' class 3918 case MCK_ConstantUImm8_0: { 3919 DiagnosticPredicate DP(Operand.isConstantUImm<8, 0>()); 3920 if (DP.isMatch()) 3921 return MCTargetAsmParser::Match_Success; 3922 if (DP.isNearMatch()) 3923 return MipsAsmParser::Match_UImm8_0; 3924 break; 3925 } 3926 // 'SImm7Lsl2' class 3927 case MCK_SImm7Lsl2: { 3928 DiagnosticPredicate DP(Operand.isScaledSImm<7, 2>()); 3929 if (DP.isMatch()) 3930 return MCTargetAsmParser::Match_Success; 3931 if (DP.isNearMatch()) 3932 return MipsAsmParser::Match_SImm7_Lsl2; 3933 break; 3934 } 3935 // 'ConstantSImm9_0' class 3936 case MCK_ConstantSImm9_0: { 3937 DiagnosticPredicate DP(Operand.isConstantSImm<9, 0>()); 3938 if (DP.isMatch()) 3939 return MCTargetAsmParser::Match_Success; 3940 if (DP.isNearMatch()) 3941 return MipsAsmParser::Match_SImm9_0; 3942 break; 3943 } 3944 // 'ConstantSImm10_0' class 3945 case MCK_ConstantSImm10_0: { 3946 DiagnosticPredicate DP(Operand.isConstantSImm<10, 0>()); 3947 if (DP.isMatch()) 3948 return MCTargetAsmParser::Match_Success; 3949 if (DP.isNearMatch()) 3950 return MipsAsmParser::Match_SImm10_0; 3951 break; 3952 } 3953 // 'ConstantUImm10_0' class 3954 case MCK_ConstantUImm10_0: { 3955 DiagnosticPredicate DP(Operand.isConstantUImm<10, 0>()); 3956 if (DP.isMatch()) 3957 return MCTargetAsmParser::Match_Success; 3958 if (DP.isNearMatch()) 3959 return MipsAsmParser::Match_UImm10_0; 3960 break; 3961 } 3962 // 'SImm10Lsl1' class 3963 case MCK_SImm10Lsl1: { 3964 DiagnosticPredicate DP(Operand.isScaledSImm<10, 1>()); 3965 if (DP.isMatch()) 3966 return MCTargetAsmParser::Match_Success; 3967 if (DP.isNearMatch()) 3968 return MipsAsmParser::Match_SImm10_Lsl1; 3969 break; 3970 } 3971 // 'ConstantSImm11_0' class 3972 case MCK_ConstantSImm11_0: { 3973 DiagnosticPredicate DP(Operand.isConstantSImm<11, 0>()); 3974 if (DP.isMatch()) 3975 return MCTargetAsmParser::Match_Success; 3976 if (DP.isNearMatch()) 3977 return MipsAsmParser::Match_SImm11_0; 3978 break; 3979 } 3980 // 'SImm10Lsl2' class 3981 case MCK_SImm10Lsl2: { 3982 DiagnosticPredicate DP(Operand.isScaledSImm<10, 2>()); 3983 if (DP.isMatch()) 3984 return MCTargetAsmParser::Match_Success; 3985 if (DP.isNearMatch()) 3986 return MipsAsmParser::Match_SImm10_Lsl2; 3987 break; 3988 } 3989 // 'SImm10Lsl3' class 3990 case MCK_SImm10Lsl3: { 3991 DiagnosticPredicate DP(Operand.isScaledSImm<10, 3>()); 3992 if (DP.isMatch()) 3993 return MCTargetAsmParser::Match_Success; 3994 if (DP.isNearMatch()) 3995 return MipsAsmParser::Match_SImm10_Lsl3; 3996 break; 3997 } 3998 // 'SImm16' class 3999 case MCK_SImm16: { 4000 DiagnosticPredicate DP(Operand.isSImm<16>()); 4001 if (DP.isMatch()) 4002 return MCTargetAsmParser::Match_Success; 4003 if (DP.isNearMatch()) 4004 return MipsAsmParser::Match_SImm16; 4005 break; 4006 } 4007 // 'SImm16_Relaxed' class 4008 case MCK_SImm16_Relaxed: { 4009 DiagnosticPredicate DP(Operand.isAnyImm<16>()); 4010 if (DP.isMatch()) 4011 return MCTargetAsmParser::Match_Success; 4012 if (DP.isNearMatch()) 4013 return MipsAsmParser::Match_SImm16_Relaxed; 4014 break; 4015 } 4016 // 'UImm16_AltRelaxed' class 4017 case MCK_UImm16_AltRelaxed: { 4018 DiagnosticPredicate DP(Operand.isUImm<16>()); 4019 if (DP.isMatch()) 4020 return MCTargetAsmParser::Match_Success; 4021 if (DP.isNearMatch()) 4022 return MipsAsmParser::Match_UImm16_AltRelaxed; 4023 break; 4024 } 4025 // 'UImm16' class 4026 case MCK_UImm16: { 4027 DiagnosticPredicate DP(Operand.isUImm<16>()); 4028 if (DP.isMatch()) 4029 return MCTargetAsmParser::Match_Success; 4030 if (DP.isNearMatch()) 4031 return MipsAsmParser::Match_UImm16; 4032 break; 4033 } 4034 // 'SImm19Lsl2' class 4035 case MCK_SImm19Lsl2: { 4036 DiagnosticPredicate DP(Operand.isScaledSImm<19, 2>()); 4037 if (DP.isMatch()) 4038 return MCTargetAsmParser::Match_Success; 4039 if (DP.isNearMatch()) 4040 return MipsAsmParser::Match_SImm19_Lsl2; 4041 break; 4042 } 4043 // 'UImm16_Relaxed' class 4044 case MCK_UImm16_Relaxed: { 4045 DiagnosticPredicate DP(Operand.isAnyImm<16>()); 4046 if (DP.isMatch()) 4047 return MCTargetAsmParser::Match_Success; 4048 if (DP.isNearMatch()) 4049 return MipsAsmParser::Match_UImm16_Relaxed; 4050 break; 4051 } 4052 // 'ConstantUImm20_0' class 4053 case MCK_ConstantUImm20_0: { 4054 DiagnosticPredicate DP(Operand.isConstantUImm<20, 0>()); 4055 if (DP.isMatch()) 4056 return MCTargetAsmParser::Match_Success; 4057 if (DP.isNearMatch()) 4058 return MipsAsmParser::Match_UImm20_0; 4059 break; 4060 } 4061 // 'ConstantUImm26_0' class 4062 case MCK_ConstantUImm26_0: { 4063 DiagnosticPredicate DP(Operand.isConstantUImm<26, 0>()); 4064 if (DP.isMatch()) 4065 return MCTargetAsmParser::Match_Success; 4066 if (DP.isNearMatch()) 4067 return MipsAsmParser::Match_UImm26_0; 4068 break; 4069 } 4070 // 'SImm32' class 4071 case MCK_SImm32: { 4072 DiagnosticPredicate DP(Operand.isSImm<32>()); 4073 if (DP.isMatch()) 4074 return MCTargetAsmParser::Match_Success; 4075 if (DP.isNearMatch()) 4076 return MipsAsmParser::Match_SImm32; 4077 break; 4078 } 4079 // 'SImm32_Relaxed' class 4080 case MCK_SImm32_Relaxed: { 4081 DiagnosticPredicate DP(Operand.isAnyImm<33>()); 4082 if (DP.isMatch()) 4083 return MCTargetAsmParser::Match_Success; 4084 if (DP.isNearMatch()) 4085 return MipsAsmParser::Match_SImm32_Relaxed; 4086 break; 4087 } 4088 // 'UImm32_Coerced' class 4089 case MCK_UImm32_Coerced: { 4090 DiagnosticPredicate DP(Operand.isSImm<33>()); 4091 if (DP.isMatch()) 4092 return MCTargetAsmParser::Match_Success; 4093 if (DP.isNearMatch()) 4094 return MipsAsmParser::Match_UImm32_Coerced; 4095 break; 4096 } 4097 } // end switch (Kind) 4098 4099 if (Operand.isReg()) { 4100 MatchClassKind OpKind; 4101 switch (Operand.getReg()) { 4102 default: OpKind = InvalidMatchClass; break; 4103 case Mips::ZERO: OpKind = MCK_GPR32ZERO; break; 4104 case Mips::AT: OpKind = MCK_GPR32NONZERO; break; 4105 case Mips::V0: OpKind = MCK_Reg11; break; 4106 case Mips::V1: OpKind = MCK_Reg11; break; 4107 case Mips::A0: OpKind = MCK_Reg8; break; 4108 case Mips::A1: OpKind = MCK_Reg8; break; 4109 case Mips::A2: OpKind = MCK_Reg8; break; 4110 case Mips::A3: OpKind = MCK_Reg8; break; 4111 case Mips::T0: OpKind = MCK_GPR32NONZERO; break; 4112 case Mips::T1: OpKind = MCK_GPR32NONZERO; break; 4113 case Mips::T2: OpKind = MCK_GPR32NONZERO; break; 4114 case Mips::T3: OpKind = MCK_GPR32NONZERO; break; 4115 case Mips::T4: OpKind = MCK_GPR32NONZERO; break; 4116 case Mips::T5: OpKind = MCK_GPR32NONZERO; break; 4117 case Mips::T6: OpKind = MCK_GPR32NONZERO; break; 4118 case Mips::T7: OpKind = MCK_GPR32NONZERO; break; 4119 case Mips::S0: OpKind = MCK_Reg9; break; 4120 case Mips::S1: OpKind = MCK_Reg11; break; 4121 case Mips::S2: OpKind = MCK_Reg10; break; 4122 case Mips::S3: OpKind = MCK_Reg10; break; 4123 case Mips::S4: OpKind = MCK_Reg10; break; 4124 case Mips::S5: OpKind = MCK_GPR32NONZERO; break; 4125 case Mips::S6: OpKind = MCK_GPR32NONZERO; break; 4126 case Mips::S7: OpKind = MCK_GPR32NONZERO; break; 4127 case Mips::T8: OpKind = MCK_GPR32NONZERO; break; 4128 case Mips::T9: OpKind = MCK_GPR32NONZERO; break; 4129 case Mips::K0: OpKind = MCK_GPR32NONZERO; break; 4130 case Mips::K1: OpKind = MCK_GPR32NONZERO; break; 4131 case Mips::GP: OpKind = MCK_GP32; break; 4132 case Mips::SP: OpKind = MCK_CPUSPReg; break; 4133 case Mips::FP: OpKind = MCK_GPR32NONZERO; break; 4134 case Mips::RA: OpKind = MCK_CPURAReg; break; 4135 case Mips::ZERO_64: OpKind = MCK_Reg15; break; 4136 case Mips::AT_64: OpKind = MCK_Reg20; break; 4137 case Mips::V0_64: OpKind = MCK_Reg26; break; 4138 case Mips::V1_64: OpKind = MCK_Reg26; break; 4139 case Mips::A0_64: OpKind = MCK_Reg23; break; 4140 case Mips::A1_64: OpKind = MCK_Reg23; break; 4141 case Mips::A2_64: OpKind = MCK_Reg23; break; 4142 case Mips::A3_64: OpKind = MCK_Reg23; break; 4143 case Mips::T0_64: OpKind = MCK_Reg20; break; 4144 case Mips::T1_64: OpKind = MCK_Reg20; break; 4145 case Mips::T2_64: OpKind = MCK_Reg20; break; 4146 case Mips::T3_64: OpKind = MCK_Reg20; break; 4147 case Mips::T4_64: OpKind = MCK_Reg20; break; 4148 case Mips::T5_64: OpKind = MCK_Reg20; break; 4149 case Mips::T6_64: OpKind = MCK_Reg20; break; 4150 case Mips::T7_64: OpKind = MCK_Reg20; break; 4151 case Mips::S0_64: OpKind = MCK_Reg24; break; 4152 case Mips::S1_64: OpKind = MCK_Reg26; break; 4153 case Mips::S2_64: OpKind = MCK_Reg25; break; 4154 case Mips::S3_64: OpKind = MCK_Reg25; break; 4155 case Mips::S4_64: OpKind = MCK_Reg25; break; 4156 case Mips::S5_64: OpKind = MCK_Reg20; break; 4157 case Mips::S6_64: OpKind = MCK_Reg20; break; 4158 case Mips::S7_64: OpKind = MCK_Reg20; break; 4159 case Mips::T8_64: OpKind = MCK_Reg20; break; 4160 case Mips::T9_64: OpKind = MCK_Reg20; break; 4161 case Mips::K0_64: OpKind = MCK_Reg20; break; 4162 case Mips::K1_64: OpKind = MCK_Reg20; break; 4163 case Mips::GP_64: OpKind = MCK_GP64; break; 4164 case Mips::SP_64: OpKind = MCK_SP64; break; 4165 case Mips::FP_64: OpKind = MCK_Reg20; break; 4166 case Mips::RA_64: OpKind = MCK_Reg29; break; 4167 case Mips::F0: OpKind = MCK_FGR32; break; 4168 case Mips::F1: OpKind = MCK_Reg31; break; 4169 case Mips::F2: OpKind = MCK_FGR32; break; 4170 case Mips::F3: OpKind = MCK_Reg31; break; 4171 case Mips::F4: OpKind = MCK_FGR32; break; 4172 case Mips::F5: OpKind = MCK_Reg31; break; 4173 case Mips::F6: OpKind = MCK_FGR32; break; 4174 case Mips::F7: OpKind = MCK_Reg31; break; 4175 case Mips::F8: OpKind = MCK_FGR32; break; 4176 case Mips::F9: OpKind = MCK_Reg31; break; 4177 case Mips::F10: OpKind = MCK_FGR32; break; 4178 case Mips::F11: OpKind = MCK_Reg31; break; 4179 case Mips::F12: OpKind = MCK_FGR32; break; 4180 case Mips::F13: OpKind = MCK_Reg31; break; 4181 case Mips::F14: OpKind = MCK_FGR32; break; 4182 case Mips::F15: OpKind = MCK_Reg31; break; 4183 case Mips::F16: OpKind = MCK_FGR32; break; 4184 case Mips::F17: OpKind = MCK_Reg31; break; 4185 case Mips::F18: OpKind = MCK_FGR32; break; 4186 case Mips::F19: OpKind = MCK_Reg31; break; 4187 case Mips::F20: OpKind = MCK_FGR32; break; 4188 case Mips::F21: OpKind = MCK_Reg31; break; 4189 case Mips::F22: OpKind = MCK_FGR32; break; 4190 case Mips::F23: OpKind = MCK_Reg31; break; 4191 case Mips::F24: OpKind = MCK_FGR32; break; 4192 case Mips::F25: OpKind = MCK_Reg31; break; 4193 case Mips::F26: OpKind = MCK_FGR32; break; 4194 case Mips::F27: OpKind = MCK_Reg31; break; 4195 case Mips::F28: OpKind = MCK_FGR32; break; 4196 case Mips::F29: OpKind = MCK_Reg31; break; 4197 case Mips::F30: OpKind = MCK_FGR32; break; 4198 case Mips::F31: OpKind = MCK_Reg31; break; 4199 case Mips::F_HI0: OpKind = MCK_FGRH32; break; 4200 case Mips::F_HI1: OpKind = MCK_Reg34; break; 4201 case Mips::F_HI2: OpKind = MCK_FGRH32; break; 4202 case Mips::F_HI3: OpKind = MCK_Reg34; break; 4203 case Mips::F_HI4: OpKind = MCK_FGRH32; break; 4204 case Mips::F_HI5: OpKind = MCK_Reg34; break; 4205 case Mips::F_HI6: OpKind = MCK_FGRH32; break; 4206 case Mips::F_HI7: OpKind = MCK_Reg34; break; 4207 case Mips::F_HI8: OpKind = MCK_FGRH32; break; 4208 case Mips::F_HI9: OpKind = MCK_Reg34; break; 4209 case Mips::F_HI10: OpKind = MCK_FGRH32; break; 4210 case Mips::F_HI11: OpKind = MCK_Reg34; break; 4211 case Mips::F_HI12: OpKind = MCK_FGRH32; break; 4212 case Mips::F_HI13: OpKind = MCK_Reg34; break; 4213 case Mips::F_HI14: OpKind = MCK_FGRH32; break; 4214 case Mips::F_HI15: OpKind = MCK_Reg34; break; 4215 case Mips::F_HI16: OpKind = MCK_FGRH32; break; 4216 case Mips::F_HI17: OpKind = MCK_Reg34; break; 4217 case Mips::F_HI18: OpKind = MCK_FGRH32; break; 4218 case Mips::F_HI19: OpKind = MCK_Reg34; break; 4219 case Mips::F_HI20: OpKind = MCK_FGRH32; break; 4220 case Mips::F_HI21: OpKind = MCK_Reg34; break; 4221 case Mips::F_HI22: OpKind = MCK_FGRH32; break; 4222 case Mips::F_HI23: OpKind = MCK_Reg34; break; 4223 case Mips::F_HI24: OpKind = MCK_FGRH32; break; 4224 case Mips::F_HI25: OpKind = MCK_Reg34; break; 4225 case Mips::F_HI26: OpKind = MCK_FGRH32; break; 4226 case Mips::F_HI27: OpKind = MCK_Reg34; break; 4227 case Mips::F_HI28: OpKind = MCK_FGRH32; break; 4228 case Mips::F_HI29: OpKind = MCK_Reg34; break; 4229 case Mips::F_HI30: OpKind = MCK_FGRH32; break; 4230 case Mips::F_HI31: OpKind = MCK_Reg34; break; 4231 case Mips::D0: OpKind = MCK_AFGR64; break; 4232 case Mips::D1: OpKind = MCK_Reg36; break; 4233 case Mips::D2: OpKind = MCK_AFGR64; break; 4234 case Mips::D3: OpKind = MCK_Reg36; break; 4235 case Mips::D4: OpKind = MCK_AFGR64; break; 4236 case Mips::D5: OpKind = MCK_Reg36; break; 4237 case Mips::D6: OpKind = MCK_AFGR64; break; 4238 case Mips::D7: OpKind = MCK_Reg36; break; 4239 case Mips::D8: OpKind = MCK_AFGR64; break; 4240 case Mips::D9: OpKind = MCK_Reg36; break; 4241 case Mips::D10: OpKind = MCK_AFGR64; break; 4242 case Mips::D11: OpKind = MCK_Reg36; break; 4243 case Mips::D12: OpKind = MCK_AFGR64; break; 4244 case Mips::D13: OpKind = MCK_Reg36; break; 4245 case Mips::D14: OpKind = MCK_AFGR64; break; 4246 case Mips::D15: OpKind = MCK_Reg36; break; 4247 case Mips::D0_64: OpKind = MCK_FGR64; break; 4248 case Mips::D1_64: OpKind = MCK_Reg39; break; 4249 case Mips::D2_64: OpKind = MCK_FGR64; break; 4250 case Mips::D3_64: OpKind = MCK_Reg39; break; 4251 case Mips::D4_64: OpKind = MCK_FGR64; break; 4252 case Mips::D5_64: OpKind = MCK_Reg39; break; 4253 case Mips::D6_64: OpKind = MCK_FGR64; break; 4254 case Mips::D7_64: OpKind = MCK_Reg39; break; 4255 case Mips::D8_64: OpKind = MCK_FGR64; break; 4256 case Mips::D9_64: OpKind = MCK_Reg39; break; 4257 case Mips::D10_64: OpKind = MCK_FGR64; break; 4258 case Mips::D11_64: OpKind = MCK_Reg39; break; 4259 case Mips::D12_64: OpKind = MCK_FGR64; break; 4260 case Mips::D13_64: OpKind = MCK_Reg39; break; 4261 case Mips::D14_64: OpKind = MCK_FGR64; break; 4262 case Mips::D15_64: OpKind = MCK_Reg39; break; 4263 case Mips::D16_64: OpKind = MCK_FGR64; break; 4264 case Mips::D17_64: OpKind = MCK_Reg39; break; 4265 case Mips::D18_64: OpKind = MCK_FGR64; break; 4266 case Mips::D19_64: OpKind = MCK_Reg39; break; 4267 case Mips::D20_64: OpKind = MCK_FGR64; break; 4268 case Mips::D21_64: OpKind = MCK_Reg39; break; 4269 case Mips::D22_64: OpKind = MCK_FGR64; break; 4270 case Mips::D23_64: OpKind = MCK_Reg39; break; 4271 case Mips::D24_64: OpKind = MCK_FGR64; break; 4272 case Mips::D25_64: OpKind = MCK_Reg39; break; 4273 case Mips::D26_64: OpKind = MCK_FGR64; break; 4274 case Mips::D27_64: OpKind = MCK_Reg39; break; 4275 case Mips::D28_64: OpKind = MCK_FGR64; break; 4276 case Mips::D29_64: OpKind = MCK_Reg39; break; 4277 case Mips::D30_64: OpKind = MCK_FGR64; break; 4278 case Mips::D31_64: OpKind = MCK_Reg39; break; 4279 case Mips::W0: OpKind = MCK_MSA128WEvens; break; 4280 case Mips::W1: OpKind = MCK_Reg42; break; 4281 case Mips::W2: OpKind = MCK_MSA128WEvens; break; 4282 case Mips::W3: OpKind = MCK_Reg42; break; 4283 case Mips::W4: OpKind = MCK_MSA128WEvens; break; 4284 case Mips::W5: OpKind = MCK_Reg42; break; 4285 case Mips::W6: OpKind = MCK_MSA128WEvens; break; 4286 case Mips::W7: OpKind = MCK_Reg42; break; 4287 case Mips::W8: OpKind = MCK_MSA128WEvens; break; 4288 case Mips::W9: OpKind = MCK_Reg42; break; 4289 case Mips::W10: OpKind = MCK_MSA128WEvens; break; 4290 case Mips::W11: OpKind = MCK_Reg42; break; 4291 case Mips::W12: OpKind = MCK_MSA128WEvens; break; 4292 case Mips::W13: OpKind = MCK_Reg42; break; 4293 case Mips::W14: OpKind = MCK_MSA128WEvens; break; 4294 case Mips::W15: OpKind = MCK_Reg42; break; 4295 case Mips::W16: OpKind = MCK_MSA128WEvens; break; 4296 case Mips::W17: OpKind = MCK_Reg42; break; 4297 case Mips::W18: OpKind = MCK_MSA128WEvens; break; 4298 case Mips::W19: OpKind = MCK_Reg42; break; 4299 case Mips::W20: OpKind = MCK_MSA128WEvens; break; 4300 case Mips::W21: OpKind = MCK_Reg42; break; 4301 case Mips::W22: OpKind = MCK_MSA128WEvens; break; 4302 case Mips::W23: OpKind = MCK_Reg42; break; 4303 case Mips::W24: OpKind = MCK_MSA128WEvens; break; 4304 case Mips::W25: OpKind = MCK_Reg42; break; 4305 case Mips::W26: OpKind = MCK_MSA128WEvens; break; 4306 case Mips::W27: OpKind = MCK_Reg42; break; 4307 case Mips::W28: OpKind = MCK_MSA128WEvens; break; 4308 case Mips::W29: OpKind = MCK_Reg42; break; 4309 case Mips::W30: OpKind = MCK_MSA128WEvens; break; 4310 case Mips::W31: OpKind = MCK_Reg42; break; 4311 case Mips::HI0: OpKind = MCK_HI32; break; 4312 case Mips::HI1: OpKind = MCK_HI32DSP; break; 4313 case Mips::HI2: OpKind = MCK_HI32DSP; break; 4314 case Mips::HI3: OpKind = MCK_HI32DSP; break; 4315 case Mips::LO0: OpKind = MCK_LO32; break; 4316 case Mips::LO1: OpKind = MCK_LO32DSP; break; 4317 case Mips::LO2: OpKind = MCK_LO32DSP; break; 4318 case Mips::LO3: OpKind = MCK_LO32DSP; break; 4319 case Mips::HI0_64: OpKind = MCK_HI64; break; 4320 case Mips::LO0_64: OpKind = MCK_LO64; break; 4321 case Mips::FCR0: OpKind = MCK_CCR; break; 4322 case Mips::FCR1: OpKind = MCK_CCR; break; 4323 case Mips::FCR2: OpKind = MCK_CCR; break; 4324 case Mips::FCR3: OpKind = MCK_CCR; break; 4325 case Mips::FCR4: OpKind = MCK_CCR; break; 4326 case Mips::FCR5: OpKind = MCK_CCR; break; 4327 case Mips::FCR6: OpKind = MCK_CCR; break; 4328 case Mips::FCR7: OpKind = MCK_CCR; break; 4329 case Mips::FCR8: OpKind = MCK_CCR; break; 4330 case Mips::FCR9: OpKind = MCK_CCR; break; 4331 case Mips::FCR10: OpKind = MCK_CCR; break; 4332 case Mips::FCR11: OpKind = MCK_CCR; break; 4333 case Mips::FCR12: OpKind = MCK_CCR; break; 4334 case Mips::FCR13: OpKind = MCK_CCR; break; 4335 case Mips::FCR14: OpKind = MCK_CCR; break; 4336 case Mips::FCR15: OpKind = MCK_CCR; break; 4337 case Mips::FCR16: OpKind = MCK_CCR; break; 4338 case Mips::FCR17: OpKind = MCK_CCR; break; 4339 case Mips::FCR18: OpKind = MCK_CCR; break; 4340 case Mips::FCR19: OpKind = MCK_CCR; break; 4341 case Mips::FCR20: OpKind = MCK_CCR; break; 4342 case Mips::FCR21: OpKind = MCK_CCR; break; 4343 case Mips::FCR22: OpKind = MCK_CCR; break; 4344 case Mips::FCR23: OpKind = MCK_CCR; break; 4345 case Mips::FCR24: OpKind = MCK_CCR; break; 4346 case Mips::FCR25: OpKind = MCK_CCR; break; 4347 case Mips::FCR26: OpKind = MCK_CCR; break; 4348 case Mips::FCR27: OpKind = MCK_CCR; break; 4349 case Mips::FCR28: OpKind = MCK_CCR; break; 4350 case Mips::FCR29: OpKind = MCK_CCR; break; 4351 case Mips::FCR30: OpKind = MCK_CCR; break; 4352 case Mips::FCR31: OpKind = MCK_CCR; break; 4353 case Mips::FCC0: OpKind = MCK_FCC; break; 4354 case Mips::FCC1: OpKind = MCK_FCC; break; 4355 case Mips::FCC2: OpKind = MCK_FCC; break; 4356 case Mips::FCC3: OpKind = MCK_FCC; break; 4357 case Mips::FCC4: OpKind = MCK_FCC; break; 4358 case Mips::FCC5: OpKind = MCK_FCC; break; 4359 case Mips::FCC6: OpKind = MCK_FCC; break; 4360 case Mips::FCC7: OpKind = MCK_FCC; break; 4361 case Mips::COP00: OpKind = MCK_COP0; break; 4362 case Mips::COP01: OpKind = MCK_COP0; break; 4363 case Mips::COP02: OpKind = MCK_COP0; break; 4364 case Mips::COP03: OpKind = MCK_COP0; break; 4365 case Mips::COP04: OpKind = MCK_COP0; break; 4366 case Mips::COP05: OpKind = MCK_COP0; break; 4367 case Mips::COP06: OpKind = MCK_COP0; break; 4368 case Mips::COP07: OpKind = MCK_COP0; break; 4369 case Mips::COP08: OpKind = MCK_COP0; break; 4370 case Mips::COP09: OpKind = MCK_COP0; break; 4371 case Mips::COP010: OpKind = MCK_COP0; break; 4372 case Mips::COP011: OpKind = MCK_COP0; break; 4373 case Mips::COP012: OpKind = MCK_COP0; break; 4374 case Mips::COP013: OpKind = MCK_COP0; break; 4375 case Mips::COP014: OpKind = MCK_COP0; break; 4376 case Mips::COP015: OpKind = MCK_COP0; break; 4377 case Mips::COP016: OpKind = MCK_COP0; break; 4378 case Mips::COP017: OpKind = MCK_COP0; break; 4379 case Mips::COP018: OpKind = MCK_COP0; break; 4380 case Mips::COP019: OpKind = MCK_COP0; break; 4381 case Mips::COP020: OpKind = MCK_COP0; break; 4382 case Mips::COP021: OpKind = MCK_COP0; break; 4383 case Mips::COP022: OpKind = MCK_COP0; break; 4384 case Mips::COP023: OpKind = MCK_COP0; break; 4385 case Mips::COP024: OpKind = MCK_COP0; break; 4386 case Mips::COP025: OpKind = MCK_COP0; break; 4387 case Mips::COP026: OpKind = MCK_COP0; break; 4388 case Mips::COP027: OpKind = MCK_COP0; break; 4389 case Mips::COP028: OpKind = MCK_COP0; break; 4390 case Mips::COP029: OpKind = MCK_COP0; break; 4391 case Mips::COP030: OpKind = MCK_COP0; break; 4392 case Mips::COP031: OpKind = MCK_COP0; break; 4393 case Mips::COP20: OpKind = MCK_COP2; break; 4394 case Mips::COP21: OpKind = MCK_COP2; break; 4395 case Mips::COP22: OpKind = MCK_COP2; break; 4396 case Mips::COP23: OpKind = MCK_COP2; break; 4397 case Mips::COP24: OpKind = MCK_COP2; break; 4398 case Mips::COP25: OpKind = MCK_COP2; break; 4399 case Mips::COP26: OpKind = MCK_COP2; break; 4400 case Mips::COP27: OpKind = MCK_COP2; break; 4401 case Mips::COP28: OpKind = MCK_COP2; break; 4402 case Mips::COP29: OpKind = MCK_COP2; break; 4403 case Mips::COP210: OpKind = MCK_COP2; break; 4404 case Mips::COP211: OpKind = MCK_COP2; break; 4405 case Mips::COP212: OpKind = MCK_COP2; break; 4406 case Mips::COP213: OpKind = MCK_COP2; break; 4407 case Mips::COP214: OpKind = MCK_COP2; break; 4408 case Mips::COP215: OpKind = MCK_COP2; break; 4409 case Mips::COP216: OpKind = MCK_COP2; break; 4410 case Mips::COP217: OpKind = MCK_COP2; break; 4411 case Mips::COP218: OpKind = MCK_COP2; break; 4412 case Mips::COP219: OpKind = MCK_COP2; break; 4413 case Mips::COP220: OpKind = MCK_COP2; break; 4414 case Mips::COP221: OpKind = MCK_COP2; break; 4415 case Mips::COP222: OpKind = MCK_COP2; break; 4416 case Mips::COP223: OpKind = MCK_COP2; break; 4417 case Mips::COP224: OpKind = MCK_COP2; break; 4418 case Mips::COP225: OpKind = MCK_COP2; break; 4419 case Mips::COP226: OpKind = MCK_COP2; break; 4420 case Mips::COP227: OpKind = MCK_COP2; break; 4421 case Mips::COP228: OpKind = MCK_COP2; break; 4422 case Mips::COP229: OpKind = MCK_COP2; break; 4423 case Mips::COP230: OpKind = MCK_COP2; break; 4424 case Mips::COP231: OpKind = MCK_COP2; break; 4425 case Mips::COP30: OpKind = MCK_COP3; break; 4426 case Mips::COP31: OpKind = MCK_COP3; break; 4427 case Mips::COP32: OpKind = MCK_COP3; break; 4428 case Mips::COP33: OpKind = MCK_COP3; break; 4429 case Mips::COP34: OpKind = MCK_COP3; break; 4430 case Mips::COP35: OpKind = MCK_COP3; break; 4431 case Mips::COP36: OpKind = MCK_COP3; break; 4432 case Mips::COP37: OpKind = MCK_COP3; break; 4433 case Mips::COP38: OpKind = MCK_COP3; break; 4434 case Mips::COP39: OpKind = MCK_COP3; break; 4435 case Mips::COP310: OpKind = MCK_COP3; break; 4436 case Mips::COP311: OpKind = MCK_COP3; break; 4437 case Mips::COP312: OpKind = MCK_COP3; break; 4438 case Mips::COP313: OpKind = MCK_COP3; break; 4439 case Mips::COP314: OpKind = MCK_COP3; break; 4440 case Mips::COP315: OpKind = MCK_COP3; break; 4441 case Mips::COP316: OpKind = MCK_COP3; break; 4442 case Mips::COP317: OpKind = MCK_COP3; break; 4443 case Mips::COP318: OpKind = MCK_COP3; break; 4444 case Mips::COP319: OpKind = MCK_COP3; break; 4445 case Mips::COP320: OpKind = MCK_COP3; break; 4446 case Mips::COP321: OpKind = MCK_COP3; break; 4447 case Mips::COP322: OpKind = MCK_COP3; break; 4448 case Mips::COP323: OpKind = MCK_COP3; break; 4449 case Mips::COP324: OpKind = MCK_COP3; break; 4450 case Mips::COP325: OpKind = MCK_COP3; break; 4451 case Mips::COP326: OpKind = MCK_COP3; break; 4452 case Mips::COP327: OpKind = MCK_COP3; break; 4453 case Mips::COP328: OpKind = MCK_COP3; break; 4454 case Mips::COP329: OpKind = MCK_COP3; break; 4455 case Mips::COP330: OpKind = MCK_COP3; break; 4456 case Mips::COP331: OpKind = MCK_COP3; break; 4457 case Mips::PC: OpKind = MCK_PC; break; 4458 case Mips::HWR0: OpKind = MCK_HWRegs; break; 4459 case Mips::HWR1: OpKind = MCK_HWRegs; break; 4460 case Mips::HWR2: OpKind = MCK_HWRegs; break; 4461 case Mips::HWR3: OpKind = MCK_HWRegs; break; 4462 case Mips::HWR4: OpKind = MCK_HWRegs; break; 4463 case Mips::HWR5: OpKind = MCK_HWRegs; break; 4464 case Mips::HWR6: OpKind = MCK_HWRegs; break; 4465 case Mips::HWR7: OpKind = MCK_HWRegs; break; 4466 case Mips::HWR8: OpKind = MCK_HWRegs; break; 4467 case Mips::HWR9: OpKind = MCK_HWRegs; break; 4468 case Mips::HWR10: OpKind = MCK_HWRegs; break; 4469 case Mips::HWR11: OpKind = MCK_HWRegs; break; 4470 case Mips::HWR12: OpKind = MCK_HWRegs; break; 4471 case Mips::HWR13: OpKind = MCK_HWRegs; break; 4472 case Mips::HWR14: OpKind = MCK_HWRegs; break; 4473 case Mips::HWR15: OpKind = MCK_HWRegs; break; 4474 case Mips::HWR16: OpKind = MCK_HWRegs; break; 4475 case Mips::HWR17: OpKind = MCK_HWRegs; break; 4476 case Mips::HWR18: OpKind = MCK_HWRegs; break; 4477 case Mips::HWR19: OpKind = MCK_HWRegs; break; 4478 case Mips::HWR20: OpKind = MCK_HWRegs; break; 4479 case Mips::HWR21: OpKind = MCK_HWRegs; break; 4480 case Mips::HWR22: OpKind = MCK_HWRegs; break; 4481 case Mips::HWR23: OpKind = MCK_HWRegs; break; 4482 case Mips::HWR24: OpKind = MCK_HWRegs; break; 4483 case Mips::HWR25: OpKind = MCK_HWRegs; break; 4484 case Mips::HWR26: OpKind = MCK_HWRegs; break; 4485 case Mips::HWR27: OpKind = MCK_HWRegs; break; 4486 case Mips::HWR28: OpKind = MCK_HWRegs; break; 4487 case Mips::HWR29: OpKind = MCK_HWRegs; break; 4488 case Mips::HWR30: OpKind = MCK_HWRegs; break; 4489 case Mips::HWR31: OpKind = MCK_HWRegs; break; 4490 case Mips::AC0: OpKind = MCK_ACC64; break; 4491 case Mips::AC1: OpKind = MCK_ACC64DSP; break; 4492 case Mips::AC2: OpKind = MCK_ACC64DSP; break; 4493 case Mips::AC3: OpKind = MCK_ACC64DSP; break; 4494 case Mips::AC0_64: OpKind = MCK_ACC128; break; 4495 case Mips::DSPCCond: OpKind = MCK_DSPCC; break; 4496 case Mips::MSAIR: OpKind = MCK_MSACtrl; break; 4497 case Mips::MSACSR: OpKind = MCK_MSACtrl; break; 4498 case Mips::MSAAccess: OpKind = MCK_MSACtrl; break; 4499 case Mips::MSASave: OpKind = MCK_MSACtrl; break; 4500 case Mips::MSAModify: OpKind = MCK_MSACtrl; break; 4501 case Mips::MSARequest: OpKind = MCK_MSACtrl; break; 4502 case Mips::MSAMap: OpKind = MCK_MSACtrl; break; 4503 case Mips::MSAUnmap: OpKind = MCK_MSACtrl; break; 4504 case Mips::MPL0: OpKind = MCK_OCTEON_MPL; break; 4505 case Mips::MPL1: OpKind = MCK_OCTEON_MPL; break; 4506 case Mips::MPL2: OpKind = MCK_OCTEON_MPL; break; 4507 case Mips::P0: OpKind = MCK_OCTEON_P; break; 4508 case Mips::P1: OpKind = MCK_OCTEON_P; break; 4509 case Mips::P2: OpKind = MCK_OCTEON_P; break; 4510 } 4511 return isSubclass(OpKind, Kind) ? (unsigned)MCTargetAsmParser::Match_Success : 4512 getDiagKindFromRegisterClass(Kind); 4513 } 4514 4515 if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER) 4516 return getDiagKindFromRegisterClass(Kind); 4517 4518 return MCTargetAsmParser::Match_InvalidOperand; 4519} 4520 4521#ifndef NDEBUG 4522const char *getMatchClassName(MatchClassKind Kind) { 4523 switch (Kind) { 4524 case InvalidMatchClass: return "InvalidMatchClass"; 4525 case OptionalMatchClass: return "OptionalMatchClass"; 4526 case MCK__35_: return "MCK__35_"; 4527 case MCK__40_: return "MCK__40_"; 4528 case MCK__41_: return "MCK__41_"; 4529 case MCK_0: return "MCK_0"; 4530 case MCK_16: return "MCK_16"; 4531 case MCK__91_: return "MCK__91_"; 4532 case MCK__93_: return "MCK__93_"; 4533 case MCK_bit: return "MCK_bit"; 4534 case MCK_inst: return "MCK_inst"; 4535 case MCK_Reg15: return "MCK_Reg15"; 4536 case MCK_Reg29: return "MCK_Reg29"; 4537 case MCK_ACC128: return "MCK_ACC128"; 4538 case MCK_ACC64: return "MCK_ACC64"; 4539 case MCK_CPURAReg: return "MCK_CPURAReg"; 4540 case MCK_CPUSPReg: return "MCK_CPUSPReg"; 4541 case MCK_DSPCC: return "MCK_DSPCC"; 4542 case MCK_GP32: return "MCK_GP32"; 4543 case MCK_GP64: return "MCK_GP64"; 4544 case MCK_GPR32ZERO: return "MCK_GPR32ZERO"; 4545 case MCK_HI32: return "MCK_HI32"; 4546 case MCK_HI64: return "MCK_HI64"; 4547 case MCK_LO32: return "MCK_LO32"; 4548 case MCK_LO64: return "MCK_LO64"; 4549 case MCK_PC: return "MCK_PC"; 4550 case MCK_SP64: return "MCK_SP64"; 4551 case MCK_Reg11: return "MCK_Reg11"; 4552 case MCK_Reg26: return "MCK_Reg26"; 4553 case MCK_OCTEON_MPL: return "MCK_OCTEON_MPL"; 4554 case MCK_OCTEON_P: return "MCK_OCTEON_P"; 4555 case MCK_Reg4: return "MCK_Reg4"; 4556 case MCK_Reg9: return "MCK_Reg9"; 4557 case MCK_Reg19: return "MCK_Reg19"; 4558 case MCK_Reg24: return "MCK_Reg24"; 4559 case MCK_ACC64DSP: return "MCK_ACC64DSP"; 4560 case MCK_HI32DSP: return "MCK_HI32DSP"; 4561 case MCK_LO32DSP: return "MCK_LO32DSP"; 4562 case MCK_Reg8: return "MCK_Reg8"; 4563 case MCK_Reg10: return "MCK_Reg10"; 4564 case MCK_Reg23: return "MCK_Reg23"; 4565 case MCK_Reg25: return "MCK_Reg25"; 4566 case MCK_Reg17: return "MCK_Reg17"; 4567 case MCK_Reg18: return "MCK_Reg18"; 4568 case MCK_Reg21: return "MCK_Reg21"; 4569 case MCK_Reg36: return "MCK_Reg36"; 4570 case MCK_CPU16Regs: return "MCK_CPU16Regs"; 4571 case MCK_FCC: return "MCK_FCC"; 4572 case MCK_GPRMM16MoveP: return "MCK_GPRMM16MoveP"; 4573 case MCK_GPRMM16Zero: return "MCK_GPRMM16Zero"; 4574 case MCK_MSACtrl: return "MCK_MSACtrl"; 4575 case MCK_Reg22: return "MCK_Reg22"; 4576 case MCK_CPU16RegsPlusSP: return "MCK_CPU16RegsPlusSP"; 4577 case MCK_Reg31: return "MCK_Reg31"; 4578 case MCK_Reg34: return "MCK_Reg34"; 4579 case MCK_Reg39: return "MCK_Reg39"; 4580 case MCK_Reg42: return "MCK_Reg42"; 4581 case MCK_AFGR64: return "MCK_AFGR64"; 4582 case MCK_MSA128WEvens: return "MCK_MSA128WEvens"; 4583 case MCK_Reg37: return "MCK_Reg37"; 4584 case MCK_Reg20: return "MCK_Reg20"; 4585 case MCK_GPR32NONZERO: return "MCK_GPR32NONZERO"; 4586 case MCK_CCR: return "MCK_CCR"; 4587 case MCK_COP0: return "MCK_COP0"; 4588 case MCK_COP2: return "MCK_COP2"; 4589 case MCK_COP3: return "MCK_COP3"; 4590 case MCK_DSPR: return "MCK_DSPR"; 4591 case MCK_FGR32: return "MCK_FGR32"; 4592 case MCK_FGR64: return "MCK_FGR64"; 4593 case MCK_FGRH32: return "MCK_FGRH32"; 4594 case MCK_GPR64: return "MCK_GPR64"; 4595 case MCK_HWRegs: return "MCK_HWRegs"; 4596 case MCK_MSA128F16: return "MCK_MSA128F16"; 4597 case MCK_OddSP: return "MCK_OddSP"; 4598 case MCK_ACC64DSPAsmReg: return "MCK_ACC64DSPAsmReg"; 4599 case MCK_AFGR64AsmReg: return "MCK_AFGR64AsmReg"; 4600 case MCK_CCRAsmReg: return "MCK_CCRAsmReg"; 4601 case MCK_COP0AsmReg: return "MCK_COP0AsmReg"; 4602 case MCK_COP2AsmReg: return "MCK_COP2AsmReg"; 4603 case MCK_COP3AsmReg: return "MCK_COP3AsmReg"; 4604 case MCK_FCCAsmReg: return "MCK_FCCAsmReg"; 4605 case MCK_FGR32AsmReg: return "MCK_FGR32AsmReg"; 4606 case MCK_FGR64AsmReg: return "MCK_FGR64AsmReg"; 4607 case MCK_FGRH32AsmReg: return "MCK_FGRH32AsmReg"; 4608 case MCK_GPR32AsmReg: return "MCK_GPR32AsmReg"; 4609 case MCK_GPR32NonZeroAsmReg: return "MCK_GPR32NonZeroAsmReg"; 4610 case MCK_GPR32ZeroAsmReg: return "MCK_GPR32ZeroAsmReg"; 4611 case MCK_GPR64AsmReg: return "MCK_GPR64AsmReg"; 4612 case MCK_GPRMM16AsmReg: return "MCK_GPRMM16AsmReg"; 4613 case MCK_GPRMM16AsmRegMoveP: return "MCK_GPRMM16AsmRegMoveP"; 4614 case MCK_GPRMM16AsmRegZero: return "MCK_GPRMM16AsmRegZero"; 4615 case MCK_HI32DSPAsmReg: return "MCK_HI32DSPAsmReg"; 4616 case MCK_HWRegsAsmReg: return "MCK_HWRegsAsmReg"; 4617 case MCK_Imm: return "MCK_Imm"; 4618 case MCK_LO32DSPAsmReg: return "MCK_LO32DSPAsmReg"; 4619 case MCK_MSA128AsmReg: return "MCK_MSA128AsmReg"; 4620 case MCK_MSACtrlAsmReg: return "MCK_MSACtrlAsmReg"; 4621 case MCK_MicroMipsMemGP: return "MCK_MicroMipsMemGP"; 4622 case MCK_MicroMipsMem: return "MCK_MicroMipsMem"; 4623 case MCK_MicroMipsMemSP: return "MCK_MicroMipsMemSP"; 4624 case MCK_InvNum: return "MCK_InvNum"; 4625 case MCK_JumpTarget: return "MCK_JumpTarget"; 4626 case MCK_MemOffsetSimm10: return "MCK_MemOffsetSimm10"; 4627 case MCK_MemOffsetSimm10_1: return "MCK_MemOffsetSimm10_1"; 4628 case MCK_MemOffsetSimm10_2: return "MCK_MemOffsetSimm10_2"; 4629 case MCK_MemOffsetSimm10_3: return "MCK_MemOffsetSimm10_3"; 4630 case MCK_MemOffsetSimm11: return "MCK_MemOffsetSimm11"; 4631 case MCK_MemOffsetSimm12: return "MCK_MemOffsetSimm12"; 4632 case MCK_MemOffsetSimm16: return "MCK_MemOffsetSimm16"; 4633 case MCK_MemOffsetSimm9: return "MCK_MemOffsetSimm9"; 4634 case MCK_MemOffsetSimmPtr: return "MCK_MemOffsetSimmPtr"; 4635 case MCK_MemOffsetUimm4: return "MCK_MemOffsetUimm4"; 4636 case MCK_Mem: return "MCK_Mem"; 4637 case MCK_MovePRegPair: return "MCK_MovePRegPair"; 4638 case MCK_RegList16: return "MCK_RegList16"; 4639 case MCK_RegList: return "MCK_RegList"; 4640 case MCK_Simm19_Lsl2: return "MCK_Simm19_Lsl2"; 4641 case MCK_StrictlyAFGR64AsmReg: return "MCK_StrictlyAFGR64AsmReg"; 4642 case MCK_StrictlyFGR32AsmReg: return "MCK_StrictlyFGR32AsmReg"; 4643 case MCK_StrictlyFGR64AsmReg: return "MCK_StrictlyFGR64AsmReg"; 4644 case MCK_ConstantImmz: return "MCK_ConstantImmz"; 4645 case MCK_ConstantUImm1_0: return "MCK_ConstantUImm1_0"; 4646 case MCK_ConstantUImm2_0: return "MCK_ConstantUImm2_0"; 4647 case MCK_ConstantUImm2_1: return "MCK_ConstantUImm2_1"; 4648 case MCK_ConstantUImm3_0: return "MCK_ConstantUImm3_0"; 4649 case MCK_ConstantSImm4_0: return "MCK_ConstantSImm4_0"; 4650 case MCK_ConstantUImm4_0: return "MCK_ConstantUImm4_0"; 4651 case MCK_ConstantSImm5_0: return "MCK_ConstantSImm5_0"; 4652 case MCK_ConstantUImm5_0: return "MCK_ConstantUImm5_0"; 4653 case MCK_ConstantUImm5_1: return "MCK_ConstantUImm5_1"; 4654 case MCK_ConstantUImm5_Plus1_Report_UImm6: return "MCK_ConstantUImm5_Plus1_Report_UImm6"; 4655 case MCK_ConstantUImm5_32_Norm: return "MCK_ConstantUImm5_32_Norm"; 4656 case MCK_ConstantUImm5_32: return "MCK_ConstantUImm5_32"; 4657 case MCK_ConstantUImm5_0_Report_UImm6: return "MCK_ConstantUImm5_0_Report_UImm6"; 4658 case MCK_ConstantUImm5_33: return "MCK_ConstantUImm5_33"; 4659 case MCK_ConstantUImmRange2_64: return "MCK_ConstantUImmRange2_64"; 4660 case MCK_UImm5Lsl2: return "MCK_UImm5Lsl2"; 4661 case MCK_ConstantSImm6_0: return "MCK_ConstantSImm6_0"; 4662 case MCK_ConstantUImm6_0: return "MCK_ConstantUImm6_0"; 4663 case MCK_UImm6Lsl2: return "MCK_UImm6Lsl2"; 4664 case MCK_ConstantUImm7_0: return "MCK_ConstantUImm7_0"; 4665 case MCK_UImm7_N1: return "MCK_UImm7_N1"; 4666 case MCK_ConstantUImm8_0: return "MCK_ConstantUImm8_0"; 4667 case MCK_SImm7Lsl2: return "MCK_SImm7Lsl2"; 4668 case MCK_ConstantSImm9_0: return "MCK_ConstantSImm9_0"; 4669 case MCK_ConstantSImm10_0: return "MCK_ConstantSImm10_0"; 4670 case MCK_ConstantUImm10_0: return "MCK_ConstantUImm10_0"; 4671 case MCK_SImm10Lsl1: return "MCK_SImm10Lsl1"; 4672 case MCK_ConstantSImm11_0: return "MCK_ConstantSImm11_0"; 4673 case MCK_SImm10Lsl2: return "MCK_SImm10Lsl2"; 4674 case MCK_SImm10Lsl3: return "MCK_SImm10Lsl3"; 4675 case MCK_SImm16: return "MCK_SImm16"; 4676 case MCK_SImm16_Relaxed: return "MCK_SImm16_Relaxed"; 4677 case MCK_UImm16_AltRelaxed: return "MCK_UImm16_AltRelaxed"; 4678 case MCK_UImm16: return "MCK_UImm16"; 4679 case MCK_SImm19Lsl2: return "MCK_SImm19Lsl2"; 4680 case MCK_UImm16_Relaxed: return "MCK_UImm16_Relaxed"; 4681 case MCK_ConstantUImm20_0: return "MCK_ConstantUImm20_0"; 4682 case MCK_ConstantUImm26_0: return "MCK_ConstantUImm26_0"; 4683 case MCK_SImm32: return "MCK_SImm32"; 4684 case MCK_SImm32_Relaxed: return "MCK_SImm32_Relaxed"; 4685 case MCK_UImm32_Coerced: return "MCK_UImm32_Coerced"; 4686 case NumMatchClassKinds: return "NumMatchClassKinds"; 4687 } 4688 llvm_unreachable("unhandled MatchClassKind!"); 4689} 4690 4691#endif // NDEBUG 4692uint64_t MipsAsmParser:: 4693ComputeAvailableFeatures(const FeatureBitset& FB) const { 4694 uint64_t Features = 0; 4695 if ((FB[Mips::FeatureMips2])) 4696 Features |= Feature_HasMips2; 4697 if ((FB[Mips::FeatureMips3_32])) 4698 Features |= Feature_HasMips3_32; 4699 if ((FB[Mips::FeatureMips3_32r2])) 4700 Features |= Feature_HasMips3_32r2; 4701 if ((FB[Mips::FeatureMips3])) 4702 Features |= Feature_HasMips3; 4703 if ((!FB[Mips::FeatureMips3])) 4704 Features |= Feature_NotMips3; 4705 if ((FB[Mips::FeatureMips4_32])) 4706 Features |= Feature_HasMips4_32; 4707 if ((!FB[Mips::FeatureMips4_32])) 4708 Features |= Feature_NotMips4_32; 4709 if ((FB[Mips::FeatureMips4_32r2])) 4710 Features |= Feature_HasMips4_32r2; 4711 if ((FB[Mips::FeatureMips5_32r2])) 4712 Features |= Feature_HasMips5_32r2; 4713 if ((FB[Mips::FeatureMips32])) 4714 Features |= Feature_HasMips32; 4715 if ((FB[Mips::FeatureMips32r2])) 4716 Features |= Feature_HasMips32r2; 4717 if ((FB[Mips::FeatureMips32r5])) 4718 Features |= Feature_HasMips32r5; 4719 if ((FB[Mips::FeatureMips32r6])) 4720 Features |= Feature_HasMips32r6; 4721 if ((!FB[Mips::FeatureMips32r6])) 4722 Features |= Feature_NotMips32r6; 4723 if ((FB[Mips::FeatureGP64Bit])) 4724 Features |= Feature_IsGP64bit; 4725 if ((!FB[Mips::FeatureGP64Bit])) 4726 Features |= Feature_IsGP32bit; 4727 if ((FB[Mips::FeaturePTR64Bit])) 4728 Features |= Feature_IsPTR64bit; 4729 if ((!FB[Mips::FeaturePTR64Bit])) 4730 Features |= Feature_IsPTR32bit; 4731 if ((FB[Mips::FeatureMips64])) 4732 Features |= Feature_HasMips64; 4733 if ((!FB[Mips::FeatureMips64])) 4734 Features |= Feature_NotMips64; 4735 if ((FB[Mips::FeatureMips64r2])) 4736 Features |= Feature_HasMips64r2; 4737 if ((FB[Mips::FeatureMips64r5])) 4738 Features |= Feature_HasMips64r5; 4739 if ((FB[Mips::FeatureMips64r6])) 4740 Features |= Feature_HasMips64r6; 4741 if ((!FB[Mips::FeatureMips64r6])) 4742 Features |= Feature_NotMips64r6; 4743 if ((FB[Mips::FeatureMips16])) 4744 Features |= Feature_InMips16Mode; 4745 if ((!FB[Mips::FeatureMips16])) 4746 Features |= Feature_NotInMips16Mode; 4747 if ((FB[Mips::FeatureCnMips])) 4748 Features |= Feature_HasCnMips; 4749 if ((!FB[Mips::FeatureCnMips])) 4750 Features |= Feature_NotCnMips; 4751 if ((FB[Mips::FeatureSym32])) 4752 Features |= Feature_IsSym32; 4753 if ((!FB[Mips::FeatureSym32])) 4754 Features |= Feature_IsSym64; 4755 if ((!FB[Mips::FeatureMips16])) 4756 Features |= Feature_HasStdEnc; 4757 if ((FB[Mips::FeatureMicroMips])) 4758 Features |= Feature_InMicroMips; 4759 if ((!FB[Mips::FeatureMicroMips])) 4760 Features |= Feature_NotInMicroMips; 4761 if ((FB[Mips::FeatureEVA])) 4762 Features |= Feature_HasEVA; 4763 if ((FB[Mips::FeatureMSA])) 4764 Features |= Feature_HasMSA; 4765 if ((!FB[Mips::FeatureMadd4])) 4766 Features |= Feature_HasMadd4; 4767 if ((FB[Mips::FeatureMT])) 4768 Features |= Feature_HasMT; 4769 if ((FB[Mips::FeatureUseIndirectJumpsHazard])) 4770 Features |= Feature_UseIndirectJumpsHazard; 4771 if ((!FB[Mips::FeatureUseIndirectJumpsHazard])) 4772 Features |= Feature_NoIndirectJumpGuards; 4773 if ((FB[Mips::FeatureCRC])) 4774 Features |= Feature_HasCRC; 4775 if ((FB[Mips::FeatureVirt])) 4776 Features |= Feature_HasVirt; 4777 if ((FB[Mips::FeatureGINV])) 4778 Features |= Feature_HasGINV; 4779 if ((FB[Mips::FeatureFP64Bit])) 4780 Features |= Feature_IsFP64bit; 4781 if ((!FB[Mips::FeatureFP64Bit])) 4782 Features |= Feature_NotFP64bit; 4783 if ((FB[Mips::FeatureSingleFloat])) 4784 Features |= Feature_IsSingleFloat; 4785 if ((!FB[Mips::FeatureSingleFloat])) 4786 Features |= Feature_IsNotSingleFloat; 4787 if ((!FB[Mips::FeatureSoftFloat])) 4788 Features |= Feature_IsNotSoftFloat; 4789 if ((FB[Mips::FeatureDSP])) 4790 Features |= Feature_HasDSP; 4791 if ((FB[Mips::FeatureDSPR2])) 4792 Features |= Feature_HasDSPR2; 4793 if ((FB[Mips::FeatureDSPR3])) 4794 Features |= Feature_HasDSPR3; 4795 return Features; 4796} 4797 4798static bool checkAsmTiedOperandConstraints(const MipsAsmParser&AsmParser, 4799 unsigned Kind, 4800 const OperandVector &Operands, 4801 uint64_t &ErrorInfo) { 4802 assert(Kind < CVT_NUM_SIGNATURES && "Invalid signature!"); 4803 const uint8_t *Converter = ConversionTable[Kind]; 4804 for (const uint8_t *p = Converter; *p; p+= 2) { 4805 switch (*p) { 4806 case CVT_Tied: { 4807 unsigned OpIdx = *(p+1); 4808 assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) - 4809 std::begin(TiedAsmOperandTable)) && 4810 "Tied operand not found"); 4811 unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1]; 4812 unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2]; 4813 if (OpndNum1 != OpndNum2) { 4814 auto &SrcOp1 = Operands[OpndNum1]; 4815 auto &SrcOp2 = Operands[OpndNum2]; 4816 if (SrcOp1->isReg() && SrcOp2->isReg()) { 4817 if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) { 4818 ErrorInfo = OpndNum2; 4819 return false; 4820 } 4821 } 4822 } 4823 break; 4824 } 4825 default: 4826 break; 4827 } 4828 } 4829 return true; 4830} 4831 4832static const char *const MnemonicTable = 4833 "\003abs\005abs.d\005abs.s\tabsq_s.ph\tabsq_s.qb\010absq_s.w\003add\005a" 4834 "dd.d\005add.s\007add_a.b\007add_a.d\007add_a.h\007add_a.w\004addi\005ad" 4835 "diu\007addiupc\taddiur1sp\007addiur2\007addius5\007addiusp\007addq.ph\t" 4836 "addq_s.ph\010addq_s.w\010addqh.ph\007addqh.w\naddqh_r.ph\taddqh_r.w\010" 4837 "adds_a.b\010adds_a.d\010adds_a.h\010adds_a.w\010adds_s.b\010adds_s.d\010" 4838 "adds_s.h\010adds_s.w\010adds_u.b\010adds_u.d\010adds_u.h\010adds_u.w\005" 4839 "addsc\004addu\007addu.ph\007addu.qb\006addu16\taddu_s.ph\taddu_s.qb\010" 4840 "adduh.qb\nadduh_r.qb\006addv.b\006addv.d\006addv.h\006addv.w\007addvi.b" 4841 "\007addvi.d\007addvi.h\007addvi.w\005addwc\005align\006aluipc\003and\005" 4842 "and.v\005and16\004andi\006andi.b\006andi16\006append\010asub_s.b\010asu" 4843 "b_s.d\010asub_s.h\010asub_s.w\010asub_u.b\010asub_u.d\010asub_u.h\010as" 4844 "ub_u.w\003aui\005auipc\007ave_s.b\007ave_s.d\007ave_s.h\007ave_s.w\007a" 4845 "ve_u.b\007ave_u.d\007ave_u.h\007ave_u.w\010aver_s.b\010aver_s.d\010aver" 4846 "_s.h\010aver_s.w\010aver_u.b\010aver_u.d\010aver_u.h\010aver_u.w\001b\003" 4847 "b16\005baddu\003bal\004balc\006balign\005bbit0\007bbit032\005bbit1\007b" 4848 "bit132\002bc\004bc16\006bc1eqz\007bc1eqzc\004bc1f\005bc1fl\006bc1nez\007" 4849 "bc1nezc\004bc1t\005bc1tl\006bc2eqz\007bc2eqzc\006bc2nez\007bc2nezc\006b" 4850 "clr.b\006bclr.d\006bclr.h\006bclr.w\007bclri.b\007bclri.d\007bclri.h\007" 4851 "bclri.w\003beq\004beqc\004beql\004beqz\006beqz16\007beqzalc\005beqzc\007" 4852 "beqzc16\005beqzl\003bge\004bgec\004bgel\004bgeu\005bgeuc\005bgeul\004bg" 4853 "ez\006bgezal\007bgezalc\007bgezall\007bgezals\005bgezc\005bgezl\003bgt\004" 4854 "bgtl\004bgtu\005bgtul\004bgtz\007bgtzalc\005bgtzc\005bgtzl\007binsl.b\007" 4855 "binsl.d\007binsl.h\007binsl.w\010binsli.b\010binsli.d\010binsli.h\010bi" 4856 "nsli.w\007binsr.b\007binsr.d\007binsr.h\007binsr.w\010binsri.b\010binsr" 4857 "i.d\010binsri.h\010binsri.w\006bitrev\007bitswap\003ble\004blel\004bleu" 4858 "\005bleul\004blez\007blezalc\005blezc\005blezl\003blt\004bltc\004bltl\004" 4859 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"d\tcmp.slt.s\ncmp.sueq.d\ncmp.sueq.s\ncmp.sule.d\ncmp.sule.s\ncmp.sult." 4884 "d\ncmp.sult.s\tcmp.sun.d\tcmp.sun.s\tcmp.ueq.d\tcmp.ueq.s\tcmp.ule.d\tc" 4885 "mp.ule.s\tcmp.ult.d\tcmp.ult.s\010cmp.un.d\010cmp.un.s\014cmpgdu.eq.qb\014" 4886 "cmpgdu.le.qb\014cmpgdu.lt.qb\013cmpgu.eq.qb\013cmpgu.le.qb\013cmpgu.lt." 4887 "qb\004cmpi\ncmpu.eq.qb\ncmpu.le.qb\ncmpu.lt.qb\010copy_s.b\010copy_s.d\010" 4888 "copy_s.h\010copy_s.w\010copy_u.b\010copy_u.h\010copy_u.w\006crc32b\007c" 4889 "rc32cb\007crc32cd\007crc32ch\007crc32cw\006crc32d\006crc32h\006crc32w\004" 4890 "ctc1\004ctc2\006ctcmsa\005cttc1\007cvt.d.l\007cvt.d.s\007cvt.d.w\007cvt" 4891 ".l.d\007cvt.l.s\007cvt.s.d\007cvt.s.l\007cvt.s.w\007cvt.w.d\007cvt.w.s\004" 4892 "dadd\005daddi\006daddiu\005daddu\004dahi\006dalign\004dati\004daui\010d" 4893 "bitswap\004dclo\004dclz\004ddiv\005ddivu\005deret\004dext\005dextm\005d" 4894 "extu\002di\004dins\005dinsm\005dinsu\003div\005div.d\005div.s\007div_s." 4895 "b\007div_s.d\007div_s.h\007div_s.w\007div_u.b\007div_u.d\007div_u.h\007" 4896 "div_u.w\004divu\003dla\003dli\004dlsa\005dmfc0\005dmfc1\005dmfc2\006dmf" 4897 "gc0\004dmod\005dmodu\003dmt\005dmtc0\005dmtc1\005dmtc2\006dmtgc0\004dmu" 4898 "h\005dmuhu\004dmul\005dmulo\006dmulou\005dmult\006dmultu\005dmulu\004dn" 4899 "eg\005dnegu\010dotp_s.d\010dotp_s.h\010dotp_s.w\010dotp_u.d\010dotp_u.h" 4900 "\010dotp_u.w\010dpa.w.ph\tdpadd_s.d\tdpadd_s.h\tdpadd_s.w\tdpadd_u.d\td" 4901 "padd_u.h\tdpadd_u.w\013dpaq_s.w.ph\013dpaq_sa.l.w\014dpaqx_s.w.ph\015dp" 4902 "aqx_sa.w.ph\ndpau.h.qbl\ndpau.h.qbr\tdpax.w.ph\004dpop\010dps.w.ph\013d" 4903 "psq_s.w.ph\013dpsq_sa.l.w\014dpsqx_s.w.ph\015dpsqx_sa.w.ph\ndpsu.h.qbl\n" 4904 "dpsu.h.qbr\tdpsub_s.d\tdpsub_s.h\tdpsub_s.w\tdpsub_u.d\tdpsub_u.h\tdpsu" 4905 "b_u.w\tdpsx.w.ph\004drem\005dremu\004drol\004dror\005drotr\007drotr32\006" 4906 "drotrv\004dsbh\004dshd\004dsll\006dsll32\005dsllv\004dsra\006dsra32\005" 4907 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"mulq_rs.ph\tmulq_rs.w\tmulq_s.ph\010mulq_s.w\010mulr_q.h\010mulr_q.w\nm" 4968 "ulsa.w.ph\015mulsaq_s.w.ph\004mult\005multu\004mulu\006mulv.b\006mulv.d" 4969 "\006mulv.h\006mulv.w\003neg\005neg.d\005neg.s\004negu\006nloc.b\006nloc" 4970 ".d\006nloc.h\006nloc.w\006nlzc.b\006nlzc.d\006nlzc.h\006nlzc.w\007nmadd" 4971 ".d\007nmadd.s\007nmsub.d\007nmsub.s\003nop\003nor\005nor.v\006nori.b\003" 4972 "not\005not16\002or\004or.v\004or16\003ori\005ori.b\tpackrl.ph\005pause\007" 4973 "pckev.b\007pckev.d\007pckev.h\007pckev.w\007pckod.b\007pckod.d\007pckod" 4974 ".h\007pckod.w\006pcnt.b\006pcnt.d\006pcnt.h\006pcnt.w\007pick.ph\007pic" 4975 "k.qb\003pop\014preceq.w.phl\014preceq.w.phr\016precequ.ph.qbl\017preceq" 4976 "u.ph.qbla\016precequ.ph.qbr\017precequ.ph.qbra\015preceu.ph.qbl\016prec" 4977 "eu.ph.qbla\015preceu.ph.qbr\016preceu.ph.qbra\013precr.qb.ph\016precr_s" 4978 "ra.ph.w\020precr_sra_r.ph.w\013precrq.ph.w\014precrq.qb.ph\016precrq_rs" 4979 ".ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w." 4980 "qb\005rddsp\005rdhwr\006rdpgpr\007recip.d\007recip.s\003rem\004remu\007" 4981 "repl.ph\007repl.qb\010replv.ph\010replv.qb\006rint.d\006rint.s\003rol\003" 4982 "ror\004rotr\005rotrv\tround.l.d\tround.l.s\tround.w.d\tround.w.s\007rsq" 4983 "rt.d\007rsqrt.s\003s.d\003s.s\007sat_s.b\007sat_s.d\007sat_s.h\007sat_s" 4984 ".w\007sat_u.b\007sat_u.d\007sat_u.h\007sat_u.w\002sb\004sb16\003sbe\002" 4985 "sc\003scd\003sce\002sd\005sdbbp\007sdbbp16\004sdc1\004sdc2\004sdc3\003s" 4986 "dl\003sdr\005sdxc1\003seb\003seh\005sel.d\005sel.s\006seleqz\010seleqz." 4987 "d\010seleqz.s\006selnez\010selnez.d\010selnez.s\003seq\004seqi\003sgt\004" 4988 "sgtu\002sh\004sh16\003she\005shf.b\005shf.h\005shf.w\005shilo\006shilov" 4989 "\007shll.ph\007shll.qb\tshll_s.ph\010shll_s.w\010shllv.ph\010shllv.qb\n" 4990 "shllv_s.ph\tshllv_s.w\007shra.ph\007shra.qb\tshra_r.ph\tshra_r.qb\010sh" 4991 "ra_r.w\010shrav.ph\010shrav.qb\nshrav_r.ph\nshrav_r.qb\tshrav_r.w\007sh" 4992 "rl.ph\007shrl.qb\010shrlv.ph\010shrlv.qb\005sld.b\005sld.d\005sld.h\005" 4993 "sld.w\006sldi.b\006sldi.d\006sldi.h\006sldi.w\003sll\005sll.b\005sll.d\005" 4994 "sll.h\005sll.w\005sll16\006slli.b\006slli.d\006slli.h\006slli.w\004sllv" 4995 "\003slt\004slti\005sltiu\004sltu\003sne\004snei\007splat.b\007splat.d\007" 4996 "splat.h\007splat.w\010splati.b\010splati.d\010splati.h\010splati.w\006s" 4997 "qrt.d\006sqrt.s\003sra\005sra.b\005sra.d\005sra.h\005sra.w\006srai.b\006" 4998 "srai.d\006srai.h\006srai.w\006srar.b\006srar.d\006srar.h\006srar.w\007s" 4999 "rari.b\007srari.d\007srari.h\007srari.w\004srav\003srl\005srl.b\005srl." 5000 "d\005srl.h\005srl.w\005srl16\006srli.b\006srli.d\006srli.h\006srli.w\006" 5001 "srlr.b\006srlr.d\006srlr.h\006srlr.w\007srlri.b\007srlri.d\007srlri.h\007" 5002 "srlri.w\004srlv\005ssnop\004st.b\004st.d\004st.h\004st.w\003sub\005sub." 5003 "d\005sub.s\007subq.ph\tsubq_s.ph\010subq_s.w\010subqh.ph\007subqh.w\nsu" 5004 "bqh_r.ph\tsubqh_r.w\010subs_s.b\010subs_s.d\010subs_s.h\010subs_s.w\010" 5005 "subs_u.b\010subs_u.d\010subs_u.h\010subs_u.w\nsubsus_u.b\nsubsus_u.d\ns" 5006 "ubsus_u.h\nsubsus_u.w\nsubsuu_s.b\nsubsuu_s.d\nsubsuu_s.h\nsubsuu_s.w\004" 5007 "subu\007subu.ph\007subu.qb\006subu16\tsubu_s.ph\tsubu_s.qb\010subuh.qb\n" 5008 "subuh_r.qb\006subv.b\006subv.d\006subv.h\006subv.w\007subvi.b\007subvi." 5009 "d\007subvi.h\007subvi.w\005suxc1\002sw\004sw16\004swc1\004swc2\004swc3\003" 5010 "swe\003swl\004swle\003swm\005swm16\005swm32\003swp\003swr\004swre\005sw" 5011 "xc1\004sync\005synci\nsynciobdma\005syncs\005syncw\006syncws\007syscall" 5012 "\003teq\004teqi\003tge\004tgei\005tgeiu\004tgeu\007tlbginv\010tlbginvf\005" 5013 "tlbgp\005tlbgr\006tlbgwi\006tlbgwr\006tlbinv\007tlbinvf\004tlbp\004tlbr" 5014 "\005tlbwi\005tlbwr\003tlt\004tlti\005tltiu\004tltu\003tne\004tnei\ttrun" 5015 "c.l.d\ttrunc.l.s\ttrunc.w.d\ttrunc.w.s\003ulh\004ulhu\003ulw\003ush\003" 5016 "usw\006v3mulu\004vmm0\005vmulu\006vshf.b\006vshf.d\006vshf.h\006vshf.w\004" 5017 "wait\005wrdsp\006wrpgpr\004wsbh\003xor\005xor.v\005xor16\004xori\006xor" 5018 "i.b\005yield"; 5019 5020namespace { 5021 struct MatchEntry { 5022 uint16_t Mnemonic; 5023 uint16_t Opcode; 5024 uint16_t ConvertFn; 5025 uint64_t RequiredFeatures; 5026 uint8_t Classes[8]; 5027 StringRef getMnemonic() const { 5028 return StringRef(MnemonicTable + Mnemonic + 1, 5029 MnemonicTable[Mnemonic]); 5030 } 5031 }; 5032 5033 // Predicate for searching for an opcode. 5034 struct LessOpcode { 5035 bool operator()(const MatchEntry &LHS, StringRef RHS) { 5036 return LHS.getMnemonic() < RHS; 5037 } 5038 bool operator()(StringRef LHS, const MatchEntry &RHS) { 5039 return LHS < RHS.getMnemonic(); 5040 } 5041 bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) { 5042 return LHS.getMnemonic() < RHS.getMnemonic(); 5043 } 5044 }; 5045} // end anonymous namespace. 5046 5047static const MatchEntry MatchTable0[] = { 5048 { 0 /* abs */, Mips::ABSMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5049 { 4 /* abs.d */, Mips::FABS_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5050 { 4 /* abs.d */, Mips::FABS_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5051 { 4 /* abs.d */, Mips::FABS_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5052 { 4 /* abs.d */, Mips::FABS_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5053 { 10 /* abs.s */, Mips::FABS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5054 { 10 /* abs.s */, Mips::FABS_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5055 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5056 { 16 /* absq_s.ph */, Mips::ABSQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5057 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5058 { 26 /* absq_s.qb */, Mips::ABSQ_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5059 { 36 /* absq_s.w */, Mips::ABSQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5060 { 36 /* absq_s.w */, Mips::ABSQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5061 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5062 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5063 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5064 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5065 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5066 { 45 /* add */, Mips::ADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5067 { 45 /* add */, Mips::ADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5068 { 45 /* add */, Mips::ADD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5069 { 45 /* add */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5070 { 45 /* add */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5071 { 49 /* add.d */, Mips::FADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5072 { 49 /* add.d */, Mips::FADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5073 { 49 /* add.d */, Mips::FADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5074 { 49 /* add.d */, Mips::FADD_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5075 { 55 /* add.s */, Mips::FADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5076 { 55 /* add.s */, Mips::FADD_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5077 { 55 /* add.s */, Mips::FADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5078 { 61 /* add_a.b */, Mips::ADD_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5079 { 69 /* add_a.d */, Mips::ADD_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5080 { 77 /* add_a.h */, Mips::ADD_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5081 { 85 /* add_a.w */, Mips::ADD_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5082 { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5083 { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5084 { 93 /* addi */, Mips::ADDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 5085 { 93 /* addi */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5086 { 98 /* addiu */, Mips::AddiuSpImmX16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16 }, }, 5087 { 98 /* addiu */, Mips::AddiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 5088 { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5089 { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5090 { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5091 { 98 /* addiu */, Mips::AddiuRxPcImmX16, Convert__Reg1_0__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_PC, MCK_SImm16 }, }, 5092 { 98 /* addiu */, Mips::AddiuRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, 5093 { 98 /* addiu */, Mips::ADDIU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 5094 { 98 /* addiu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 5095 { 98 /* addiu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm16_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16_Relaxed }, }, 5096 { 98 /* addiu */, Mips::AddiuSpImm16, Convert__SImm161_1, Feature_InMips16Mode, { MCK_CPUSPReg, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5097 { 98 /* addiu */, Mips::AddiuRxRxImm16, Convert__Reg1_0__Tie0_1_1__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5098 { 104 /* addiupc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 5099 { 104 /* addiupc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 5100 { 104 /* addiupc */, Mips::ADDIUPC_MM, Convert__GPRMM16AsmReg1_0__Imm1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_Imm }, }, 5101 { 112 /* addiur1sp */, Mips::ADDIUR1SP_MM, Convert__GPRMM16AsmReg1_0__UImm6Lsl21_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_UImm6Lsl2 }, }, 5102 { 122 /* addiur2 */, Mips::ADDIUR2_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 5103 { 130 /* addius5 */, Mips::ADDIUS5_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__ConstantSImm4_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantSImm4_0 }, }, 5104 { 138 /* addiusp */, Mips::ADDIUSP_MM, Convert__Imm1_0, Feature_InMicroMips, { MCK_Imm }, }, 5105 { 146 /* addq.ph */, Mips::ADDQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5106 { 146 /* addq.ph */, Mips::ADDQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5107 { 154 /* addq_s.ph */, Mips::ADDQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5108 { 154 /* addq_s.ph */, Mips::ADDQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5109 { 164 /* addq_s.w */, Mips::ADDQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5110 { 164 /* addq_s.w */, Mips::ADDQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5111 { 173 /* addqh.ph */, Mips::ADDQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5112 { 173 /* addqh.ph */, Mips::ADDQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5113 { 182 /* addqh.w */, Mips::ADDQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5114 { 182 /* addqh.w */, Mips::ADDQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5115 { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5116 { 190 /* addqh_r.ph */, Mips::ADDQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5117 { 201 /* addqh_r.w */, Mips::ADDQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5118 { 201 /* addqh_r.w */, Mips::ADDQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5119 { 211 /* adds_a.b */, Mips::ADDS_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5120 { 220 /* adds_a.d */, Mips::ADDS_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5121 { 229 /* adds_a.h */, Mips::ADDS_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5122 { 238 /* adds_a.w */, Mips::ADDS_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5123 { 247 /* adds_s.b */, Mips::ADDS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5124 { 256 /* adds_s.d */, Mips::ADDS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5125 { 265 /* adds_s.h */, Mips::ADDS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5126 { 274 /* adds_s.w */, Mips::ADDS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5127 { 283 /* adds_u.b */, Mips::ADDS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5128 { 292 /* adds_u.d */, Mips::ADDS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5129 { 301 /* adds_u.h */, Mips::ADDS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5130 { 310 /* adds_u.w */, Mips::ADDS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5131 { 319 /* addsc */, Mips::ADDSC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5132 { 319 /* addsc */, Mips::ADDSC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5133 { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5134 { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5135 { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5136 { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5137 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5138 { 325 /* addu */, Mips::AdduRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, 5139 { 325 /* addu */, Mips::ADDU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5140 { 325 /* addu */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5141 { 325 /* addu */, Mips::ADDu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5142 { 325 /* addu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5143 { 325 /* addu */, Mips::ADDiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5144 { 330 /* addu.ph */, Mips::ADDU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5145 { 330 /* addu.ph */, Mips::ADDU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5146 { 338 /* addu.qb */, Mips::ADDU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5147 { 338 /* addu.qb */, Mips::ADDU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5148 { 346 /* addu16 */, Mips::ADDU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5149 { 346 /* addu16 */, Mips::ADDU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5150 { 353 /* addu_s.ph */, Mips::ADDU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5151 { 353 /* addu_s.ph */, Mips::ADDU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5152 { 363 /* addu_s.qb */, Mips::ADDU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5153 { 363 /* addu_s.qb */, Mips::ADDU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5154 { 373 /* adduh.qb */, Mips::ADDUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5155 { 373 /* adduh.qb */, Mips::ADDUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5156 { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5157 { 382 /* adduh_r.qb */, Mips::ADDUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5158 { 393 /* addv.b */, Mips::ADDV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5159 { 400 /* addv.d */, Mips::ADDV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5160 { 407 /* addv.h */, Mips::ADDV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5161 { 414 /* addv.w */, Mips::ADDV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5162 { 421 /* addvi.b */, Mips::ADDVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5163 { 429 /* addvi.d */, Mips::ADDVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5164 { 437 /* addvi.h */, Mips::ADDVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5165 { 445 /* addvi.w */, Mips::ADDVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5166 { 453 /* addwc */, Mips::ADDWC_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5167 { 453 /* addwc */, Mips::ADDWC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5168 { 459 /* align */, Mips::ALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5169 { 459 /* align */, Mips::ALIGN_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_01_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5170 { 465 /* aluipc */, Mips::ALUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5171 { 465 /* aluipc */, Mips::ALUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5172 { 472 /* and */, Mips::AndRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 5173 { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5174 { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5175 { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5176 { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5177 { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5178 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5179 { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 5180 { 472 /* and */, Mips::AND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5181 { 472 /* and */, Mips::AND_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5182 { 472 /* and */, Mips::AND_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5183 { 472 /* and */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5184 { 472 /* and */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5185 { 472 /* and */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 5186 { 472 /* and */, Mips::ANDi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 5187 { 476 /* and.v */, Mips::AND_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5188 { 482 /* and16 */, Mips::AND16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5189 { 482 /* and16 */, Mips::AND16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 5190 { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5191 { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5192 { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 5193 { 488 /* andi */, Mips::ANDI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5194 { 488 /* andi */, Mips::ANDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5195 { 488 /* andi */, Mips::ANDi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5196 { 493 /* andi.b */, Mips::ANDI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5197 { 500 /* andi16 */, Mips::ANDI16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 5198 { 500 /* andi16 */, Mips::ANDI16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 5199 { 507 /* append */, Mips::APPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 5200 { 507 /* append */, Mips::APPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 5201 { 514 /* asub_s.b */, Mips::ASUB_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5202 { 523 /* asub_s.d */, Mips::ASUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5203 { 532 /* asub_s.h */, Mips::ASUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5204 { 541 /* asub_s.w */, Mips::ASUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5205 { 550 /* asub_u.b */, Mips::ASUB_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5206 { 559 /* asub_u.d */, Mips::ASUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5207 { 568 /* asub_u.h */, Mips::ASUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5208 { 577 /* asub_u.w */, Mips::ASUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5209 { 586 /* aui */, Mips::AUI, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5210 { 586 /* aui */, Mips::AUI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 5211 { 590 /* auipc */, Mips::AUIPC, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5212 { 590 /* auipc */, Mips::AUIPC_MMR6, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 5213 { 596 /* ave_s.b */, Mips::AVE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5214 { 604 /* ave_s.d */, Mips::AVE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5215 { 612 /* ave_s.h */, Mips::AVE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5216 { 620 /* ave_s.w */, Mips::AVE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5217 { 628 /* ave_u.b */, Mips::AVE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5218 { 636 /* ave_u.d */, Mips::AVE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5219 { 644 /* ave_u.h */, Mips::AVE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5220 { 652 /* ave_u.w */, Mips::AVE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5221 { 660 /* aver_s.b */, Mips::AVER_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5222 { 669 /* aver_s.d */, Mips::AVER_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5223 { 678 /* aver_s.h */, Mips::AVER_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5224 { 687 /* aver_s.w */, Mips::AVER_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5225 { 696 /* aver_u.b */, Mips::AVER_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5226 { 705 /* aver_u.d */, Mips::AVER_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5227 { 714 /* aver_u.h */, Mips::AVER_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5228 { 723 /* aver_u.w */, Mips::AVER_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5229 { 732 /* b */, Mips::BEQ, Convert__regZERO__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5230 { 732 /* b */, Mips::B_MM_Pseudo, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, }, 5231 { 732 /* b */, Mips::BimmX16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget }, }, 5232 { 732 /* b */, Mips::B_MMR6_Pseudo, Convert__JumpTarget1_0, 0, { MCK_JumpTarget }, }, 5233 { 732 /* b */, Mips::Bimm16, Convert__JumpTarget1_0, Feature_InMips16Mode, { MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5234 { 734 /* b16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, }, 5235 { 734 /* b16 */, Mips::B16_MM, Convert__JumpTarget1_0, Feature_InMicroMips, { MCK_JumpTarget }, }, 5236 { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5237 { 738 /* baddu */, Mips::BADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5238 { 744 /* bal */, Mips::BGEZAL, Convert__regZERO__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5239 { 744 /* bal */, Mips::BAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, }, 5240 { 744 /* bal */, Mips::BGEZAL_MM, Convert__regZERO__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, }, 5241 { 748 /* balc */, Mips::BALC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_JumpTarget }, }, 5242 { 748 /* balc */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, }, 5243 { 753 /* balign */, Mips::BALIGN_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5244 { 753 /* balign */, Mips::BALIGN, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm2_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 5245 { 760 /* bbit0 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, 5246 { 760 /* bbit0 */, Mips::BBIT0, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, 5247 { 766 /* bbit032 */, Mips::BBIT032, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, 5248 { 774 /* bbit1 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_JumpTarget }, }, 5249 { 774 /* bbit1 */, Mips::BBIT1, Convert__GPR64AsmReg1_0__ConstantUImm5_0_Report_UImm61_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_JumpTarget }, }, 5250 { 780 /* bbit132 */, Mips::BBIT132, Convert__GPR64AsmReg1_0__ConstantUImm5_01_1__JumpTarget1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_JumpTarget }, }, 5251 { 788 /* bc */, Mips::BC, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5252 { 788 /* bc */, Mips::BC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, }, 5253 { 791 /* bc16 */, Mips::BC16_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, }, 5254 { 796 /* bc1eqz */, Mips::BC1EQZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5255 { 803 /* bc1eqzc */, Mips::BC1EQZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5256 { 811 /* bc1f */, Mips::BC1F, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5257 { 811 /* bc1f */, Mips::BC1F_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, }, 5258 { 811 /* bc1f */, Mips::BC1F, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5259 { 811 /* bc1f */, Mips::BC1F_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5260 { 816 /* bc1fl */, Mips::BC1FL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5261 { 816 /* bc1fl */, Mips::BC1FL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5262 { 822 /* bc1nez */, Mips::BC1NEZ, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5263 { 829 /* bc1nezc */, Mips::BC1NEZC_MMR6, Convert__FGR64AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_JumpTarget }, }, 5264 { 837 /* bc1t */, Mips::BC1T, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5265 { 837 /* bc1t */, Mips::BC1T_MM, Convert__regFCC0__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_JumpTarget }, }, 5266 { 837 /* bc1t */, Mips::BC1T, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5267 { 837 /* bc1t */, Mips::BC1T_MM, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5268 { 842 /* bc1tl */, Mips::BC1TL, Convert__regFCC0__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5269 { 842 /* bc1tl */, Mips::BC1TL, Convert__FCCAsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_JumpTarget }, }, 5270 { 848 /* bc2eqz */, Mips::BC2EQZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5271 { 855 /* bc2eqzc */, Mips::BC2EQZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5272 { 863 /* bc2nez */, Mips::BC2NEZ, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5273 { 870 /* bc2nezc */, Mips::BC2NEZC_MMR6, Convert__COP2AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_JumpTarget }, }, 5274 { 878 /* bclr.b */, Mips::BCLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5275 { 885 /* bclr.d */, Mips::BCLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5276 { 892 /* bclr.h */, Mips::BCLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5277 { 899 /* bclr.w */, Mips::BCLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5278 { 906 /* bclri.b */, Mips::BCLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5279 { 914 /* bclri.d */, Mips::BCLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5280 { 922 /* bclri.h */, Mips::BCLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5281 { 930 /* bclri.w */, Mips::BCLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5282 { 938 /* beq */, Mips::BEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5283 { 938 /* beq */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5284 { 938 /* beq */, Mips::BeqImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5285 { 942 /* beqc */, Mips::BEQC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5286 { 942 /* beqc */, Mips::BEQC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5287 { 942 /* beqc */, Mips::BEQC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5288 { 947 /* beql */, Mips::BEQL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5289 { 947 /* beql */, Mips::BEQLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5290 { 952 /* beqz */, Mips::BeqzRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, 5291 { 952 /* beqz */, Mips::BEQ, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5292 { 952 /* beqz */, Mips::BEQ_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5293 { 952 /* beqz */, Mips::BeqzRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5294 { 957 /* beqz16 */, Mips::BEQZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5295 { 957 /* beqz16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5296 { 964 /* beqzalc */, Mips::BEQZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5297 { 964 /* beqzalc */, Mips::BEQZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5298 { 972 /* beqzc */, Mips::BEQZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5299 { 972 /* beqzc */, Mips::BEQZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5300 { 972 /* beqzc */, Mips::BEQZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5301 { 972 /* beqzc */, Mips::BEQZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5302 { 978 /* beqzc16 */, Mips::BEQZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5303 { 986 /* beqzl */, Mips::BEQL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5304 { 992 /* bge */, Mips::BGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5305 { 992 /* bge */, Mips::BGEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5306 { 996 /* bgec */, Mips::BGEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5307 { 996 /* bgec */, Mips::BGEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5308 { 996 /* bgec */, Mips::BGEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5309 { 1001 /* bgel */, Mips::BGEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5310 { 1001 /* bgel */, Mips::BGELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5311 { 1006 /* bgeu */, Mips::BGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5312 { 1006 /* bgeu */, Mips::BGEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5313 { 1011 /* bgeuc */, Mips::BGEUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5314 { 1011 /* bgeuc */, Mips::BGEUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5315 { 1011 /* bgeuc */, Mips::BGEUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5316 { 1017 /* bgeul */, Mips::BGEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5317 { 1017 /* bgeul */, Mips::BGEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5318 { 1023 /* bgez */, Mips::BGEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5319 { 1023 /* bgez */, Mips::BGEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5320 { 1028 /* bgezal */, Mips::BGEZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5321 { 1028 /* bgezal */, Mips::BGEZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5322 { 1035 /* bgezalc */, Mips::BGEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5323 { 1035 /* bgezalc */, Mips::BGEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5324 { 1043 /* bgezall */, Mips::BGEZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5325 { 1051 /* bgezals */, Mips::BGEZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5326 { 1059 /* bgezc */, Mips::BGEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5327 { 1059 /* bgezc */, Mips::BGEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5328 { 1059 /* bgezc */, Mips::BGEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5329 { 1065 /* bgezl */, Mips::BGEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5330 { 1071 /* bgt */, Mips::BGT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5331 { 1071 /* bgt */, Mips::BGTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5332 { 1075 /* bgtl */, Mips::BGTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5333 { 1075 /* bgtl */, Mips::BGTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5334 { 1080 /* bgtu */, Mips::BGTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5335 { 1080 /* bgtu */, Mips::BGTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5336 { 1085 /* bgtul */, Mips::BGTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5337 { 1085 /* bgtul */, Mips::BGTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5338 { 1091 /* bgtz */, Mips::BGTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5339 { 1091 /* bgtz */, Mips::BGTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5340 { 1096 /* bgtzalc */, Mips::BGTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5341 { 1096 /* bgtzalc */, Mips::BGTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5342 { 1104 /* bgtzc */, Mips::BGTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5343 { 1104 /* bgtzc */, Mips::BGTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5344 { 1104 /* bgtzc */, Mips::BGTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5345 { 1110 /* bgtzl */, Mips::BGTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5346 { 1116 /* binsl.b */, Mips::BINSL_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5347 { 1124 /* binsl.d */, Mips::BINSL_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5348 { 1132 /* binsl.h */, Mips::BINSL_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5349 { 1140 /* binsl.w */, Mips::BINSL_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5350 { 1148 /* binsli.b */, Mips::BINSLI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5351 { 1157 /* binsli.d */, Mips::BINSLI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5352 { 1166 /* binsli.h */, Mips::BINSLI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5353 { 1175 /* binsli.w */, Mips::BINSLI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5354 { 1184 /* binsr.b */, Mips::BINSR_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5355 { 1192 /* binsr.d */, Mips::BINSR_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5356 { 1200 /* binsr.h */, Mips::BINSR_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5357 { 1208 /* binsr.w */, Mips::BINSR_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5358 { 1216 /* binsri.b */, Mips::BINSRI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5359 { 1225 /* binsri.d */, Mips::BINSRI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5360 { 1234 /* binsri.h */, Mips::BINSRI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5361 { 1243 /* binsri.w */, Mips::BINSRI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5362 { 1252 /* bitrev */, Mips::BITREV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5363 { 1252 /* bitrev */, Mips::BITREV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5364 { 1259 /* bitswap */, Mips::BITSWAP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5365 { 1259 /* bitswap */, Mips::BITSWAP_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5366 { 1267 /* ble */, Mips::BLE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5367 { 1267 /* ble */, Mips::BLEImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5368 { 1271 /* blel */, Mips::BLEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5369 { 1271 /* blel */, Mips::BLELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5370 { 1276 /* bleu */, Mips::BLEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5371 { 1276 /* bleu */, Mips::BLEUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5372 { 1281 /* bleul */, Mips::BLEUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5373 { 1281 /* bleul */, Mips::BLEULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5374 { 1287 /* blez */, Mips::BLEZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5375 { 1287 /* blez */, Mips::BLEZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5376 { 1292 /* blezalc */, Mips::BLEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5377 { 1292 /* blezalc */, Mips::BLEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5378 { 1300 /* blezc */, Mips::BLEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5379 { 1300 /* blezc */, Mips::BLEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5380 { 1300 /* blezc */, Mips::BLEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5381 { 1306 /* blezl */, Mips::BLEZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5382 { 1312 /* blt */, Mips::BLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5383 { 1312 /* blt */, Mips::BLTImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5384 { 1316 /* bltc */, Mips::BLTC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5385 { 1316 /* bltc */, Mips::BLTC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5386 { 1316 /* bltc */, Mips::BLTC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5387 { 1321 /* bltl */, Mips::BLTL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5388 { 1321 /* bltl */, Mips::BLTLImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5389 { 1326 /* bltu */, Mips::BLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5390 { 1326 /* bltu */, Mips::BLTUImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5391 { 1331 /* bltuc */, Mips::BLTUC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5392 { 1331 /* bltuc */, Mips::BLTUC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5393 { 1331 /* bltuc */, Mips::BLTUC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5394 { 1337 /* bltul */, Mips::BLTUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5395 { 1337 /* bltul */, Mips::BLTULImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5396 { 1343 /* bltz */, Mips::BLTZ, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5397 { 1343 /* bltz */, Mips::BLTZ_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5398 { 1348 /* bltzal */, Mips::BLTZAL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5399 { 1348 /* bltzal */, Mips::BLTZAL_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5400 { 1355 /* bltzalc */, Mips::BLTZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5401 { 1355 /* bltzalc */, Mips::BLTZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5402 { 1363 /* bltzall */, Mips::BLTZALL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5403 { 1371 /* bltzals */, Mips::BLTZALS_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5404 { 1379 /* bltzc */, Mips::BLTZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5405 { 1379 /* bltzc */, Mips::BLTZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5406 { 1379 /* bltzc */, Mips::BLTZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5407 { 1385 /* bltzl */, Mips::BLTZL, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5408 { 1391 /* bmnz.v */, Mips::BMNZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5409 { 1398 /* bmnzi.b */, Mips::BMNZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5410 { 1406 /* bmz.v */, Mips::BMZ_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5411 { 1412 /* bmzi.b */, Mips::BMZI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5412 { 1419 /* bne */, Mips::BNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5413 { 1419 /* bne */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5414 { 1419 /* bne */, Mips::BneImm, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, 0, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5415 { 1423 /* bnec */, Mips::BNEC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5416 { 1423 /* bnec */, Mips::BNEC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5417 { 1423 /* bnec */, Mips::BNEC64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5418 { 1428 /* bneg.b */, Mips::BNEG_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5419 { 1435 /* bneg.d */, Mips::BNEG_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5420 { 1442 /* bneg.h */, Mips::BNEG_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5421 { 1449 /* bneg.w */, Mips::BNEG_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5422 { 1456 /* bnegi.b */, Mips::BNEGI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5423 { 1464 /* bnegi.d */, Mips::BNEGI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5424 { 1472 /* bnegi.h */, Mips::BNEGI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5425 { 1480 /* bnegi.w */, Mips::BNEGI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5426 { 1488 /* bnel */, Mips::BNEL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5427 { 1488 /* bnel */, Mips::BNELImmMacro, Convert__GPR32AsmReg1_0__Imm1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_Imm, MCK_JumpTarget }, }, 5428 { 1493 /* bnez */, Mips::BnezRxImmX16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget }, }, 5429 { 1493 /* bnez */, Mips::BNE, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5430 { 1493 /* bnez */, Mips::BNE_MM, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5431 { 1493 /* bnez */, Mips::BnezRxImm16, Convert__Reg1_0__JumpTarget1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_JumpTarget, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5432 { 1498 /* bnez16 */, Mips::BNEZ16_MM, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5433 { 1498 /* bnez16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5434 { 1505 /* bnezalc */, Mips::BNEZALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5435 { 1505 /* bnezalc */, Mips::BNEZALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5436 { 1513 /* bnezc */, Mips::BNEZC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5437 { 1513 /* bnezc */, Mips::BNEZC_MM, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5438 { 1513 /* bnezc */, Mips::BNEZC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5439 { 1513 /* bnezc */, Mips::BNEZC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 5440 { 1519 /* bnezc16 */, Mips::BNEZC16_MMR6, Convert__GPRMM16AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_JumpTarget }, }, 5441 { 1527 /* bnezl */, Mips::BNEL, Convert__GPR32AsmReg1_0__regZERO__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5442 { 1533 /* bnvc */, Mips::BNVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5443 { 1533 /* bnvc */, Mips::BNVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5444 { 1538 /* bnz.b */, Mips::BNZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5445 { 1544 /* bnz.d */, Mips::BNZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5446 { 1550 /* bnz.h */, Mips::BNZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5447 { 1556 /* bnz.v */, Mips::BNZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5448 { 1562 /* bnz.w */, Mips::BNZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5449 { 1568 /* bovc */, Mips::BOVC, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5450 { 1568 /* bovc */, Mips::BOVC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__JumpTarget1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_JumpTarget }, }, 5451 { 1573 /* bposge32 */, Mips::BPOSGE32_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, { MCK_JumpTarget }, }, 5452 { 1573 /* bposge32 */, Mips::BPOSGE32, Convert__JumpTarget1_0, Feature_HasDSP|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 5453 { 1582 /* bposge32c */, Mips::BPOSGE32C_MMR3, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasDSPR3, { MCK_JumpTarget }, }, 5454 { 1592 /* break */, Mips::BREAK, Convert__imm_95_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 5455 { 1592 /* break */, Mips::BREAK_MM, Convert__imm_95_0__imm_95_0, Feature_InMicroMips, { }, }, 5456 { 1592 /* break */, Mips::Break16, Convert_NoOperands, Feature_InMips16Mode, { MCK_0 }, }, 5457 { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, 5458 { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__imm_95_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, }, 5459 { 1592 /* break */, Mips::BREAK, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, 5460 { 1592 /* break */, Mips::BREAK_MMR6, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, 5461 { 1592 /* break */, Mips::BREAK_MM, Convert__ConstantUImm10_01_0__ConstantUImm10_01_1, Feature_InMicroMips, { MCK_ConstantUImm10_0, MCK_ConstantUImm10_0 }, }, 5462 { 1598 /* break16 */, Mips::BREAK16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, }, 5463 { 1598 /* break16 */, Mips::BREAK16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, }, 5464 { 1606 /* bsel.v */, Mips::BSEL_V, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5465 { 1613 /* bseli.b */, Mips::BSELI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 5466 { 1621 /* bset.b */, Mips::BSET_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5467 { 1628 /* bset.d */, Mips::BSET_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5468 { 1635 /* bset.h */, Mips::BSET_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5469 { 1642 /* bset.w */, Mips::BSET_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5470 { 1649 /* bseti.b */, Mips::BSETI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 5471 { 1657 /* bseti.d */, Mips::BSETI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 5472 { 1665 /* bseti.h */, Mips::BSETI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 5473 { 1673 /* bseti.w */, Mips::BSETI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5474 { 1681 /* bteqz */, Mips::BteqzX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, }, 5475 { 1681 /* bteqz */, Mips::Bteqz16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5476 { 1687 /* btnez */, Mips::BtnezX16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16 }, }, 5477 { 1687 /* btnez */, Mips::Btnez16, Convert__SImm161_0, Feature_InMips16Mode, { MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5478 { 1693 /* bz.b */, Mips::BZ_B, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5479 { 1698 /* bz.d */, Mips::BZ_D, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5480 { 1703 /* bz.h */, Mips::BZ_H, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5481 { 1708 /* bz.v */, Mips::BZ_V, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5482 { 1713 /* bz.w */, Mips::BZ_W, Convert__MSA128AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_JumpTarget }, }, 5483 { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5484 { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5485 { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5486 { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5487 { 1718 /* c.eq.d */, Mips::C_EQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5488 { 1718 /* c.eq.d */, Mips::C_EQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5489 { 1718 /* c.eq.d */, Mips::C_EQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5490 { 1718 /* c.eq.d */, Mips::C_EQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5491 { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5492 { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5493 { 1725 /* c.eq.s */, Mips::C_EQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5494 { 1725 /* c.eq.s */, Mips::C_EQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5495 { 1732 /* c.f.d */, Mips::C_F_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5496 { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5497 { 1732 /* c.f.d */, Mips::C_F_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5498 { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5499 { 1732 /* c.f.d */, Mips::C_F_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5500 { 1732 /* c.f.d */, Mips::C_F_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5501 { 1732 /* c.f.d */, Mips::C_F_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5502 { 1732 /* c.f.d */, Mips::C_F_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5503 { 1738 /* c.f.s */, Mips::C_F_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5504 { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5505 { 1738 /* c.f.s */, Mips::C_F_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5506 { 1738 /* c.f.s */, Mips::C_F_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5507 { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5508 { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5509 { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5510 { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5511 { 1744 /* c.le.d */, Mips::C_LE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5512 { 1744 /* c.le.d */, Mips::C_LE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5513 { 1744 /* c.le.d */, Mips::C_LE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5514 { 1744 /* c.le.d */, Mips::C_LE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5515 { 1751 /* c.le.s */, Mips::C_LE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5516 { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5517 { 1751 /* c.le.s */, Mips::C_LE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5518 { 1751 /* c.le.s */, Mips::C_LE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5519 { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5520 { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5521 { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5522 { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5523 { 1758 /* c.lt.d */, Mips::C_LT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5524 { 1758 /* c.lt.d */, Mips::C_LT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5525 { 1758 /* c.lt.d */, Mips::C_LT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5526 { 1758 /* c.lt.d */, Mips::C_LT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5527 { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5528 { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5529 { 1765 /* c.lt.s */, Mips::C_LT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5530 { 1765 /* c.lt.s */, Mips::C_LT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5531 { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5532 { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5533 { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5534 { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5535 { 1772 /* c.nge.d */, Mips::C_NGE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5536 { 1772 /* c.nge.d */, Mips::C_NGE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5537 { 1772 /* c.nge.d */, Mips::C_NGE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5538 { 1772 /* c.nge.d */, Mips::C_NGE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5539 { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5540 { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5541 { 1780 /* c.nge.s */, Mips::C_NGE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5542 { 1780 /* c.nge.s */, Mips::C_NGE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5543 { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5544 { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5545 { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5546 { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5547 { 1788 /* c.ngl.d */, Mips::C_NGL_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5548 { 1788 /* c.ngl.d */, Mips::C_NGL_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5549 { 1788 /* c.ngl.d */, Mips::C_NGL_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5550 { 1788 /* c.ngl.d */, Mips::C_NGL_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5551 { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5552 { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5553 { 1796 /* c.ngl.s */, Mips::C_NGL_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5554 { 1796 /* c.ngl.s */, Mips::C_NGL_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5555 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5556 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5557 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5558 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5559 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5560 { 1804 /* c.ngle.d */, Mips::C_NGLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5561 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5562 { 1804 /* c.ngle.d */, Mips::C_NGLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5563 { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5564 { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5565 { 1813 /* c.ngle.s */, Mips::C_NGLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5566 { 1813 /* c.ngle.s */, Mips::C_NGLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5567 { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5568 { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5569 { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5570 { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5571 { 1822 /* c.ngt.d */, Mips::C_NGT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5572 { 1822 /* c.ngt.d */, Mips::C_NGT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5573 { 1822 /* c.ngt.d */, Mips::C_NGT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5574 { 1822 /* c.ngt.d */, Mips::C_NGT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5575 { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5576 { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5577 { 1830 /* c.ngt.s */, Mips::C_NGT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5578 { 1830 /* c.ngt.s */, Mips::C_NGT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5579 { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5580 { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5581 { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5582 { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5583 { 1838 /* c.ole.d */, Mips::C_OLE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5584 { 1838 /* c.ole.d */, Mips::C_OLE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5585 { 1838 /* c.ole.d */, Mips::C_OLE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5586 { 1838 /* c.ole.d */, Mips::C_OLE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5587 { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5588 { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5589 { 1846 /* c.ole.s */, Mips::C_OLE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5590 { 1846 /* c.ole.s */, Mips::C_OLE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5591 { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5592 { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5593 { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5594 { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5595 { 1854 /* c.olt.d */, Mips::C_OLT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5596 { 1854 /* c.olt.d */, Mips::C_OLT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5597 { 1854 /* c.olt.d */, Mips::C_OLT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5598 { 1854 /* c.olt.d */, Mips::C_OLT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5599 { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5600 { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5601 { 1862 /* c.olt.s */, Mips::C_OLT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5602 { 1862 /* c.olt.s */, Mips::C_OLT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5603 { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5604 { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5605 { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5606 { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5607 { 1870 /* c.seq.d */, Mips::C_SEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5608 { 1870 /* c.seq.d */, Mips::C_SEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5609 { 1870 /* c.seq.d */, Mips::C_SEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5610 { 1870 /* c.seq.d */, Mips::C_SEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5611 { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5612 { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5613 { 1878 /* c.seq.s */, Mips::C_SEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5614 { 1878 /* c.seq.s */, Mips::C_SEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5615 { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5616 { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5617 { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5618 { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5619 { 1886 /* c.sf.d */, Mips::C_SF_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5620 { 1886 /* c.sf.d */, Mips::C_SF_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5621 { 1886 /* c.sf.d */, Mips::C_SF_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5622 { 1886 /* c.sf.d */, Mips::C_SF_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5623 { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5624 { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5625 { 1893 /* c.sf.s */, Mips::C_SF_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5626 { 1893 /* c.sf.s */, Mips::C_SF_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5627 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5628 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5629 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5630 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5631 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5632 { 1900 /* c.ueq.d */, Mips::C_UEQ_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5633 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5634 { 1900 /* c.ueq.d */, Mips::C_UEQ_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5635 { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5636 { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5637 { 1908 /* c.ueq.s */, Mips::C_UEQ_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5638 { 1908 /* c.ueq.s */, Mips::C_UEQ_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5639 { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5640 { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5641 { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5642 { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5643 { 1916 /* c.ule.d */, Mips::C_ULE_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5644 { 1916 /* c.ule.d */, Mips::C_ULE_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5645 { 1916 /* c.ule.d */, Mips::C_ULE_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5646 { 1916 /* c.ule.d */, Mips::C_ULE_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5647 { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5648 { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5649 { 1924 /* c.ule.s */, Mips::C_ULE_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5650 { 1924 /* c.ule.s */, Mips::C_ULE_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5651 { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5652 { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5653 { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5654 { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5655 { 1932 /* c.ult.d */, Mips::C_ULT_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5656 { 1932 /* c.ult.d */, Mips::C_ULT_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5657 { 1932 /* c.ult.d */, Mips::C_ULT_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5658 { 1932 /* c.ult.d */, Mips::C_ULT_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5659 { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5660 { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5661 { 1940 /* c.ult.s */, Mips::C_ULT_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5662 { 1940 /* c.ult.s */, Mips::C_ULT_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5663 { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5664 { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__regFCC0__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5665 { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5666 { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__regFCC0__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5667 { 1948 /* c.un.d */, Mips::C_UN_D32, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5668 { 1948 /* c.un.d */, Mips::C_UN_D32_MM, Convert__FCCAsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5669 { 1948 /* c.un.d */, Mips::C_UN_D64, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5670 { 1948 /* c.un.d */, Mips::C_UN_D64_MM, Convert__FCCAsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5671 { 1955 /* c.un.s */, Mips::C_UN_S, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5672 { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__regFCC0__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5673 { 1955 /* c.un.s */, Mips::C_UN_S, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5674 { 1955 /* c.un.s */, Mips::C_UN_S_MM, Convert__FCCAsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FCCAsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5675 { 1962 /* cache */, Mips::CACHE_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 5676 { 1962 /* cache */, Mips::CACHE, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, 5677 { 1962 /* cache */, Mips::CACHE_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 5678 { 1962 /* cache */, Mips::CACHE_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 5679 { 1968 /* cachee */, Mips::CACHEE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 5680 { 1968 /* cachee */, Mips::CACHEE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 5681 { 1975 /* ceil.l.d */, Mips::CEIL_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5682 { 1975 /* ceil.l.d */, Mips::CEIL_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5683 { 1984 /* ceil.l.s */, Mips::CEIL_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5684 { 1984 /* ceil.l.s */, Mips::CEIL_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5685 { 1993 /* ceil.w.d */, Mips::CEIL_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5686 { 1993 /* ceil.w.d */, Mips::CEIL_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5687 { 1993 /* ceil.w.d */, Mips::CEIL_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5688 { 1993 /* ceil.w.d */, Mips::CEIL_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 5689 { 2002 /* ceil.w.s */, Mips::CEIL_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5690 { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5691 { 2002 /* ceil.w.s */, Mips::CEIL_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5692 { 2011 /* ceq.b */, Mips::CEQ_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5693 { 2017 /* ceq.d */, Mips::CEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5694 { 2023 /* ceq.h */, Mips::CEQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5695 { 2029 /* ceq.w */, Mips::CEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5696 { 2035 /* ceqi.b */, Mips::CEQI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5697 { 2042 /* ceqi.d */, Mips::CEQI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5698 { 2049 /* ceqi.h */, Mips::CEQI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5699 { 2056 /* ceqi.w */, Mips::CEQI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5700 { 2063 /* cfc1 */, Mips::CFC1, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 5701 { 2063 /* cfc1 */, Mips::CFC1_MM, Convert__GPR32AsmReg1_0__CCRAsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 5702 { 2068 /* cfc2 */, Mips::CFC2_MM, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 5703 { 2073 /* cfcmsa */, Mips::CFCMSA, Convert__GPR32AsmReg1_0__MSACtrlAsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSACtrlAsmReg }, }, 5704 { 2080 /* cftc1 */, Mips::CFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 5705 { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 5706 { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 5707 { 2086 /* cins */, Mips::CINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 5708 { 2086 /* cins */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 5709 { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 5710 { 2091 /* cins32 */, Mips::CINS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 5711 { 2098 /* class.d */, Mips::CLASS_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5712 { 2098 /* class.d */, Mips::CLASS_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5713 { 2106 /* class.s */, Mips::CLASS_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5714 { 2106 /* class.s */, Mips::CLASS_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5715 { 2114 /* cle_s.b */, Mips::CLE_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5716 { 2122 /* cle_s.d */, Mips::CLE_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5717 { 2130 /* cle_s.h */, Mips::CLE_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5718 { 2138 /* cle_s.w */, Mips::CLE_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5719 { 2146 /* cle_u.b */, Mips::CLE_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5720 { 2154 /* cle_u.d */, Mips::CLE_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5721 { 2162 /* cle_u.h */, Mips::CLE_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5722 { 2170 /* cle_u.w */, Mips::CLE_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5723 { 2178 /* clei_s.b */, Mips::CLEI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5724 { 2187 /* clei_s.d */, Mips::CLEI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5725 { 2196 /* clei_s.h */, Mips::CLEI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5726 { 2205 /* clei_s.w */, Mips::CLEI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5727 { 2214 /* clei_u.b */, Mips::CLEI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5728 { 2223 /* clei_u.d */, Mips::CLEI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5729 { 2232 /* clei_u.h */, Mips::CLEI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5730 { 2241 /* clei_u.w */, Mips::CLEI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5731 { 2250 /* clo */, Mips::CLO, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5732 { 2250 /* clo */, Mips::CLO_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5733 { 2250 /* clo */, Mips::CLO_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5734 { 2250 /* clo */, Mips::CLO_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5735 { 2254 /* clt_s.b */, Mips::CLT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5736 { 2262 /* clt_s.d */, Mips::CLT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5737 { 2270 /* clt_s.h */, Mips::CLT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5738 { 2278 /* clt_s.w */, Mips::CLT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5739 { 2286 /* clt_u.b */, Mips::CLT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5740 { 2294 /* clt_u.d */, Mips::CLT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5741 { 2302 /* clt_u.h */, Mips::CLT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5742 { 2310 /* clt_u.w */, Mips::CLT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5743 { 2318 /* clti_s.b */, Mips::CLTI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5744 { 2327 /* clti_s.d */, Mips::CLTI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5745 { 2336 /* clti_s.h */, Mips::CLTI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5746 { 2345 /* clti_s.w */, Mips::CLTI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 5747 { 2354 /* clti_u.b */, Mips::CLTI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5748 { 2363 /* clti_u.d */, Mips::CLTI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5749 { 2372 /* clti_u.h */, Mips::CLTI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5750 { 2381 /* clti_u.w */, Mips::CLTI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 5751 { 2390 /* clz */, Mips::CLZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5752 { 2390 /* clz */, Mips::CLZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5753 { 2390 /* clz */, Mips::CLZ_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5754 { 2390 /* clz */, Mips::CLZ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5755 { 2394 /* cmp */, Mips::CmpRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 5756 { 2398 /* cmp.af.d */, Mips::CMP_F_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5757 { 2398 /* cmp.af.d */, Mips::CMP_AF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5758 { 2407 /* cmp.af.s */, Mips::CMP_F_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5759 { 2407 /* cmp.af.s */, Mips::CMP_AF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5760 { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5761 { 2416 /* cmp.eq.d */, Mips::CMP_EQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5762 { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5763 { 2425 /* cmp.eq.ph */, Mips::CMP_EQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5764 { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5765 { 2435 /* cmp.eq.s */, Mips::CMP_EQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5766 { 2444 /* cmp.le.d */, Mips::CMP_LE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5767 { 2444 /* cmp.le.d */, Mips::CMP_LE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5768 { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5769 { 2453 /* cmp.le.ph */, Mips::CMP_LE_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5770 { 2463 /* cmp.le.s */, Mips::CMP_LE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5771 { 2463 /* cmp.le.s */, Mips::CMP_LE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5772 { 2472 /* cmp.lt.d */, Mips::CMP_LT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5773 { 2472 /* cmp.lt.d */, Mips::CMP_LT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5774 { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5775 { 2481 /* cmp.lt.ph */, Mips::CMP_LT_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5776 { 2491 /* cmp.lt.s */, Mips::CMP_LT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5777 { 2491 /* cmp.lt.s */, Mips::CMP_LT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5778 { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5779 { 2500 /* cmp.saf.d */, Mips::CMP_SAF_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5780 { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5781 { 2510 /* cmp.saf.s */, Mips::CMP_SAF_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5782 { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5783 { 2520 /* cmp.seq.d */, Mips::CMP_SEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5784 { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5785 { 2530 /* cmp.seq.s */, Mips::CMP_SEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5786 { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5787 { 2540 /* cmp.sle.d */, Mips::CMP_SLE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5788 { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5789 { 2550 /* cmp.sle.s */, Mips::CMP_SLE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5790 { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5791 { 2560 /* cmp.slt.d */, Mips::CMP_SLT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5792 { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5793 { 2570 /* cmp.slt.s */, Mips::CMP_SLT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5794 { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5795 { 2580 /* cmp.sueq.d */, Mips::CMP_SUEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5796 { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5797 { 2591 /* cmp.sueq.s */, Mips::CMP_SUEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5798 { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5799 { 2602 /* cmp.sule.d */, Mips::CMP_SULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5800 { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5801 { 2613 /* cmp.sule.s */, Mips::CMP_SULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5802 { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5803 { 2624 /* cmp.sult.d */, Mips::CMP_SULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5804 { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5805 { 2635 /* cmp.sult.s */, Mips::CMP_SULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5806 { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5807 { 2646 /* cmp.sun.d */, Mips::CMP_SUN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5808 { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5809 { 2656 /* cmp.sun.s */, Mips::CMP_SUN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5810 { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5811 { 2666 /* cmp.ueq.d */, Mips::CMP_UEQ_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5812 { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5813 { 2676 /* cmp.ueq.s */, Mips::CMP_UEQ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5814 { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5815 { 2686 /* cmp.ule.d */, Mips::CMP_ULE_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5816 { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5817 { 2696 /* cmp.ule.s */, Mips::CMP_ULE_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5818 { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5819 { 2706 /* cmp.ult.d */, Mips::CMP_ULT_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5820 { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5821 { 2716 /* cmp.ult.s */, Mips::CMP_ULT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5822 { 2726 /* cmp.un.d */, Mips::CMP_UN_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5823 { 2726 /* cmp.un.d */, Mips::CMP_UN_D_MMR6, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5824 { 2735 /* cmp.un.s */, Mips::CMP_UN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5825 { 2735 /* cmp.un.s */, Mips::CMP_UN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5826 { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5827 { 2744 /* cmpgdu.eq.qb */, Mips::CMPGDU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5828 { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5829 { 2757 /* cmpgdu.le.qb */, Mips::CMPGDU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5830 { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5831 { 2770 /* cmpgdu.lt.qb */, Mips::CMPGDU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5832 { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5833 { 2783 /* cmpgu.eq.qb */, Mips::CMPGU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5834 { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5835 { 2795 /* cmpgu.le.qb */, Mips::CMPGU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5836 { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5837 { 2807 /* cmpgu.lt.qb */, Mips::CMPGU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5838 { 2819 /* cmpi */, Mips::CmpiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 5839 { 2819 /* cmpi */, Mips::CmpiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 5840 { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5841 { 2824 /* cmpu.eq.qb */, Mips::CMPU_EQ_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5842 { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5843 { 2835 /* cmpu.le.qb */, Mips::CMPU_LE_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5844 { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5845 { 2846 /* cmpu.lt.qb */, Mips::CMPU_LT_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5846 { 2857 /* copy_s.b */, Mips::COPY_S_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 5847 { 2866 /* copy_s.d */, Mips::COPY_S_D, Convert__GPR64AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, 5848 { 2875 /* copy_s.h */, Mips::COPY_S_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 5849 { 2884 /* copy_s.w */, Mips::COPY_S_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 5850 { 2893 /* copy_u.b */, Mips::COPY_U_B, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 5851 { 2902 /* copy_u.h */, Mips::COPY_U_H, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 5852 { 2911 /* copy_u.w */, Mips::COPY_U_W, Convert__GPR32AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 5853 { 2920 /* crc32b */, Mips::CRC32B, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5854 { 2927 /* crc32cb */, Mips::CRC32CB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5855 { 2935 /* crc32cd */, Mips::CRC32CD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5856 { 2943 /* crc32ch */, Mips::CRC32CH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5857 { 2951 /* crc32cw */, Mips::CRC32CW, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5858 { 2959 /* crc32d */, Mips::CRC32D, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5859 { 2966 /* crc32h */, Mips::CRC32H, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5860 { 2973 /* crc32w */, Mips::CRC32W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5861 { 2980 /* ctc1 */, Mips::CTC1, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 5862 { 2980 /* ctc1 */, Mips::CTC1_MM, Convert__CCRAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_CCRAsmReg }, }, 5863 { 2985 /* ctc2 */, Mips::CTC2_MM, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 5864 { 2990 /* ctcmsa */, Mips::CTCMSA, Convert__MSACtrlAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSACtrlAsmReg, MCK_GPR32AsmReg }, }, 5865 { 2997 /* cttc1 */, Mips::CTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 5866 { 3003 /* cvt.d.l */, Mips::CVT_D64_L, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5867 { 3003 /* cvt.d.l */, Mips::CVT_D_L_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5868 { 3011 /* cvt.d.s */, Mips::CVT_D32_S, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 5869 { 3011 /* cvt.d.s */, Mips::CVT_D32_S_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 5870 { 3011 /* cvt.d.s */, Mips::CVT_D64_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5871 { 3011 /* cvt.d.s */, Mips::CVT_D64_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5872 { 3019 /* cvt.d.w */, Mips::CVT_D32_W, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 5873 { 3019 /* cvt.d.w */, Mips::CVT_D32_W_MM, Convert__AFGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_FGR32AsmReg }, }, 5874 { 3019 /* cvt.d.w */, Mips::CVT_D64_W, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5875 { 3019 /* cvt.d.w */, Mips::CVT_D64_W_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5876 { 3027 /* cvt.l.d */, Mips::CVT_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5877 { 3027 /* cvt.l.d */, Mips::CVT_L_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5878 { 3027 /* cvt.l.d */, Mips::CVT_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5879 { 3035 /* cvt.l.s */, Mips::CVT_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5880 { 3035 /* cvt.l.s */, Mips::CVT_L_S_MM, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5881 { 3035 /* cvt.l.s */, Mips::CVT_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5882 { 3043 /* cvt.s.d */, Mips::CVT_S_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5883 { 3043 /* cvt.s.d */, Mips::CVT_S_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5884 { 3043 /* cvt.s.d */, Mips::CVT_S_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 5885 { 3043 /* cvt.s.d */, Mips::CVT_S_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 5886 { 3051 /* cvt.s.l */, Mips::CVT_S_L, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 5887 { 3051 /* cvt.s.l */, Mips::CVT_S_L_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 5888 { 3059 /* cvt.s.w */, Mips::CVT_S_W, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5889 { 3059 /* cvt.s.w */, Mips::CVT_S_W_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5890 { 3059 /* cvt.s.w */, Mips::CVT_S_W_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5891 { 3067 /* cvt.w.d */, Mips::CVT_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5892 { 3067 /* cvt.w.d */, Mips::CVT_W_D32_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 5893 { 3067 /* cvt.w.d */, Mips::CVT_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 5894 { 3067 /* cvt.w.d */, Mips::CVT_W_D64_MM, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 5895 { 3075 /* cvt.w.s */, Mips::CVT_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5896 { 3075 /* cvt.w.s */, Mips::CVT_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5897 { 3075 /* cvt.w.s */, Mips::CVT_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5898 { 3083 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5899 { 3083 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 5900 { 3083 /* dadd */, Mips::DADD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5901 { 3083 /* dadd */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 5902 { 3088 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 5903 { 3088 /* daddi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 5904 { 3094 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 5905 { 3094 /* daddiu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 5906 { 3101 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5907 { 3101 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm16 }, }, 5908 { 3101 /* daddu */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5909 { 3101 /* daddu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm16 }, }, 5910 { 3107 /* dahi */, Mips::DAHI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, 5911 { 3112 /* dalign */, Mips::DALIGN, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm3_0 }, }, 5912 { 3119 /* dati */, Mips::DATI, Convert__GPR64AsmReg1_0__Tie0_1_2__UImm16_AltRelaxed1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16_AltRelaxed }, }, 5913 { 3124 /* daui */, Mips::DAUI, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_UImm16 }, }, 5914 { 3129 /* dbitswap */, Mips::DBITSWAP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5915 { 3138 /* dclo */, Mips::DCLO, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5916 { 3138 /* dclo */, Mips::DCLO_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5917 { 3143 /* dclz */, Mips::DCLZ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5918 { 3143 /* dclz */, Mips::DCLZ_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5919 { 3148 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5920 { 3148 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 5921 { 3148 /* ddiv */, Mips::DSDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5922 { 3148 /* ddiv */, Mips::DSDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5923 { 3148 /* ddiv */, Mips::DDIV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5924 { 3148 /* ddiv */, Mips::DSDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 5925 { 3153 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5926 { 3153 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 5927 { 3153 /* ddivu */, Mips::DUDIV, Convert__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5928 { 3153 /* ddivu */, Mips::DUDivMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5929 { 3153 /* ddivu */, Mips::DDIVU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 5930 { 3153 /* ddivu */, Mips::DUDivIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 5931 { 3159 /* deret */, Mips::DERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { }, }, 5932 { 3159 /* deret */, Mips::DERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 5933 { 3159 /* deret */, Mips::DERET_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 5934 { 3165 /* dext */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, 5935 { 3165 /* dext */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 5936 { 3165 /* dext */, Mips::DEXT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_0_Report_UImm61_2__ConstantUImm5_Plus1_Report_UImm61_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0_Report_UImm6, MCK_ConstantUImm5_Plus1_Report_UImm6 }, }, 5937 { 3170 /* dextm */, Mips::DEXTM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_331_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_33 }, }, 5938 { 3176 /* dextu */, Mips::DEXTU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 5939 { 3182 /* di */, Mips::DI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, }, 5940 { 3182 /* di */, Mips::DI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 5941 { 3182 /* di */, Mips::DI_MM, Convert__regZERO, Feature_InMicroMips, { }, }, 5942 { 3182 /* di */, Mips::DI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 5943 { 3182 /* di */, Mips::DI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 5944 { 3182 /* di */, Mips::DI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, }, 5945 { 3185 /* dins */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, 5946 { 3185 /* dins */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 5947 { 3185 /* dins */, Mips::DINS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0, MCK_ConstantUImm5_1 }, }, 5948 { 3190 /* dinsm */, Mips::DINSM, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImmRange2_641_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImmRange2_64 }, }, 5949 { 3196 /* dinsu */, Mips::DINSU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_321_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32, MCK_ConstantUImm5_1 }, }, 5950 { 3202 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5951 { 3202 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 5952 { 3202 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, 5953 { 3202 /* div */, Mips::SDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, 5954 { 3202 /* div */, Mips::DivRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, 5955 { 3202 /* div */, Mips::SDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5956 { 3202 /* div */, Mips::SDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5957 { 3202 /* div */, Mips::DIV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5958 { 3202 /* div */, Mips::DIV_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5959 { 3202 /* div */, Mips::SDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, 5960 { 3202 /* div */, Mips::SDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5961 { 3206 /* div.d */, Mips::FDIV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5962 { 3206 /* div.d */, Mips::FDIV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 5963 { 3206 /* div.d */, Mips::FDIV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5964 { 3206 /* div.d */, Mips::FDIV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 5965 { 3212 /* div.s */, Mips::FDIV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5966 { 3212 /* div.s */, Mips::FDIV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5967 { 3212 /* div.s */, Mips::FDIV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 5968 { 3218 /* div_s.b */, Mips::DIV_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5969 { 3226 /* div_s.d */, Mips::DIV_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5970 { 3234 /* div_s.h */, Mips::DIV_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5971 { 3242 /* div_s.w */, Mips::DIV_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5972 { 3250 /* div_u.b */, Mips::DIV_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5973 { 3258 /* div_u.d */, Mips::DIV_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5974 { 3266 /* div_u.h */, Mips::DIV_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5975 { 3274 /* div_u.w */, Mips::DIV_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 5976 { 3282 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5977 { 3282 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 5978 { 3282 /* divu */, Mips::UDivMacro, Convert__GPR32NonZeroAsmReg1_0__GPR32NonZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32NonZeroAsmReg, MCK_GPR32AsmReg }, }, 5979 { 3282 /* divu */, Mips::UDIV, Convert__GPR32ZeroAsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32ZeroAsmReg, MCK_GPR32AsmReg }, }, 5980 { 3282 /* divu */, Mips::DivuRxRy16, Convert__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_GPR32ZERO, MCK_CPU16Regs, MCK_CPU16Regs }, }, 5981 { 3282 /* divu */, Mips::UDIV, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5982 { 3282 /* divu */, Mips::UDIV_MM, Convert__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32ZERO, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5983 { 3282 /* divu */, Mips::UDivMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5984 { 3282 /* divu */, Mips::DIVU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5985 { 3282 /* divu */, Mips::DIVU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 5986 { 3282 /* divu */, Mips::UDivIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm321_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32 }, }, 5987 { 3287 /* dla */, Mips::LoadAddrImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, }, 5988 { 3287 /* dla */, Mips::LoadAddrReg64, Convert__GPR64AsmReg1_0__Mem2_1, 0, { MCK_GPR64AsmReg, MCK_Mem }, }, 5989 { 3291 /* dli */, Mips::LoadImm64, Convert__GPR64AsmReg1_0__Imm1_1, 0, { MCK_GPR64AsmReg, MCK_Imm }, }, 5990 { 3295 /* dlsa */, Mips::DLSA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, 5991 { 3295 /* dlsa */, Mips::DLSA_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm2_1 }, }, 5992 { 3300 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 5993 { 3300 /* dmfc0 */, Mips::DMFC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 5994 { 3306 /* dmfc1 */, Mips::DMFC1, Convert__GPR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, 5995 { 3312 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, 5996 { 3312 /* dmfc2 */, Mips::DMFC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, 5997 { 3312 /* dmfc2 */, Mips::DMFC2, Convert__GPR64AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 5998 { 3318 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 5999 { 3318 /* dmfgc0 */, Mips::DMFGC0, Convert__GPR64AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6000 { 3325 /* dmod */, Mips::DMOD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6001 { 3330 /* dmodu */, Mips::DMODU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6002 { 3336 /* dmt */, Mips::DMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, }, 6003 { 3336 /* dmt */, Mips::DMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6004 { 3340 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 6005 { 3340 /* dmtc0 */, Mips::DMTC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6006 { 3346 /* dmtc1 */, Mips::DMTC1, Convert__FGR64AsmReg1_1__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_FGR64AsmReg }, }, 6007 { 3352 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__imm_95_0, 0, { MCK_GPR64AsmReg, MCK_COP2AsmReg }, }, 6008 { 3352 /* dmtc2 */, Mips::DMTC2_OCTEON, Convert__GPR64AsmReg1_0__UImm161_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_UImm16 }, }, 6009 { 3352 /* dmtc2 */, Mips::DMTC2, Convert__COP2AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasMips64, { MCK_GPR64AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 6010 { 3358 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_COP0AsmReg }, }, 6011 { 3358 /* dmtgc0 */, Mips::DMTGC0, Convert__COP0AsmReg1_1__GPR64AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, { MCK_GPR64AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6012 { 3365 /* dmuh */, Mips::DMUH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6013 { 3370 /* dmuhu */, Mips::DMUHU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6014 { 3376 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6015 { 3376 /* dmul */, Mips::DMULMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6016 { 3376 /* dmul */, Mips::DMUL_R6, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6017 { 3376 /* dmul */, Mips::DMUL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6018 { 3376 /* dmul */, Mips::DMULImmMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6019 { 3381 /* dmulo */, Mips::DMULOMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6020 { 3387 /* dmulou */, Mips::DMULOUMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6021 { 3394 /* dmult */, Mips::DMULT, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6022 { 3400 /* dmultu */, Mips::DMULTu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6023 { 3407 /* dmulu */, Mips::DMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6024 { 3413 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6025 { 3413 /* dneg */, Mips::DSUB, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6026 { 3418 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6027 { 3418 /* dnegu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__regZERO_64__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6028 { 3424 /* dotp_s.d */, Mips::DOTP_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6029 { 3433 /* dotp_s.h */, Mips::DOTP_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6030 { 3442 /* dotp_s.w */, Mips::DOTP_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6031 { 3451 /* dotp_u.d */, Mips::DOTP_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6032 { 3460 /* dotp_u.h */, Mips::DOTP_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6033 { 3469 /* dotp_u.w */, Mips::DOTP_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6034 { 3478 /* dpa.w.ph */, Mips::DPA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6035 { 3478 /* dpa.w.ph */, Mips::DPA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6036 { 3487 /* dpadd_s.d */, Mips::DPADD_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6037 { 3497 /* dpadd_s.h */, Mips::DPADD_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6038 { 3507 /* dpadd_s.w */, Mips::DPADD_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6039 { 3517 /* dpadd_u.d */, Mips::DPADD_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6040 { 3527 /* dpadd_u.h */, Mips::DPADD_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6041 { 3537 /* dpadd_u.w */, Mips::DPADD_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6042 { 3547 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6043 { 3547 /* dpaq_s.w.ph */, Mips::DPAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6044 { 3559 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6045 { 3559 /* dpaq_sa.l.w */, Mips::DPAQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6046 { 3571 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6047 { 3571 /* dpaqx_s.w.ph */, Mips::DPAQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6048 { 3584 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6049 { 3584 /* dpaqx_sa.w.ph */, Mips::DPAQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6050 { 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6051 { 3598 /* dpau.h.qbl */, Mips::DPAU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6052 { 3609 /* dpau.h.qbr */, Mips::DPAU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6053 { 3609 /* dpau.h.qbr */, Mips::DPAU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6054 { 3620 /* dpax.w.ph */, Mips::DPAX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6055 { 3620 /* dpax.w.ph */, Mips::DPAX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6056 { 3630 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6057 { 3630 /* dpop */, Mips::DPOP, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6058 { 3635 /* dps.w.ph */, Mips::DPS_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6059 { 3635 /* dps.w.ph */, Mips::DPS_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6060 { 3644 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6061 { 3644 /* dpsq_s.w.ph */, Mips::DPSQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6062 { 3656 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6063 { 3656 /* dpsq_sa.l.w */, Mips::DPSQ_SA_L_W, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6064 { 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6065 { 3668 /* dpsqx_s.w.ph */, Mips::DPSQX_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6066 { 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6067 { 3681 /* dpsqx_sa.w.ph */, Mips::DPSQX_SA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6068 { 3695 /* dpsu.h.qbl */, Mips::DPSU_H_QBL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6069 { 3695 /* dpsu.h.qbl */, Mips::DPSU_H_QBL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6070 { 3706 /* dpsu.h.qbr */, Mips::DPSU_H_QBR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6071 { 3706 /* dpsu.h.qbr */, Mips::DPSU_H_QBR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6072 { 3717 /* dpsub_s.d */, Mips::DPSUB_S_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6073 { 3727 /* dpsub_s.h */, Mips::DPSUB_S_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6074 { 3737 /* dpsub_s.w */, Mips::DPSUB_S_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6075 { 3747 /* dpsub_u.d */, Mips::DPSUB_U_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6076 { 3757 /* dpsub_u.h */, Mips::DPSUB_U_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6077 { 3767 /* dpsub_u.w */, Mips::DPSUB_U_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6078 { 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6079 { 3777 /* dpsx.w.ph */, Mips::DPSX_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6080 { 3787 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6081 { 3787 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6082 { 3787 /* drem */, Mips::DSRemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6083 { 3787 /* drem */, Mips::DSRemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6084 { 3792 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6085 { 3792 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6086 { 3792 /* dremu */, Mips::DURemMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6087 { 3792 /* dremu */, Mips::DURemIMacro, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_SImm32_Relaxed }, }, 6088 { 3798 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6089 { 3798 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 6090 { 3798 /* drol */, Mips::DROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6091 { 3798 /* drol */, Mips::DROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 6092 { 3803 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6093 { 3803 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 6094 { 3803 /* dror */, Mips::DROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6095 { 3803 /* dror */, Mips::DRORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_HasMips64, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 6096 { 3808 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6097 { 3808 /* drotr */, Mips::DROTR, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6098 { 3814 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6099 { 3814 /* drotr32 */, Mips::DROTR32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6100 { 3822 /* drotrv */, Mips::DROTRV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6101 { 3829 /* dsbh */, Mips::DSBH, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6102 { 3834 /* dshd */, Mips::DSHD, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6103 { 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6104 { 3839 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6105 { 3839 /* dsll */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6106 { 3839 /* dsll */, Mips::DSLL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6107 { 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6108 { 3844 /* dsll32 */, Mips::DSLL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6109 { 3851 /* dsllv */, Mips::DSLLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6110 { 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6111 { 3857 /* dsra */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6112 { 3857 /* dsra */, Mips::DSRA, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6113 { 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6114 { 3862 /* dsra32 */, Mips::DSRA32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6115 { 3869 /* dsrav */, Mips::DSRAV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6116 { 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6117 { 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm6_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6118 { 3875 /* dsrl */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6119 { 3875 /* dsrl */, Mips::DSRL, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm6_0 }, }, 6120 { 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6121 { 3880 /* dsrl32 */, Mips::DSRL32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0 }, }, 6122 { 3887 /* dsrlv */, Mips::DSRLV, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR32AsmReg }, }, 6123 { 3893 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6124 { 3893 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, 6125 { 3893 /* dsub */, Mips::DSUB, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6126 { 3893 /* dsub */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, 6127 { 3898 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_InvNum }, }, 6128 { 3898 /* dsubi */, Mips::DADDi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, 6129 { 3904 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6130 { 3904 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_InvNum }, }, 6131 { 3904 /* dsubu */, Mips::DSUBu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6132 { 3904 /* dsubu */, Mips::DADDiu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_InvNum }, }, 6133 { 3910 /* dvp */, Mips::DVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, { }, }, 6134 { 3910 /* dvp */, Mips::DVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6135 { 3910 /* dvp */, Mips::DVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6136 { 3910 /* dvp */, Mips::DVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6137 { 3914 /* dvpe */, Mips::DVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, }, 6138 { 3914 /* dvpe */, Mips::DVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6139 { 3919 /* ehb */, Mips::EHB, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 6140 { 3919 /* ehb */, Mips::EHB_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6141 { 3919 /* ehb */, Mips::EHB_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 6142 { 3923 /* ei */, Mips::EI, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, }, 6143 { 3923 /* ei */, Mips::EI_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6144 { 3923 /* ei */, Mips::EI_MM, Convert__regZERO, Feature_InMicroMips, { }, }, 6145 { 3923 /* ei */, Mips::EI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6146 { 3923 /* ei */, Mips::EI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6147 { 3923 /* ei */, Mips::EI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, }, 6148 { 3926 /* emt */, Mips::EMT, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, }, 6149 { 3926 /* emt */, Mips::EMT, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6150 { 3930 /* eret */, Mips::ERET, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, { }, }, 6151 { 3930 /* eret */, Mips::ERET_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6152 { 3930 /* eret */, Mips::ERET_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 6153 { 3935 /* eretnc */, Mips::ERETNC, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_NotInMicroMips, { }, }, 6154 { 3935 /* eretnc */, Mips::ERETNC_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6155 { 3942 /* evp */, Mips::EVP, Convert__regZERO, Feature_HasStdEnc|Feature_HasMips32r6, { }, }, 6156 { 3942 /* evp */, Mips::EVP_MMR6, Convert__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6157 { 3942 /* evp */, Mips::EVP, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6158 { 3942 /* evp */, Mips::EVP_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6159 { 3946 /* evpe */, Mips::EVPE, Convert__regZERO, Feature_HasMT|Feature_NotInMicroMips, { }, }, 6160 { 3946 /* evpe */, Mips::EVPE, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6161 { 3951 /* ext */, Mips::EXT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6162 { 3951 /* ext */, Mips::EXT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6163 { 3951 /* ext */, Mips::EXT_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6164 { 3955 /* extp */, Mips::EXTP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6165 { 3955 /* extp */, Mips::EXTP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6166 { 3960 /* extpdp */, Mips::EXTPDP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6167 { 3960 /* extpdp */, Mips::EXTPDP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6168 { 3967 /* extpdpv */, Mips::EXTPDPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6169 { 3967 /* extpdpv */, Mips::EXTPDPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6170 { 3975 /* extpv */, Mips::EXTPV_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6171 { 3975 /* extpv */, Mips::EXTPV, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6172 { 3981 /* extr.w */, Mips::EXTR_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6173 { 3981 /* extr.w */, Mips::EXTR_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6174 { 3988 /* extr_r.w */, Mips::EXTR_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6175 { 3988 /* extr_r.w */, Mips::EXTR_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6176 { 3997 /* extr_rs.w */, Mips::EXTR_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6177 { 3997 /* extr_rs.w */, Mips::EXTR_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6178 { 4007 /* extr_s.h */, Mips::EXTR_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6179 { 4007 /* extr_s.h */, Mips::EXTR_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_ConstantUImm5_0 }, }, 6180 { 4016 /* extrv.w */, Mips::EXTRV_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6181 { 4016 /* extrv.w */, Mips::EXTRV_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6182 { 4024 /* extrv_r.w */, Mips::EXTRV_R_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6183 { 4024 /* extrv_r.w */, Mips::EXTRV_R_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6184 { 4034 /* extrv_rs.w */, Mips::EXTRV_RS_W_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6185 { 4034 /* extrv_rs.w */, Mips::EXTRV_RS_W, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6186 { 4045 /* extrv_s.h */, Mips::EXTRV_S_H_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6187 { 4045 /* extrv_s.h */, Mips::EXTRV_S_H, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 6188 { 4055 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6189 { 4055 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_32_Norm1_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 6190 { 4055 /* exts */, Mips::EXTS, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6191 { 4055 /* exts */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_32_Norm1_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_32_Norm, MCK_ConstantUImm5_0 }, }, 6192 { 4060 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantUImm5_01_1__ConstantUImm5_01_2, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6193 { 4060 /* exts32 */, Mips::EXTS32, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_01_3, Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_0 }, }, 6194 { 4067 /* fadd.d */, Mips::FADD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6195 { 4074 /* fadd.w */, Mips::FADD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6196 { 4081 /* fcaf.d */, Mips::FCAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6197 { 4088 /* fcaf.w */, Mips::FCAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6198 { 4095 /* fceq.d */, Mips::FCEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6199 { 4102 /* fceq.w */, Mips::FCEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6200 { 4109 /* fclass.d */, Mips::FCLASS_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6201 { 4118 /* fclass.w */, Mips::FCLASS_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6202 { 4127 /* fcle.d */, Mips::FCLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6203 { 4134 /* fcle.w */, Mips::FCLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6204 { 4141 /* fclt.d */, Mips::FCLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6205 { 4148 /* fclt.w */, Mips::FCLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6206 { 4155 /* fcne.d */, Mips::FCNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6207 { 4162 /* fcne.w */, Mips::FCNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6208 { 4169 /* fcor.d */, Mips::FCOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6209 { 4176 /* fcor.w */, Mips::FCOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6210 { 4183 /* fcueq.d */, Mips::FCUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6211 { 4191 /* fcueq.w */, Mips::FCUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6212 { 4199 /* fcule.d */, Mips::FCULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6213 { 4207 /* fcule.w */, Mips::FCULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6214 { 4215 /* fcult.d */, Mips::FCULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6215 { 4223 /* fcult.w */, Mips::FCULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6216 { 4231 /* fcun.d */, Mips::FCUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6217 { 4238 /* fcun.w */, Mips::FCUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6218 { 4245 /* fcune.d */, Mips::FCUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6219 { 4253 /* fcune.w */, Mips::FCUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6220 { 4261 /* fdiv.d */, Mips::FDIV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6221 { 4268 /* fdiv.w */, Mips::FDIV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6222 { 4275 /* fexdo.h */, Mips::FEXDO_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6223 { 4283 /* fexdo.w */, Mips::FEXDO_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6224 { 4291 /* fexp2.d */, Mips::FEXP2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6225 { 4299 /* fexp2.w */, Mips::FEXP2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6226 { 4307 /* fexupl.d */, Mips::FEXUPL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6227 { 4316 /* fexupl.w */, Mips::FEXUPL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6228 { 4325 /* fexupr.d */, Mips::FEXUPR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6229 { 4334 /* fexupr.w */, Mips::FEXUPR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6230 { 4343 /* ffint_s.d */, Mips::FFINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6231 { 4353 /* ffint_s.w */, Mips::FFINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6232 { 4363 /* ffint_u.d */, Mips::FFINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6233 { 4373 /* ffint_u.w */, Mips::FFINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6234 { 4383 /* ffql.d */, Mips::FFQL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6235 { 4390 /* ffql.w */, Mips::FFQL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6236 { 4397 /* ffqr.d */, Mips::FFQR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6237 { 4404 /* ffqr.w */, Mips::FFQR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6238 { 4411 /* fill.b */, Mips::FILL_B, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, 6239 { 4418 /* fill.d */, Mips::FILL_D, Convert__MSA128AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK_GPR64AsmReg }, }, 6240 { 4425 /* fill.h */, Mips::FILL_H, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, 6241 { 4432 /* fill.w */, Mips::FILL_W, Convert__MSA128AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_GPR32AsmReg }, }, 6242 { 4439 /* flog2.d */, Mips::FLOG2_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6243 { 4447 /* flog2.w */, Mips::FLOG2_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6244 { 4455 /* floor.l.d */, Mips::FLOOR_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6245 { 4455 /* floor.l.d */, Mips::FLOOR_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6246 { 4465 /* floor.l.s */, Mips::FLOOR_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6247 { 4465 /* floor.l.s */, Mips::FLOOR_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 6248 { 4475 /* floor.w.d */, Mips::FLOOR_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6249 { 4475 /* floor.w.d */, Mips::FLOOR_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6250 { 4475 /* floor.w.d */, Mips::FLOOR_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 6251 { 4475 /* floor.w.d */, Mips::FLOOR_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 6252 { 4485 /* floor.w.s */, Mips::FLOOR_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6253 { 4485 /* floor.w.s */, Mips::FLOOR_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6254 { 4485 /* floor.w.s */, Mips::FLOOR_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6255 { 4495 /* fmadd.d */, Mips::FMADD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6256 { 4503 /* fmadd.w */, Mips::FMADD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6257 { 4511 /* fmax.d */, Mips::FMAX_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6258 { 4518 /* fmax.w */, Mips::FMAX_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6259 { 4525 /* fmax_a.d */, Mips::FMAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6260 { 4534 /* fmax_a.w */, Mips::FMAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6261 { 4543 /* fmin.d */, Mips::FMIN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6262 { 4550 /* fmin.w */, Mips::FMIN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6263 { 4557 /* fmin_a.d */, Mips::FMIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6264 { 4566 /* fmin_a.w */, Mips::FMIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6265 { 4575 /* fmsub.d */, Mips::FMSUB_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6266 { 4583 /* fmsub.w */, Mips::FMSUB_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6267 { 4591 /* fmul.d */, Mips::FMUL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6268 { 4598 /* fmul.w */, Mips::FMUL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6269 { 4605 /* fork */, Mips::FORK, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6270 { 4610 /* frcp.d */, Mips::FRCP_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6271 { 4617 /* frcp.w */, Mips::FRCP_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6272 { 4624 /* frint.d */, Mips::FRINT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6273 { 4632 /* frint.w */, Mips::FRINT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6274 { 4640 /* frsqrt.d */, Mips::FRSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6275 { 4649 /* frsqrt.w */, Mips::FRSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6276 { 4658 /* fsaf.d */, Mips::FSAF_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6277 { 4665 /* fsaf.w */, Mips::FSAF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6278 { 4672 /* fseq.d */, Mips::FSEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6279 { 4679 /* fseq.w */, Mips::FSEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6280 { 4686 /* fsle.d */, Mips::FSLE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6281 { 4693 /* fsle.w */, Mips::FSLE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6282 { 4700 /* fslt.d */, Mips::FSLT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6283 { 4707 /* fslt.w */, Mips::FSLT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6284 { 4714 /* fsne.d */, Mips::FSNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6285 { 4721 /* fsne.w */, Mips::FSNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6286 { 4728 /* fsor.d */, Mips::FSOR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6287 { 4735 /* fsor.w */, Mips::FSOR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6288 { 4742 /* fsqrt.d */, Mips::FSQRT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6289 { 4750 /* fsqrt.w */, Mips::FSQRT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6290 { 4758 /* fsub.d */, Mips::FSUB_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6291 { 4765 /* fsub.w */, Mips::FSUB_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6292 { 4772 /* fsueq.d */, Mips::FSUEQ_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6293 { 4780 /* fsueq.w */, Mips::FSUEQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6294 { 4788 /* fsule.d */, Mips::FSULE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6295 { 4796 /* fsule.w */, Mips::FSULE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6296 { 4804 /* fsult.d */, Mips::FSULT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6297 { 4812 /* fsult.w */, Mips::FSULT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6298 { 4820 /* fsun.d */, Mips::FSUN_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6299 { 4827 /* fsun.w */, Mips::FSUN_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6300 { 4834 /* fsune.d */, Mips::FSUNE_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6301 { 4842 /* fsune.w */, Mips::FSUNE_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6302 { 4850 /* ftint_s.d */, Mips::FTINT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6303 { 4860 /* ftint_s.w */, Mips::FTINT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6304 { 4870 /* ftint_u.d */, Mips::FTINT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6305 { 4880 /* ftint_u.w */, Mips::FTINT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6306 { 4890 /* ftq.h */, Mips::FTQ_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6307 { 4896 /* ftq.w */, Mips::FTQ_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6308 { 4902 /* ftrunc_s.d */, Mips::FTRUNC_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6309 { 4913 /* ftrunc_s.w */, Mips::FTRUNC_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6310 { 4924 /* ftrunc_u.d */, Mips::FTRUNC_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6311 { 4935 /* ftrunc_u.w */, Mips::FTRUNC_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6312 { 4946 /* ginvi */, Mips::GINVI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6313 { 4946 /* ginvi */, Mips::GINVI_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg }, }, 6314 { 4952 /* ginvt */, Mips::GINVT, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 6315 { 4952 /* ginvt */, Mips::GINVT_MMR6, Convert__GPR32AsmReg1_0__ConstantUImm2_01_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, { MCK_GPR32AsmReg, MCK_ConstantUImm2_0 }, }, 6316 { 4958 /* hadd_s.d */, Mips::HADD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6317 { 4967 /* hadd_s.h */, Mips::HADD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6318 { 4976 /* hadd_s.w */, Mips::HADD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6319 { 4985 /* hadd_u.d */, Mips::HADD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6320 { 4994 /* hadd_u.h */, Mips::HADD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6321 { 5003 /* hadd_u.w */, Mips::HADD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6322 { 5012 /* hsub_s.d */, Mips::HSUB_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6323 { 5021 /* hsub_s.h */, Mips::HSUB_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6324 { 5030 /* hsub_s.w */, Mips::HSUB_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6325 { 5039 /* hsub_u.d */, Mips::HSUB_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6326 { 5048 /* hsub_u.h */, Mips::HSUB_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6327 { 5057 /* hsub_u.w */, Mips::HSUB_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6328 { 5066 /* hypcall */, Mips::HYPCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 6329 { 5066 /* hypcall */, Mips::HYPCALL_MM, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 6330 { 5066 /* hypcall */, Mips::HYPCALL, Convert__ConstantUImm10_01_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_ConstantUImm10_0 }, }, 6331 { 5066 /* hypcall */, Mips::HYPCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_ConstantUImm10_0 }, }, 6332 { 5074 /* ilvev.b */, Mips::ILVEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6333 { 5082 /* ilvev.d */, Mips::ILVEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6334 { 5090 /* ilvev.h */, Mips::ILVEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6335 { 5098 /* ilvev.w */, Mips::ILVEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6336 { 5106 /* ilvl.b */, Mips::ILVL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6337 { 5113 /* ilvl.d */, Mips::ILVL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6338 { 5120 /* ilvl.h */, Mips::ILVL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6339 { 5127 /* ilvl.w */, Mips::ILVL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6340 { 5134 /* ilvod.b */, Mips::ILVOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6341 { 5142 /* ilvod.d */, Mips::ILVOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6342 { 5150 /* ilvod.h */, Mips::ILVOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6343 { 5158 /* ilvod.w */, Mips::ILVOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6344 { 5166 /* ilvr.b */, Mips::ILVR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6345 { 5173 /* ilvr.d */, Mips::ILVR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6346 { 5180 /* ilvr.h */, Mips::ILVR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6347 { 5187 /* ilvr.w */, Mips::ILVR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6348 { 5194 /* ins */, Mips::INS, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6349 { 5194 /* ins */, Mips::INS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6350 { 5194 /* ins */, Mips::INS_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__ConstantUImm5_11_3__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0, MCK_ConstantUImm5_1 }, }, 6351 { 5198 /* insert.b */, Mips::INSERT_B, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_GPR32AsmReg }, }, 6352 { 5207 /* insert.d */, Mips::INSERT_D, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR64AsmReg1_4__ConstantUImm1_01_2, Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_GPR64AsmReg }, }, 6353 { 5216 /* insert.h */, Mips::INSERT_H, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_GPR32AsmReg }, }, 6354 { 5225 /* insert.w */, Mips::INSERT_W, Convert__MSA128AsmReg1_0__Tie0_1_1__GPR32AsmReg1_4__ConstantUImm2_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_GPR32AsmReg }, }, 6355 { 5234 /* insv */, Mips::INSV_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6356 { 5234 /* insv */, Mips::INSV, Convert__GPR32AsmReg1_0__Tie0_1_1__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6357 { 5239 /* insve.b */, Mips::INSVE_B, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm4_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6358 { 5247 /* insve.d */, Mips::INSVE_D, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm1_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6359 { 5255 /* insve.h */, Mips::INSVE_H, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm3_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6360 { 5263 /* insve.w */, Mips::INSVE_W, Convert__MSA128AsmReg1_0__Tie0_1_1__ConstantUImm2_01_2__MSA128AsmReg1_4__ConstantImmz1_6, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantImmz, MCK__93_ }, }, 6361 { 5271 /* j */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6362 { 5271 /* j */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6363 { 5271 /* j */, Mips::J_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, }, 6364 { 5271 /* j */, Mips::J, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 6365 { 5273 /* jal */, Mips::JalOneReg, Convert__GPR32AsmReg1_0, 0, { MCK_GPR32AsmReg }, }, 6366 { 5273 /* jal */, Mips::JAL_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, }, 6367 { 5273 /* jal */, Mips::JAL, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 6368 { 5273 /* jal */, Mips::BALC_MMR6, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_JumpTarget }, }, 6369 { 5273 /* jal */, Mips::JalTwoReg, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6370 { 5277 /* jalr */, Mips::JALR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6371 { 5277 /* jalr */, Mips::JALRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6372 { 5277 /* jalr */, Mips::JALR, Convert__regRA__GPR32AsmReg1_0, Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6373 { 5277 /* jalr */, Mips::JALR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6374 { 5277 /* jalr */, Mips::JALR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6375 { 5277 /* jalr */, Mips::JALR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_NotInMips16Mode, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6376 { 5282 /* jalr.hb */, Mips::JALR_HB, Convert__regRA__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6377 { 5282 /* jalr.hb */, Mips::JALR_HB64, Convert__regRA_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6378 { 5282 /* jalr.hb */, Mips::JALR_HB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6379 { 5282 /* jalr.hb */, Mips::JALR_HB64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6380 { 5290 /* jalrc */, Mips::JumpLinkReg16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, }, 6381 { 5290 /* jalrc */, Mips::JIALC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6382 { 5290 /* jalrc */, Mips::JALRC_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6383 { 5290 /* jalrc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, }, 6384 { 5290 /* jalrc */, Mips::JALRC_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6385 { 5296 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__regRA__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6386 { 5296 /* jalrc.hb */, Mips::JALRC_HB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6387 { 5305 /* jalrs */, Mips::JALRS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6388 { 5311 /* jalrs16 */, Mips::JALRS16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6389 { 5319 /* jals */, Mips::JALS_MM, Convert__Imm1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_Imm }, }, 6390 { 5324 /* jalx */, Mips::JALX, Convert__JumpTarget1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_JumpTarget }, }, 6391 { 5324 /* jalx */, Mips::JALX_MM, Convert__JumpTarget1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_JumpTarget }, }, 6392 { 5329 /* jialc */, Mips::JIALC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6393 { 5329 /* jialc */, Mips::JIALC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6394 { 5329 /* jialc */, Mips::JIALC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 6395 { 5335 /* jic */, Mips::JIC, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6396 { 5335 /* jic */, Mips::JIC_MMR6, Convert__GPR32AsmReg1_0__JumpTarget1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_JumpTarget }, }, 6397 { 5335 /* jic */, Mips::JIC64, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 6398 { 5339 /* jr */, Mips::JrRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, }, 6399 { 5339 /* jr */, Mips::JR, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6400 { 5339 /* jr */, Mips::JALR, Convert__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6401 { 5339 /* jr */, Mips::JR_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6402 { 5339 /* jr */, Mips::JR64, Convert__GPR64AsmReg1_0, Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6403 { 5339 /* jr */, Mips::JALR64, Convert__regZERO_64__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, }, 6404 { 5342 /* jr.hb */, Mips::JR_HB, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg }, }, 6405 { 5342 /* jr.hb */, Mips::JR_HB_R6, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6406 { 5342 /* jr.hb */, Mips::JR_HB64, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg }, }, 6407 { 5342 /* jr.hb */, Mips::JR_HB64_R6, Convert__GPR64AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg }, }, 6408 { 5348 /* jr16 */, Mips::JR16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6409 { 5353 /* jraddiusp */, Mips::JRADDIUSP, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_UImm5Lsl2 }, }, 6410 { 5363 /* jrc */, Mips::JrcRa16, Convert_NoOperands, Feature_InMips16Mode, { MCK_CPURAReg }, }, 6411 { 5363 /* jrc */, Mips::JrcRx16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, }, 6412 { 5363 /* jrc */, Mips::JIC, Convert__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6413 { 5363 /* jrc */, Mips::JRC16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6414 { 5363 /* jrc */, Mips::JIC64, Convert__GPR64AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg }, }, 6415 { 5367 /* jrc16 */, Mips::JRC16_MMR6, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6416 { 5373 /* jrcaddiusp */, Mips::JRCADDIUSP_MMR6, Convert__UImm5Lsl21_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_UImm5Lsl2 }, }, 6417 { 5384 /* l.d */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6418 { 5384 /* l.d */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6419 { 5388 /* l.s */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 6420 { 5392 /* la */, Mips::LoadAddrImm32, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, }, 6421 { 5392 /* la */, Mips::LoadAddrReg32, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, }, 6422 { 5395 /* lapc */, Mips::ADDIUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6423 { 5395 /* lapc */, Mips::ADDIUPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6424 { 5400 /* lb */, Mips::LB_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6425 { 5400 /* lb */, Mips::LB_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6426 { 5400 /* lb */, Mips::LB, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6427 { 5403 /* lbe */, Mips::LBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6428 { 5403 /* lbe */, Mips::LBE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, 6429 { 5407 /* lbu */, Mips::LBU_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6430 { 5407 /* lbu */, Mips::LBu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6431 { 5407 /* lbu */, Mips::LBu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6432 { 5411 /* lbu16 */, Mips::LBU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, 6433 { 5417 /* lbue */, Mips::LBuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6434 { 5417 /* lbue */, Mips::LBuE_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_Mem }, }, 6435 { 5422 /* lbux */, Mips::LBUX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6436 { 5422 /* lbux */, Mips::LBUX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6437 { 5427 /* ld */, Mips::LDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 6438 { 5427 /* ld */, Mips::LD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6439 { 5430 /* ld.b */, Mips::LD_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, }, 6440 { 5435 /* ld.d */, Mips::LD_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, 6441 { 5440 /* ld.h */, Mips::LD_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, 6442 { 5445 /* ld.w */, Mips::LD_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, 6443 { 5450 /* ldc1 */, Mips::LDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6444 { 5450 /* ldc1 */, Mips::LDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6445 { 5450 /* ldc1 */, Mips::LDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6446 { 5450 /* ldc1 */, Mips::LDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 6447 { 5455 /* ldc2 */, Mips::LDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 6448 { 5455 /* ldc2 */, Mips::LDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 6449 { 5455 /* ldc2 */, Mips::LDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 6450 { 5460 /* ldc3 */, Mips::LDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 6451 { 5465 /* ldi.b */, Mips::LDI_B, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6452 { 5471 /* ldi.d */, Mips::LDI_D, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6453 { 5477 /* ldi.h */, Mips::LDI_H, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6454 { 5483 /* ldi.w */, Mips::LDI_W, Convert__MSA128AsmReg1_0__ConstantSImm10_01_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_ConstantSImm10_0 }, }, 6455 { 5489 /* ldl */, Mips::LDL, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 6456 { 5493 /* ldpc */, Mips::LDPC, Convert__GPR64AsmReg1_0__JumpTarget1_1, Feature_HasStdEnc|Feature_HasMips64r6, { MCK_GPR64AsmReg, MCK_JumpTarget }, }, 6457 { 5498 /* ldr */, Mips::LDR, Convert__GPR64AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 6458 { 5502 /* ldxc1 */, Mips::LDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6459 { 5502 /* ldxc1 */, Mips::LDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6460 { 5508 /* lh */, Mips::LH, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6461 { 5508 /* lh */, Mips::LH_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6462 { 5511 /* lhe */, Mips::LHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6463 { 5511 /* lhe */, Mips::LHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6464 { 5515 /* lhu */, Mips::LHu, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6465 { 5515 /* lhu */, Mips::LHu_MM, Convert__GPR32AsmReg1_0__MemOffsetSimmPtr2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimmPtr }, }, 6466 { 5519 /* lhu16 */, Mips::LHU16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, 6467 { 5525 /* lhue */, Mips::LHuE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6468 { 5525 /* lhue */, Mips::LHuE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6469 { 5530 /* lhx */, Mips::LHX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6470 { 5530 /* lhx */, Mips::LHX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6471 { 5534 /* li */, Mips::LiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 6472 { 5534 /* li */, Mips::LoadImm32, Convert__GPR32AsmReg1_0__UImm32_Coerced1_1, 0, { MCK_GPR32AsmReg, MCK_UImm32_Coerced }, }, 6473 { 5534 /* li */, Mips::LiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 6474 { 5537 /* li.d */, Mips::LoadImmDoubleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, }, 6475 { 5537 /* li.d */, Mips::LoadImmDoubleFGR_32, Convert__StrictlyAFGR64AsmReg1_0__Imm1_1, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyAFGR64AsmReg, MCK_Imm }, }, 6476 { 5537 /* li.d */, Mips::LoadImmDoubleFGR, Convert__StrictlyFGR64AsmReg1_0__Imm1_1, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_StrictlyFGR64AsmReg, MCK_Imm }, }, 6477 { 5542 /* li.s */, Mips::LoadImmSingleGPR, Convert__GPR32AsmReg1_0__Imm1_1, 0, { MCK_GPR32AsmReg, MCK_Imm }, }, 6478 { 5542 /* li.s */, Mips::LoadImmSingleFGR, Convert__StrictlyFGR32AsmReg1_0__Imm1_1, Feature_IsNotSoftFloat, { MCK_StrictlyFGR32AsmReg, MCK_Imm }, }, 6479 { 5547 /* li16 */, Mips::LI16_MM, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, 6480 { 5547 /* li16 */, Mips::LI16_MMR6, Convert__GPRMM16AsmReg1_0__UImm7_N11_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_UImm7_N1 }, }, 6481 { 5552 /* ll */, Mips::LL64_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6482 { 5552 /* ll */, Mips::LL_R6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6483 { 5552 /* ll */, Mips::LL_MMR6, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6484 { 5552 /* ll */, Mips::LL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6485 { 5552 /* ll */, Mips::LL64, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6486 { 5552 /* ll */, Mips::LL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6487 { 5555 /* lld */, Mips::LLD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6488 { 5555 /* lld */, Mips::LLD_R6, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 6489 { 5559 /* lle */, Mips::LLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6490 { 5559 /* lle */, Mips::LLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6491 { 5563 /* lsa */, Mips::LSA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, 6492 { 5563 /* lsa */, Mips::LSA_MMR6, Convert__GPR32AsmReg1_2__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm2_11_3, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, 6493 { 5563 /* lsa */, Mips::LSA_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__ConstantUImm2_11_3, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm2_1 }, }, 6494 { 5567 /* lui */, Mips::LUI_MMR6, Convert__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 6495 { 5567 /* lui */, Mips::LUi, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, 6496 { 5567 /* lui */, Mips::LUi_MM, Convert__GPR32AsmReg1_0__UImm16_Relaxed1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16_Relaxed }, }, 6497 { 5571 /* luxc1 */, Mips::LUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6498 { 5571 /* luxc1 */, Mips::LUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6499 { 5571 /* luxc1 */, Mips::LUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6500 { 5577 /* lw */, Mips::LwRxPcTcpX16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm }, }, 6501 { 5577 /* lw */, Mips::LWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 6502 { 5577 /* lw */, Mips::LW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6503 { 5577 /* lw */, Mips::LWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 6504 { 5577 /* lw */, Mips::LWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 6505 { 5577 /* lw */, Mips::LW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6506 { 5577 /* lw */, Mips::LW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6507 { 5577 /* lw */, Mips::LWGP_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMemGP2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMemGP }, }, 6508 { 5577 /* lw */, Mips::LwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, 6509 { 5577 /* lw */, Mips::LwRxPcTcp16, Convert__Reg1_0__Imm1_1__imm_95_0, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_Imm, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 6510 { 5580 /* lw16 */, Mips::LW16_MM, Convert__GPRMM16AsmReg1_0__MicroMipsMem2_1, Feature_InMicroMips, { MCK_GPRMM16AsmReg, MCK_MicroMipsMem }, }, 6511 { 5585 /* lwc1 */, Mips::LWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 6512 { 5585 /* lwc1 */, Mips::LWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 6513 { 5590 /* lwc2 */, Mips::LWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 6514 { 5590 /* lwc2 */, Mips::LWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 6515 { 5590 /* lwc2 */, Mips::LWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 6516 { 5595 /* lwc3 */, Mips::LWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 6517 { 5600 /* lwe */, Mips::LWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6518 { 5600 /* lwe */, Mips::LWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6519 { 5604 /* lwl */, Mips::LWL, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6520 { 5604 /* lwl */, Mips::LWL_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6521 { 5608 /* lwle */, Mips::LWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6522 { 5608 /* lwle */, Mips::LWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6523 { 5613 /* lwm */, Mips::LWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, }, 6524 { 5617 /* lwm16 */, Mips::LWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 6525 { 5617 /* lwm16 */, Mips::LWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 6526 { 5623 /* lwm32 */, Mips::LWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, }, 6527 { 5629 /* lwp */, Mips::LWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, }, 6528 { 5633 /* lwpc */, Mips::LWPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6529 { 5633 /* lwpc */, Mips::LWPC_MMR6, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6530 { 5638 /* lwr */, Mips::LWR, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 6531 { 5638 /* lwr */, Mips::LWR_MM, Convert__GPR32AsmReg1_0__Mem2_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 6532 { 5642 /* lwre */, Mips::LWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6533 { 5642 /* lwre */, Mips::LWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 6534 { 5647 /* lwu */, Mips::LWU_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm122_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, }, 6535 { 5647 /* lwu */, Mips::LWu, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Mem }, }, 6536 { 5651 /* lwupc */, Mips::LWUPC, Convert__GPR32AsmReg1_0__Simm19_Lsl21_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Simm19_Lsl2 }, }, 6537 { 5657 /* lwx */, Mips::LWX_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6538 { 5657 /* lwx */, Mips::LWX, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6539 { 5661 /* lwxc1 */, Mips::LWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6540 { 5661 /* lwxc1 */, Mips::LWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6541 { 5667 /* lwxs */, Mips::LWXS_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 6542 { 5672 /* madd */, Mips::MADD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6543 { 5672 /* madd */, Mips::MADD_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6544 { 5672 /* madd */, Mips::MADD_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6545 { 5672 /* madd */, Mips::MADD_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6546 { 5677 /* madd.d */, Mips::MADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6547 { 5677 /* madd.d */, Mips::MADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6548 { 5677 /* madd.d */, Mips::MADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6549 { 5684 /* madd.s */, Mips::MADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6550 { 5684 /* madd.s */, Mips::MADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6551 { 5691 /* madd_q.h */, Mips::MADD_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6552 { 5700 /* madd_q.w */, Mips::MADD_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6553 { 5709 /* maddf.d */, Mips::MADDF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6554 { 5709 /* maddf.d */, Mips::MADDF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6555 { 5717 /* maddf.s */, Mips::MADDF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6556 { 5717 /* maddf.s */, Mips::MADDF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6557 { 5725 /* maddr_q.h */, Mips::MADDR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6558 { 5735 /* maddr_q.w */, Mips::MADDR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6559 { 5745 /* maddu */, Mips::MADDU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6560 { 5745 /* maddu */, Mips::MADDU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6561 { 5745 /* maddu */, Mips::MADDU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6562 { 5745 /* maddu */, Mips::MADDU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6563 { 5751 /* maddv.b */, Mips::MADDV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6564 { 5759 /* maddv.d */, Mips::MADDV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6565 { 5767 /* maddv.h */, Mips::MADDV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6566 { 5775 /* maddv.w */, Mips::MADDV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6567 { 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6568 { 5783 /* maq_s.w.phl */, Mips::MAQ_S_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6569 { 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6570 { 5795 /* maq_s.w.phr */, Mips::MAQ_S_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6571 { 5807 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6572 { 5807 /* maq_sa.w.phl */, Mips::MAQ_SA_W_PHL, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6573 { 5820 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6574 { 5820 /* maq_sa.w.phr */, Mips::MAQ_SA_W_PHR, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6575 { 5833 /* max.d */, Mips::MAX_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6576 { 5833 /* max.d */, Mips::MAX_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6577 { 5839 /* max.s */, Mips::MAX_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6578 { 5839 /* max.s */, Mips::MAX_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6579 { 5845 /* max_a.b */, Mips::MAX_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6580 { 5853 /* max_a.d */, Mips::MAX_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6581 { 5861 /* max_a.h */, Mips::MAX_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6582 { 5869 /* max_a.w */, Mips::MAX_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6583 { 5877 /* max_s.b */, Mips::MAX_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6584 { 5885 /* max_s.d */, Mips::MAX_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6585 { 5893 /* max_s.h */, Mips::MAX_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6586 { 5901 /* max_s.w */, Mips::MAX_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6587 { 5909 /* max_u.b */, Mips::MAX_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6588 { 5917 /* max_u.d */, Mips::MAX_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6589 { 5925 /* max_u.h */, Mips::MAX_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6590 { 5933 /* max_u.w */, Mips::MAX_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6591 { 5941 /* maxa.d */, Mips::MAXA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6592 { 5941 /* maxa.d */, Mips::MAXA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6593 { 5948 /* maxa.s */, Mips::MAXA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6594 { 5948 /* maxa.s */, Mips::MAXA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6595 { 5955 /* maxi_s.b */, Mips::MAXI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6596 { 5964 /* maxi_s.d */, Mips::MAXI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6597 { 5973 /* maxi_s.h */, Mips::MAXI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6598 { 5982 /* maxi_s.w */, Mips::MAXI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6599 { 5991 /* maxi_u.b */, Mips::MAXI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6600 { 6000 /* maxi_u.d */, Mips::MAXI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6601 { 6009 /* maxi_u.h */, Mips::MAXI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6602 { 6018 /* maxi_u.w */, Mips::MAXI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6603 { 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6604 { 6027 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6605 { 6027 /* mfc0 */, Mips::MFC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6606 { 6027 /* mfc0 */, Mips::MFC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6607 { 6032 /* mfc1 */, Mips::MFC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6608 { 6032 /* mfc1 */, Mips::MFC1_MMR6, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6609 { 6032 /* mfc1 */, Mips::MFC1_MM, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6610 { 6032 /* mfc1 */, Mips::MFC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6611 { 6037 /* mfc2 */, Mips::MFC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6612 { 6037 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6613 { 6037 /* mfc2 */, Mips::MFC2, Convert__GPR32AsmReg1_0__COP2AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 6614 { 6042 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6615 { 6042 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6616 { 6042 /* mfgc0 */, Mips::MFGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6617 { 6042 /* mfgc0 */, Mips::MFGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6618 { 6048 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6619 { 6048 /* mfhc0 */, Mips::MFHC0_MMR6, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6620 { 6054 /* mfhc1 */, Mips::MFHC1_D32, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 6621 { 6054 /* mfhc1 */, Mips::MFHC1_D32_MM, Convert__GPR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 6622 { 6054 /* mfhc1 */, Mips::MFHC1_D64, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6623 { 6054 /* mfhc1 */, Mips::MFHC1_D64_MM, Convert__GPR32AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6624 { 6060 /* mfhc2 */, Mips::MFHC2_MMR6, Convert__GPR32AsmReg1_0__COP2AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6625 { 6066 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6626 { 6066 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6627 { 6066 /* mfhgc0 */, Mips::MFHGC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6628 { 6066 /* mfhgc0 */, Mips::MFHGC0_MM, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6629 { 6073 /* mfhi */, Mips::Mfhi16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, }, 6630 { 6073 /* mfhi */, Mips::MFHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6631 { 6073 /* mfhi */, Mips::MFHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6632 { 6073 /* mfhi */, Mips::MFHI_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6633 { 6073 /* mfhi */, Mips::MFHI_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6634 { 6078 /* mfhi16 */, Mips::MFHI16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6635 { 6085 /* mflo */, Mips::Mflo16, Convert__Reg1_0, Feature_InMips16Mode, { MCK_CPU16Regs }, }, 6636 { 6085 /* mflo */, Mips::MFLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6637 { 6085 /* mflo */, Mips::MFLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6638 { 6085 /* mflo */, Mips::MFLO_DSP_MM, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6639 { 6085 /* mflo */, Mips::MFLO_DSP, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6640 { 6090 /* mflo16 */, Mips::MFLO16_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6641 { 6097 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6642 { 6097 /* mftacx */, Mips::MFTACX, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6643 { 6104 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6644 { 6104 /* mftc0 */, Mips::MFTC0, Convert__GPR32AsmReg1_0__COP0AsmReg1_1__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6645 { 6110 /* mftc1 */, Mips::MFTC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6646 { 6116 /* mftdsp */, Mips::MFTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, }, 6647 { 6123 /* mftgpr */, Mips::MFTGPR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6648 { 6130 /* mfthc1 */, Mips::MFTHC1, Convert__GPR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6649 { 6137 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6650 { 6137 /* mfthi */, Mips::MFTHI, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6651 { 6143 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__regAC0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6652 { 6143 /* mftlo */, Mips::MFTLO, Convert__GPR32AsmReg1_0__ACC64DSPAsmReg1_1, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6653 { 6149 /* mftr */, Mips::MFTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, 6654 { 6154 /* min.d */, Mips::MIN_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6655 { 6154 /* min.d */, Mips::MIN_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6656 { 6160 /* min.s */, Mips::MIN_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6657 { 6160 /* min.s */, Mips::MIN_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6658 { 6166 /* min_a.b */, Mips::MIN_A_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6659 { 6174 /* min_a.d */, Mips::MIN_A_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6660 { 6182 /* min_a.h */, Mips::MIN_A_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6661 { 6190 /* min_a.w */, Mips::MIN_A_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6662 { 6198 /* min_s.b */, Mips::MIN_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6663 { 6206 /* min_s.d */, Mips::MIN_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6664 { 6214 /* min_s.h */, Mips::MIN_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6665 { 6222 /* min_s.w */, Mips::MIN_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6666 { 6230 /* min_u.b */, Mips::MIN_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6667 { 6238 /* min_u.d */, Mips::MIN_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6668 { 6246 /* min_u.h */, Mips::MIN_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6669 { 6254 /* min_u.w */, Mips::MIN_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6670 { 6262 /* mina.d */, Mips::MINA_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6671 { 6262 /* mina.d */, Mips::MINA_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6672 { 6269 /* mina.s */, Mips::MINA_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6673 { 6269 /* mina.s */, Mips::MINA_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6674 { 6276 /* mini_s.b */, Mips::MINI_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6675 { 6285 /* mini_s.d */, Mips::MINI_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6676 { 6294 /* mini_s.h */, Mips::MINI_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6677 { 6303 /* mini_s.w */, Mips::MINI_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantSImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantSImm5_0 }, }, 6678 { 6312 /* mini_u.b */, Mips::MINI_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6679 { 6321 /* mini_u.d */, Mips::MINI_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6680 { 6330 /* mini_u.h */, Mips::MINI_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6681 { 6339 /* mini_u.w */, Mips::MINI_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 6682 { 6348 /* mod */, Mips::MOD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6683 { 6348 /* mod */, Mips::MOD_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6684 { 6352 /* mod_s.b */, Mips::MOD_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6685 { 6360 /* mod_s.d */, Mips::MOD_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6686 { 6368 /* mod_s.h */, Mips::MOD_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6687 { 6376 /* mod_s.w */, Mips::MOD_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6688 { 6384 /* mod_u.b */, Mips::MOD_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6689 { 6392 /* mod_u.d */, Mips::MOD_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6690 { 6400 /* mod_u.h */, Mips::MOD_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6691 { 6408 /* mod_u.w */, Mips::MOD_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6692 { 6416 /* modsub */, Mips::MODSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6693 { 6416 /* modsub */, Mips::MODSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6694 { 6423 /* modu */, Mips::MODU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6695 { 6423 /* modu */, Mips::MODU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6696 { 6428 /* mov.d */, Mips::FMOV_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6697 { 6428 /* mov.d */, Mips::FMOV_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6698 { 6428 /* mov.d */, Mips::FMOV_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6699 { 6428 /* mov.d */, Mips::FMOV_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6700 { 6434 /* mov.s */, Mips::FMOV_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6701 { 6434 /* mov.s */, Mips::FMOV_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6702 { 6434 /* mov.s */, Mips::FMOV_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6703 { 6440 /* move */, Mips::MoveR3216, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_DSPR }, }, 6704 { 6440 /* move */, Mips::Move32R16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_DSPR, MCK_CPU16Regs }, }, 6705 { 6440 /* move */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6706 { 6440 /* move */, Mips::ADDu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6707 { 6440 /* move */, Mips::MOVE16_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6708 { 6440 /* move */, Mips::OR64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6709 { 6440 /* move */, Mips::DADDu, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__regZERO_64, Feature_IsGP64bit|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 6710 { 6445 /* move.v */, Mips::MOVE_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6711 { 6452 /* move16 */, Mips::MOVE16_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6712 { 6459 /* movep */, Mips::MOVEP_MM, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, 6713 { 6459 /* movep */, Mips::MOVEP_MMR6, Convert__MovePRegPair2_0__GPRMM16AsmRegMoveP1_1__GPRMM16AsmRegMoveP1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MovePRegPair, MCK_GPRMM16AsmRegMoveP, MCK_GPRMM16AsmRegMoveP }, }, 6714 { 6465 /* movf */, Mips::MOVF_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 6715 { 6465 /* movf */, Mips::MOVF_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 6716 { 6470 /* movf.d */, Mips::MOVF_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 6717 { 6470 /* movf.d */, Mips::MOVF_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 6718 { 6470 /* movf.d */, Mips::MOVF_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, 6719 { 6477 /* movf.s */, Mips::MOVF_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 6720 { 6477 /* movf.s */, Mips::MOVF_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 6721 { 6484 /* movn */, Mips::MOVN_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6722 { 6484 /* movn */, Mips::MOVN_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6723 { 6489 /* movn.d */, Mips::MOVN_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 6724 { 6489 /* movn.d */, Mips::MOVN_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 6725 { 6489 /* movn.d */, Mips::MOVN_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, 6726 { 6496 /* movn.s */, Mips::MOVN_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 6727 { 6496 /* movn.s */, Mips::MOVN_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 6728 { 6503 /* movt */, Mips::MOVT_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 6729 { 6503 /* movt */, Mips::MOVT_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_FCCAsmReg }, }, 6730 { 6508 /* movt.d */, Mips::MOVT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 6731 { 6508 /* movt.d */, Mips::MOVT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_FCCAsmReg }, }, 6732 { 6508 /* movt.d */, Mips::MOVT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FCCAsmReg }, }, 6733 { 6515 /* movt.s */, Mips::MOVT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 6734 { 6515 /* movt.s */, Mips::MOVT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FCCAsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FCCAsmReg }, }, 6735 { 6522 /* movz */, Mips::MOVZ_I_I, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6736 { 6522 /* movz */, Mips::MOVZ_I_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6737 { 6527 /* movz.d */, Mips::MOVZ_I_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 6738 { 6527 /* movz.d */, Mips::MOVZ_I_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 6739 { 6527 /* movz.d */, Mips::MOVZ_I_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, 6740 { 6534 /* movz.s */, Mips::MOVZ_I_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 6741 { 6534 /* movz.s */, Mips::MOVZ_I_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 6742 { 6541 /* msub */, Mips::MSUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6743 { 6541 /* msub */, Mips::MSUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6744 { 6541 /* msub */, Mips::MSUB_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6745 { 6541 /* msub */, Mips::MSUB_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6746 { 6546 /* msub.d */, Mips::MSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6747 { 6546 /* msub.d */, Mips::MSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6748 { 6546 /* msub.d */, Mips::MSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6749 { 6553 /* msub.s */, Mips::MSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6750 { 6553 /* msub.s */, Mips::MSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6751 { 6560 /* msub_q.h */, Mips::MSUB_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6752 { 6569 /* msub_q.w */, Mips::MSUB_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6753 { 6578 /* msubf.d */, Mips::MSUBF_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6754 { 6578 /* msubf.d */, Mips::MSUBF_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6755 { 6586 /* msubf.s */, Mips::MSUBF_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6756 { 6586 /* msubf.s */, Mips::MSUBF_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6757 { 6594 /* msubr_q.h */, Mips::MSUBR_Q_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6758 { 6604 /* msubr_q.w */, Mips::MSUBR_Q_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6759 { 6614 /* msubu */, Mips::MSUBU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6760 { 6614 /* msubu */, Mips::MSUBU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6761 { 6614 /* msubu */, Mips::MSUBU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6762 { 6614 /* msubu */, Mips::MSUBU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6763 { 6620 /* msubv.b */, Mips::MSUBV_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6764 { 6628 /* msubv.d */, Mips::MSUBV_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6765 { 6636 /* msubv.h */, Mips::MSUBV_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6766 { 6644 /* msubv.w */, Mips::MSUBV_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6767 { 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6768 { 6652 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6769 { 6652 /* mtc0 */, Mips::MTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6770 { 6652 /* mtc0 */, Mips::MTC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6771 { 6657 /* mtc1 */, Mips::MTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6772 { 6657 /* mtc1 */, Mips::MTC1_MMR6, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6773 { 6657 /* mtc1 */, Mips::MTC1_MM, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6774 { 6657 /* mtc1 */, Mips::MTC1_D64, Convert__FGR64AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6775 { 6662 /* mtc2 */, Mips::MTC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6776 { 6662 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6777 { 6662 /* mtc2 */, Mips::MTC2, Convert__COP2AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP2AsmReg, MCK_ConstantUImm3_0 }, }, 6778 { 6667 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6779 { 6667 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6780 { 6667 /* mtgc0 */, Mips::MTGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6781 { 6667 /* mtgc0 */, Mips::MTGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6782 { 6673 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6783 { 6673 /* mthc0 */, Mips::MTHC0_MMR6, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6784 { 6679 /* mthc1 */, Mips::MTHC1_D32, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 6785 { 6679 /* mthc1 */, Mips::MTHC1_D32_MM, Convert__AFGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_AFGR64AsmReg }, }, 6786 { 6679 /* mthc1 */, Mips::MTHC1_D64, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6787 { 6679 /* mthc1 */, Mips::MTHC1_D64_MM, Convert__FGR64AsmReg1_1__Tie0_1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_GPR32AsmReg, MCK_FGR64AsmReg }, }, 6788 { 6685 /* mthc2 */, Mips::MTHC2_MMR6, Convert__COP2AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_COP2AsmReg }, }, 6789 { 6691 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6790 { 6691 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6791 { 6691 /* mthgc0 */, Mips::MTHGC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6792 { 6691 /* mthgc0 */, Mips::MTHGC0_MM, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6793 { 6698 /* mthi */, Mips::MTHI, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6794 { 6698 /* mthi */, Mips::MTHI_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6795 { 6698 /* mthi */, Mips::MTHI_DSP_MM, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, 6796 { 6698 /* mthi */, Mips::MTHI_DSP, Convert__HI32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_HI32DSPAsmReg }, }, 6797 { 6703 /* mthlip */, Mips::MTHLIP_MM, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6798 { 6703 /* mthlip */, Mips::MTHLIP, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0__Tie0_1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6799 { 6710 /* mtlo */, Mips::MTLO, Convert__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6800 { 6710 /* mtlo */, Mips::MTLO_MM, Convert__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6801 { 6710 /* mtlo */, Mips::MTLO_DSP_MM, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, 6802 { 6710 /* mtlo */, Mips::MTLO_DSP, Convert__LO32DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_LO32DSPAsmReg }, }, 6803 { 6715 /* mtm0 */, Mips::MTM0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6804 { 6720 /* mtm1 */, Mips::MTM1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6805 { 6725 /* mtm2 */, Mips::MTM2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6806 { 6730 /* mtp0 */, Mips::MTP0, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6807 { 6735 /* mtp1 */, Mips::MTP1, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6808 { 6740 /* mtp2 */, Mips::MTP2, Convert__GPR64AsmReg1_0, Feature_HasCnMips, { MCK_GPR64AsmReg }, }, 6809 { 6745 /* mttacx */, Mips::MTTACX, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6810 { 6745 /* mttacx */, Mips::MTTACX, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6811 { 6752 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__imm_95_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_COP0AsmReg }, }, 6812 { 6752 /* mttc0 */, Mips::MTTC0, Convert__COP0AsmReg1_1__GPR32AsmReg1_0__ConstantUImm3_01_2, Feature_HasMT, { MCK_GPR32AsmReg, MCK_COP0AsmReg, MCK_ConstantUImm3_0 }, }, 6813 { 6758 /* mttc1 */, Mips::MTTC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6814 { 6764 /* mttdsp */, Mips::MTTDSP, Convert__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg }, }, 6815 { 6771 /* mttgpr */, Mips::MTTGPR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6816 { 6778 /* mtthc1 */, Mips::MTTHC1, Convert__FGR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_FGR32AsmReg }, }, 6817 { 6785 /* mtthi */, Mips::MTTHI, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6818 { 6785 /* mtthi */, Mips::MTTHI, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6819 { 6791 /* mttlo */, Mips::MTTLO, Convert__regAC0__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6820 { 6791 /* mttlo */, Mips::MTTLO, Convert__ACC64DSPAsmReg1_1__GPR32AsmReg1_0, Feature_HasMT, { MCK_GPR32AsmReg, MCK_ACC64DSPAsmReg }, }, 6821 { 6797 /* mttr */, Mips::MTTR, Convert__GPR32AsmReg1_1__GPR32AsmReg1_0__ConstantUImm1_01_2__ConstantUImm3_01_3__ConstantUImm1_01_4, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm1_0, MCK_ConstantUImm3_0, MCK_ConstantUImm1_0 }, }, 6822 { 6802 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6823 { 6802 /* muh */, Mips::MUH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6824 { 6802 /* muh */, Mips::MUH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6825 { 6806 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6826 { 6806 /* muhu */, Mips::MUHU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6827 { 6806 /* muhu */, Mips::MUHU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6828 { 6811 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6829 { 6811 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6830 { 6811 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6831 { 6811 /* mul */, Mips::MUL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6832 { 6811 /* mul */, Mips::MUL_R6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6833 { 6811 /* mul */, Mips::MUL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6834 { 6811 /* mul */, Mips::MUL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6835 { 6811 /* mul */, Mips::MULImmMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6836 { 6815 /* mul.d */, Mips::FMUL_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6837 { 6815 /* mul.d */, Mips::FMUL_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6838 { 6815 /* mul.d */, Mips::FMUL_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6839 { 6815 /* mul.d */, Mips::FMUL_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6840 { 6821 /* mul.ph */, Mips::MUL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6841 { 6821 /* mul.ph */, Mips::MUL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6842 { 6828 /* mul.s */, Mips::FMUL_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6843 { 6828 /* mul.s */, Mips::FMUL_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6844 { 6828 /* mul.s */, Mips::FMUL_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6845 { 6834 /* mul_q.h */, Mips::MUL_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6846 { 6842 /* mul_q.w */, Mips::MUL_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6847 { 6850 /* mul_s.ph */, Mips::MUL_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6848 { 6850 /* mul_s.ph */, Mips::MUL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6849 { 6859 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6850 { 6859 /* muleq_s.w.phl */, Mips::MULEQ_S_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6851 { 6873 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6852 { 6873 /* muleq_s.w.phr */, Mips::MULEQ_S_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6853 { 6887 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6854 { 6887 /* muleu_s.ph.qbl */, Mips::MULEU_S_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6855 { 6902 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6856 { 6902 /* muleu_s.ph.qbr */, Mips::MULEU_S_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6857 { 6917 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6858 { 6917 /* mulo */, Mips::MULOMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6859 { 6922 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6860 { 6922 /* mulou */, Mips::MULOUMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6861 { 6928 /* mulq_rs.ph */, Mips::MULQ_RS_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6862 { 6928 /* mulq_rs.ph */, Mips::MULQ_RS_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6863 { 6939 /* mulq_rs.w */, Mips::MULQ_RS_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6864 { 6939 /* mulq_rs.w */, Mips::MULQ_RS_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6865 { 6949 /* mulq_s.ph */, Mips::MULQ_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6866 { 6949 /* mulq_s.ph */, Mips::MULQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6867 { 6959 /* mulq_s.w */, Mips::MULQ_S_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6868 { 6959 /* mulq_s.w */, Mips::MULQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6869 { 6968 /* mulr_q.h */, Mips::MULR_Q_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6870 { 6977 /* mulr_q.w */, Mips::MULR_Q_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6871 { 6986 /* mulsa.w.ph */, Mips::MULSA_W_PH_MMR2, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6872 { 6986 /* mulsa.w.ph */, Mips::MULSA_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSPR2, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6873 { 6997 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6874 { 6997 /* mulsaq_s.w.ph */, Mips::MULSAQ_S_W_PH, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6875 { 7011 /* mult */, Mips::MULT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6876 { 7011 /* mult */, Mips::MULT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6877 { 7011 /* mult */, Mips::MULT_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6878 { 7011 /* mult */, Mips::MULT_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6879 { 7016 /* multu */, Mips::MULTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6880 { 7016 /* multu */, Mips::MULTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6881 { 7016 /* multu */, Mips::MULTU_DSP_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6882 { 7016 /* multu */, Mips::MULTU_DSP, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6883 { 7022 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6884 { 7022 /* mulu */, Mips::MULU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6885 { 7022 /* mulu */, Mips::MULU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6886 { 7027 /* mulv.b */, Mips::MULV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6887 { 7034 /* mulv.d */, Mips::MULV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6888 { 7041 /* mulv.h */, Mips::MULV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6889 { 7048 /* mulv.w */, Mips::MULV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6890 { 7055 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6891 { 7055 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6892 { 7055 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6893 { 7055 /* neg */, Mips::NegRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 6894 { 7055 /* neg */, Mips::SUB, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6895 { 7055 /* neg */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6896 { 7055 /* neg */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6897 { 7059 /* neg.d */, Mips::FNEG_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6898 { 7059 /* neg.d */, Mips::FNEG_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6899 { 7059 /* neg.d */, Mips::FNEG_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6900 { 7059 /* neg.d */, Mips::FNEG_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6901 { 7065 /* neg.s */, Mips::FNEG_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6902 { 7065 /* neg.s */, Mips::FNEG_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6903 { 7065 /* neg.s */, Mips::FNEG_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6904 { 7071 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6905 { 7071 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6906 { 7071 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6907 { 7071 /* negu */, Mips::SUBu, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6908 { 7071 /* negu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6909 { 7071 /* negu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__regZERO__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6910 { 7076 /* nloc.b */, Mips::NLOC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6911 { 7083 /* nloc.d */, Mips::NLOC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6912 { 7090 /* nloc.h */, Mips::NLOC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6913 { 7097 /* nloc.w */, Mips::NLOC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6914 { 7104 /* nlzc.b */, Mips::NLZC_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6915 { 7111 /* nlzc.d */, Mips::NLZC_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6916 { 7118 /* nlzc.h */, Mips::NLZC_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6917 { 7125 /* nlzc.w */, Mips::NLZC_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6918 { 7132 /* nmadd.d */, Mips::NMADD_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6919 { 7132 /* nmadd.d */, Mips::NMADD_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6920 { 7132 /* nmadd.d */, Mips::NMADD_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6921 { 7140 /* nmadd.s */, Mips::NMADD_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6922 { 7140 /* nmadd.s */, Mips::NMADD_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6923 { 7148 /* nmsub.d */, Mips::NMSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6924 { 7148 /* nmsub.d */, Mips::NMSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2__AFGR64AsmReg1_3, Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 6925 { 7148 /* nmsub.d */, Mips::NMSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2__FGR64AsmReg1_3, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 6926 { 7156 /* nmsub.s */, Mips::NMSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6927 { 7156 /* nmsub.s */, Mips::NMSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2__FGR32AsmReg1_3, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 6928 { 7164 /* nop */, Mips::SLL, Convert__regZERO__regZERO__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 6929 { 7164 /* nop */, Mips::SLL_MMR6, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6930 { 7164 /* nop */, Mips::Move32R16, Convert__regZERO__regS0, Feature_InMips16Mode, { }, }, 6931 { 7164 /* nop */, Mips::SLL_MM, Convert__regZERO__regZERO__imm_95_0, Feature_InMicroMips, { }, }, 6932 { 7164 /* nop */, Mips::MOVE16_MM, Convert__regZERO__regZERO, Feature_InMicroMips, { }, }, 6933 { 7168 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6934 { 7168 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 6935 { 7168 /* nor */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6936 { 7168 /* nor */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6937 { 7168 /* nor */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6938 { 7168 /* nor */, Mips::NORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_IsGP32bit, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6939 { 7168 /* nor */, Mips::NORImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 6940 { 7172 /* nor.v */, Mips::NOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6941 { 7178 /* nori.b */, Mips::NORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 6942 { 7185 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 6943 { 7185 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg }, }, 6944 { 7185 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg }, }, 6945 { 7185 /* not */, Mips::NotRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 6946 { 7185 /* not */, Mips::NOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6947 { 7185 /* not */, Mips::NOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6948 { 7185 /* not */, Mips::NOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__regZERO, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6949 { 7189 /* not16 */, Mips::NOT16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 6950 { 7189 /* not16 */, Mips::NOT16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 6951 { 7195 /* or */, Mips::OrRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 6952 { 7195 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6953 { 7195 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6954 { 7195 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6955 { 7195 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 6956 { 7195 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6957 { 7195 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6958 { 7195 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 6959 { 7195 /* or */, Mips::OR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6960 { 7195 /* or */, Mips::OR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6961 { 7195 /* or */, Mips::OR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6962 { 7195 /* or */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 6963 { 7195 /* or */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6964 { 7195 /* or */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 6965 { 7195 /* or */, Mips::ORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 6966 { 7198 /* or.v */, Mips::OR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6967 { 7203 /* or16 */, Mips::OR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 6968 { 7203 /* or16 */, Mips::OR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 6969 { 7208 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 6970 { 7208 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 6971 { 7208 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 6972 { 7208 /* ori */, Mips::ORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 6973 { 7208 /* ori */, Mips::ORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 6974 { 7208 /* ori */, Mips::ORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 6975 { 7212 /* ori.b */, Mips::ORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 6976 { 7218 /* packrl.ph */, Mips::PACKRL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6977 { 7218 /* packrl.ph */, Mips::PACKRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6978 { 7228 /* pause */, Mips::PAUSE, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { }, }, 6979 { 7228 /* pause */, Mips::PAUSE_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 6980 { 7228 /* pause */, Mips::PAUSE_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 6981 { 7234 /* pckev.b */, Mips::PCKEV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6982 { 7242 /* pckev.d */, Mips::PCKEV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6983 { 7250 /* pckev.h */, Mips::PCKEV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6984 { 7258 /* pckev.w */, Mips::PCKEV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6985 { 7266 /* pckod.b */, Mips::PCKOD_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6986 { 7274 /* pckod.d */, Mips::PCKOD_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6987 { 7282 /* pckod.h */, Mips::PCKOD_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6988 { 7290 /* pckod.w */, Mips::PCKOD_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6989 { 7298 /* pcnt.b */, Mips::PCNT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6990 { 7305 /* pcnt.d */, Mips::PCNT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6991 { 7312 /* pcnt.h */, Mips::PCNT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6992 { 7319 /* pcnt.w */, Mips::PCNT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 6993 { 7326 /* pick.ph */, Mips::PICK_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6994 { 7326 /* pick.ph */, Mips::PICK_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6995 { 7334 /* pick.qb */, Mips::PICK_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6996 { 7334 /* pick.qb */, Mips::PICK_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6997 { 7342 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasCnMips, { MCK_GPR32AsmReg }, }, 6998 { 7342 /* pop */, Mips::POP, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 6999 { 7346 /* preceq.w.phl */, Mips::PRECEQ_W_PHL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7000 { 7346 /* preceq.w.phl */, Mips::PRECEQ_W_PHL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7001 { 7359 /* preceq.w.phr */, Mips::PRECEQ_W_PHR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7002 { 7359 /* preceq.w.phr */, Mips::PRECEQ_W_PHR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7003 { 7372 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7004 { 7372 /* precequ.ph.qbl */, Mips::PRECEQU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7005 { 7387 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7006 { 7387 /* precequ.ph.qbla */, Mips::PRECEQU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7007 { 7403 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7008 { 7403 /* precequ.ph.qbr */, Mips::PRECEQU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7009 { 7418 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7010 { 7418 /* precequ.ph.qbra */, Mips::PRECEQU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7011 { 7434 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7012 { 7434 /* preceu.ph.qbl */, Mips::PRECEU_PH_QBL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7013 { 7448 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7014 { 7448 /* preceu.ph.qbla */, Mips::PRECEU_PH_QBLA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7015 { 7463 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7016 { 7463 /* preceu.ph.qbr */, Mips::PRECEU_PH_QBR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7017 { 7477 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7018 { 7477 /* preceu.ph.qbra */, Mips::PRECEU_PH_QBRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7019 { 7492 /* precr.qb.ph */, Mips::PRECR_QB_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7020 { 7492 /* precr.qb.ph */, Mips::PRECR_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7021 { 7504 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7022 { 7504 /* precr_sra.ph.w */, Mips::PRECR_SRA_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7023 { 7519 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7024 { 7519 /* precr_sra_r.ph.w */, Mips::PRECR_SRA_R_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7025 { 7536 /* precrq.ph.w */, Mips::PRECRQ_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7026 { 7536 /* precrq.ph.w */, Mips::PRECRQ_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7027 { 7548 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7028 { 7548 /* precrq.qb.ph */, Mips::PRECRQ_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7029 { 7561 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7030 { 7561 /* precrq_rs.ph.w */, Mips::PRECRQ_RS_PH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7031 { 7576 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7032 { 7576 /* precrqu_s.qb.ph */, Mips::PRECRQU_S_QB_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7033 { 7592 /* pref */, Mips::PREF_R6, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 7034 { 7592 /* pref */, Mips::PREF, Convert__Mem2_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_Mem }, }, 7035 { 7592 /* pref */, Mips::PREF_MM, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 7036 { 7592 /* pref */, Mips::PREF_MMR6, Convert__Mem2_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0, MCK_Mem }, }, 7037 { 7597 /* prefe */, Mips::PREFE, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 7038 { 7597 /* prefe */, Mips::PREFE_MM, Convert__MemOffsetSimm92_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasEVA, { MCK_ConstantUImm5_0, MCK_MemOffsetSimm9 }, }, 7039 { 7603 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm5_0, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7040 { 7609 /* prepend */, Mips::PREPEND_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7041 { 7609 /* prepend */, Mips::PREPEND, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2__Tie0_1_1, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7042 { 7617 /* raddu.w.qb */, Mips::RADDU_W_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7043 { 7617 /* raddu.w.qb */, Mips::RADDU_W_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7044 { 7628 /* rddsp */, Mips::RDDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, 7045 { 7628 /* rddsp */, Mips::RDDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7046 { 7634 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, 7047 { 7634 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, 7048 { 7634 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg }, }, 7049 { 7634 /* rdhwr */, Mips::RDHWR_MMR6, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm3_0 }, }, 7050 { 7634 /* rdhwr */, Mips::RDHWR, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, 7051 { 7634 /* rdhwr */, Mips::RDHWR_MM, Convert__GPR32AsmReg1_0__HWRegsAsmReg1_1__ConstantUImm8_01_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_HWRegsAsmReg, MCK_ConstantUImm8_0 }, }, 7052 { 7640 /* rdpgpr */, Mips::RDPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7053 { 7647 /* recip.d */, Mips::RECIP_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7054 { 7647 /* recip.d */, Mips::RECIP_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7055 { 7647 /* recip.d */, Mips::RECIP_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7056 { 7647 /* recip.d */, Mips::RECIP_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7057 { 7655 /* recip.s */, Mips::RECIP_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7058 { 7655 /* recip.s */, Mips::RECIP_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7059 { 7663 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7060 { 7663 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7061 { 7663 /* rem */, Mips::SRemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7062 { 7663 /* rem */, Mips::SRemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7063 { 7667 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7064 { 7667 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7065 { 7667 /* remu */, Mips::URemMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7066 { 7667 /* remu */, Mips::URemIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7067 { 7672 /* repl.ph */, Mips::REPL_PH_MM, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, 7068 { 7672 /* repl.ph */, Mips::REPL_PH, Convert__GPR32AsmReg1_0__ConstantSImm10_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantSImm10_0 }, }, 7069 { 7680 /* repl.qb */, Mips::REPL_QB_MM, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, 7070 { 7680 /* repl.qb */, Mips::REPL_QB, Convert__GPR32AsmReg1_0__ConstantUImm8_01_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm8_0 }, }, 7071 { 7688 /* replv.ph */, Mips::REPLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7072 { 7688 /* replv.ph */, Mips::REPLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7073 { 7697 /* replv.qb */, Mips::REPLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7074 { 7697 /* replv.qb */, Mips::REPLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7075 { 7706 /* rint.d */, Mips::RINT_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7076 { 7706 /* rint.d */, Mips::RINT_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7077 { 7713 /* rint.s */, Mips::RINT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7078 { 7713 /* rint.s */, Mips::RINT_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7079 { 7720 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7080 { 7720 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7081 { 7720 /* rol */, Mips::ROL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7082 { 7720 /* rol */, Mips::ROLImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7083 { 7724 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7084 { 7724 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm161_1, 0, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7085 { 7724 /* ror */, Mips::ROR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7086 { 7724 /* ror */, Mips::RORImm, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7087 { 7728 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7088 { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7089 { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7090 { 7728 /* rotr */, Mips::ROTR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7091 { 7728 /* rotr */, Mips::ROTR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7092 { 7733 /* rotrv */, Mips::ROTRV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7093 { 7733 /* rotrv */, Mips::ROTRV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7094 { 7739 /* round.l.d */, Mips::ROUND_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7095 { 7739 /* round.l.d */, Mips::ROUND_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7096 { 7749 /* round.l.s */, Mips::ROUND_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 7097 { 7749 /* round.l.s */, Mips::ROUND_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 7098 { 7759 /* round.w.d */, Mips::ROUND_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7099 { 7759 /* round.w.d */, Mips::ROUND_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7100 { 7759 /* round.w.d */, Mips::ROUND_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 7101 { 7759 /* round.w.d */, Mips::ROUND_W_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7102 { 7769 /* round.w.s */, Mips::ROUND_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7103 { 7769 /* round.w.s */, Mips::ROUND_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7104 { 7769 /* round.w.s */, Mips::ROUND_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7105 { 7779 /* rsqrt.d */, Mips::RSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7106 { 7779 /* rsqrt.d */, Mips::RSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7107 { 7779 /* rsqrt.d */, Mips::RSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7108 { 7779 /* rsqrt.d */, Mips::RSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7109 { 7787 /* rsqrt.s */, Mips::RSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7110 { 7787 /* rsqrt.s */, Mips::RSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_NotInMips16Mode|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7111 { 7795 /* s.d */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7112 { 7795 /* s.d */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7113 { 7799 /* s.s */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 7114 { 7803 /* sat_s.b */, Mips::SAT_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7115 { 7811 /* sat_s.d */, Mips::SAT_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7116 { 7819 /* sat_s.h */, Mips::SAT_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7117 { 7827 /* sat_s.w */, Mips::SAT_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7118 { 7835 /* sat_u.b */, Mips::SAT_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7119 { 7843 /* sat_u.d */, Mips::SAT_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7120 { 7851 /* sat_u.h */, Mips::SAT_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7121 { 7859 /* sat_u.w */, Mips::SAT_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7122 { 7867 /* sb */, Mips::SB, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7123 { 7867 /* sb */, Mips::SB_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7124 { 7867 /* sb */, Mips::SB_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7125 { 7867 /* sb */, Mips::SbRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, 7126 { 7870 /* sb16 */, Mips::SB16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7127 { 7870 /* sb16 */, Mips::SB16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7128 { 7875 /* sbe */, Mips::SBE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7129 { 7875 /* sbe */, Mips::SBE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7130 { 7879 /* sc */, Mips::SC64_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7131 { 7879 /* sc */, Mips::SC_R6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7132 { 7879 /* sc */, Mips::SC_MMR6, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7133 { 7879 /* sc */, Mips::SC, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7134 { 7879 /* sc */, Mips::SC64, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7135 { 7879 /* sc */, Mips::SC_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7136 { 7882 /* scd */, Mips::SCD_R6, Convert__GPR64AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_MemOffsetSimm9 }, }, 7137 { 7882 /* scd */, Mips::SCD, Convert__GPR64AsmReg1_0__Tie0_1_1__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 7138 { 7886 /* sce */, Mips::SCE, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7139 { 7886 /* sce */, Mips::SCE_MM, Convert__GPR32AsmReg1_0__Tie0_1_1__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7140 { 7890 /* sd */, Mips::SDMacro, Convert__GPR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips3, { MCK_GPR32AsmReg, MCK_MemOffsetSimm16 }, }, 7141 { 7890 /* sd */, Mips::SD, Convert__GPR64AsmReg1_0__MemOffsetSimmPtr2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_MemOffsetSimmPtr }, }, 7142 { 7893 /* sdbbp */, Mips::SDBBP, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6, { }, }, 7143 { 7893 /* sdbbp */, Mips::SDBBP_R6, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { }, }, 7144 { 7893 /* sdbbp */, Mips::SDBBP_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 7145 { 7893 /* sdbbp */, Mips::SDBBP_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, }, 7146 { 7893 /* sdbbp */, Mips::SDBBP, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, 7147 { 7893 /* sdbbp */, Mips::SDBBP_R6, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, 7148 { 7893 /* sdbbp */, Mips::SDBBP_MMR6, Convert__ConstantUImm20_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm20_0 }, }, 7149 { 7899 /* sdbbp16 */, Mips::SDBBP16_MM, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_ConstantUImm4_0 }, }, 7150 { 7899 /* sdbbp16 */, Mips::SDBBP16_MMR6, Convert__ConstantUImm4_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm4_0 }, }, 7151 { 7907 /* sdc1 */, Mips::SDC1, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7152 { 7907 /* sdc1 */, Mips::SDC1_MM, Convert__AFGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7153 { 7907 /* sdc1 */, Mips::SDC164, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7154 { 7907 /* sdc1 */, Mips::SDC1_D64_MMR6, Convert__FGR64AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_MemOffsetSimm16 }, }, 7155 { 7912 /* sdc2 */, Mips::SDC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 7156 { 7912 /* sdc2 */, Mips::SDC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 7157 { 7912 /* sdc2 */, Mips::SDC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 7158 { 7917 /* sdc3 */, Mips::SDC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 7159 { 7922 /* sdl */, Mips::SDL, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 7160 { 7926 /* sdr */, Mips::SDR, Convert__GPR64AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR64AsmReg, MCK_Mem }, }, 7161 { 7930 /* sdxc1 */, Mips::SDXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7162 { 7930 /* sdxc1 */, Mips::SDXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7163 { 7936 /* seb */, Mips::SebRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, }, 7164 { 7936 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7165 { 7936 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, }, 7166 { 7936 /* seb */, Mips::SEB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7167 { 7936 /* seb */, Mips::SEB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7168 { 7940 /* seh */, Mips::SehRx16, Convert__Reg1_0__Tie0_1_1, Feature_InMips16Mode, { MCK_CPU16Regs }, }, 7169 { 7940 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7170 { 7940 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg }, }, 7171 { 7940 /* seh */, Mips::SEH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7172 { 7940 /* seh */, Mips::SEH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7173 { 7944 /* sel.d */, Mips::SEL_D, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7174 { 7944 /* sel.d */, Mips::SEL_D_MMR6, Convert__FGR64AsmReg1_0__Tie0_1_1__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7175 { 7950 /* sel.s */, Mips::SEL_S, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7176 { 7950 /* sel.s */, Mips::SEL_S_MMR6, Convert__FGR32AsmReg1_0__Tie0_1_1__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7177 { 7956 /* seleqz */, Mips::SELEQZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7178 { 7956 /* seleqz */, Mips::SELEQZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7179 { 7956 /* seleqz */, Mips::SELEQZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7180 { 7963 /* seleqz.d */, Mips::SELEQZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7181 { 7963 /* seleqz.d */, Mips::SELEQZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7182 { 7972 /* seleqz.s */, Mips::SELEQZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7183 { 7972 /* seleqz.s */, Mips::SELEQZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7184 { 7981 /* selnez */, Mips::SELNEZ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7185 { 7981 /* selnez */, Mips::SELNEZ_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7186 { 7981 /* selnez */, Mips::SELNEZ64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7187 { 7988 /* selnez.d */, Mips::SELNEZ_D, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7188 { 7988 /* selnez.d */, Mips::SELNEZ_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7189 { 7997 /* selnez.s */, Mips::SELNEZ_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7190 { 7997 /* selnez.s */, Mips::SELNEZ_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7191 { 8006 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7192 { 8006 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm321_1, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_SImm32 }, }, 7193 { 8006 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7194 { 8006 /* seq */, Mips::SEQMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7195 { 8006 /* seq */, Mips::SEQIMacro, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_NotCnMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7196 { 8006 /* seq */, Mips::SEQ, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7197 { 8010 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7198 { 8010 /* seqi */, Mips::SEQi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7199 { 8015 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7200 { 8015 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7201 { 8015 /* sgt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7202 { 8015 /* sgt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7203 { 8019 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7204 { 8019 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7205 { 8019 /* sgtu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7206 { 8019 /* sgtu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_2__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7207 { 8024 /* sh */, Mips::SH, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7208 { 8024 /* sh */, Mips::SH_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7209 { 8024 /* sh */, Mips::SH_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7210 { 8024 /* sh */, Mips::ShRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, 7211 { 8027 /* sh16 */, Mips::SH16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7212 { 8027 /* sh16 */, Mips::SH16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7213 { 8032 /* she */, Mips::SHE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7214 { 8032 /* she */, Mips::SHE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7215 { 8036 /* shf.b */, Mips::SHF_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7216 { 8042 /* shf.h */, Mips::SHF_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7217 { 8048 /* shf.w */, Mips::SHF_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7218 { 8054 /* shilo */, Mips::SHILO_MM, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, 7219 { 8054 /* shilo */, Mips::SHILO, Convert__ACC64DSPAsmReg1_0__ConstantSImm6_01_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_ConstantSImm6_0 }, }, 7220 { 8060 /* shilov */, Mips::SHILOV_MM, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 7221 { 8060 /* shilov */, Mips::SHILOV, Convert__ACC64DSPAsmReg1_0__GPR32AsmReg1_1__Tie0_1_1, Feature_HasDSP, { MCK_ACC64DSPAsmReg, MCK_GPR32AsmReg }, }, 7222 { 8067 /* shll.ph */, Mips::SHLL_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7223 { 8067 /* shll.ph */, Mips::SHLL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7224 { 8075 /* shll.qb */, Mips::SHLL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7225 { 8075 /* shll.qb */, Mips::SHLL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7226 { 8083 /* shll_s.ph */, Mips::SHLL_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7227 { 8083 /* shll_s.ph */, Mips::SHLL_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7228 { 8093 /* shll_s.w */, Mips::SHLL_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7229 { 8093 /* shll_s.w */, Mips::SHLL_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7230 { 8102 /* shllv.ph */, Mips::SHLLV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7231 { 8102 /* shllv.ph */, Mips::SHLLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7232 { 8111 /* shllv.qb */, Mips::SHLLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7233 { 8111 /* shllv.qb */, Mips::SHLLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7234 { 8120 /* shllv_s.ph */, Mips::SHLLV_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7235 { 8120 /* shllv_s.ph */, Mips::SHLLV_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7236 { 8131 /* shllv_s.w */, Mips::SHLLV_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7237 { 8131 /* shllv_s.w */, Mips::SHLLV_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7238 { 8141 /* shra.ph */, Mips::SHRA_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7239 { 8141 /* shra.ph */, Mips::SHRA_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7240 { 8149 /* shra.qb */, Mips::SHRA_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7241 { 8149 /* shra.qb */, Mips::SHRA_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7242 { 8157 /* shra_r.ph */, Mips::SHRA_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7243 { 8157 /* shra_r.ph */, Mips::SHRA_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7244 { 8167 /* shra_r.qb */, Mips::SHRA_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7245 { 8167 /* shra_r.qb */, Mips::SHRA_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7246 { 8177 /* shra_r.w */, Mips::SHRA_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7247 { 8177 /* shra_r.w */, Mips::SHRA_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7248 { 8186 /* shrav.ph */, Mips::SHRAV_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7249 { 8186 /* shrav.ph */, Mips::SHRAV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7250 { 8195 /* shrav.qb */, Mips::SHRAV_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7251 { 8195 /* shrav.qb */, Mips::SHRAV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7252 { 8204 /* shrav_r.ph */, Mips::SHRAV_R_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7253 { 8204 /* shrav_r.ph */, Mips::SHRAV_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7254 { 8215 /* shrav_r.qb */, Mips::SHRAV_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7255 { 8215 /* shrav_r.qb */, Mips::SHRAV_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7256 { 8226 /* shrav_r.w */, Mips::SHRAV_R_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7257 { 8226 /* shrav_r.w */, Mips::SHRAV_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7258 { 8236 /* shrl.ph */, Mips::SHRL_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7259 { 8236 /* shrl.ph */, Mips::SHRL_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7260 { 8244 /* shrl.qb */, Mips::SHRL_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7261 { 8244 /* shrl.qb */, Mips::SHRL_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm3_01_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm3_0 }, }, 7262 { 8252 /* shrlv.ph */, Mips::SHRLV_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7263 { 8252 /* shrlv.ph */, Mips::SHRLV_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7264 { 8261 /* shrlv.qb */, Mips::SHRLV_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7265 { 8261 /* shrlv.qb */, Mips::SHRLV_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7266 { 8270 /* sld.b */, Mips::SLD_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7267 { 8276 /* sld.d */, Mips::SLD_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7268 { 8282 /* sld.h */, Mips::SLD_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7269 { 8288 /* sld.w */, Mips::SLD_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7270 { 8294 /* sldi.b */, Mips::SLDI_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 7271 { 8301 /* sldi.d */, Mips::SLDI_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, 7272 { 8308 /* sldi.h */, Mips::SLDI_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 7273 { 8315 /* sldi.w */, Mips::SLDI_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 7274 { 8322 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7275 { 8322 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7276 { 8322 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7277 { 8322 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7278 { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7279 { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7280 { 8322 /* sll */, Mips::SllX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, 7281 { 8322 /* sll */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7282 { 8322 /* sll */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7283 { 8322 /* sll */, Mips::SLL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7284 { 8322 /* sll */, Mips::SLL_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7285 { 8322 /* sll */, Mips::SLL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7286 { 8326 /* sll.b */, Mips::SLL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7287 { 8332 /* sll.d */, Mips::SLL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7288 { 8338 /* sll.h */, Mips::SLL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7289 { 8344 /* sll.w */, Mips::SLL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7290 { 8350 /* sll16 */, Mips::SLL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7291 { 8350 /* sll16 */, Mips::SLL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7292 { 8356 /* slli.b */, Mips::SLLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7293 { 8363 /* slli.d */, Mips::SLLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7294 { 8370 /* slli.h */, Mips::SLLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7295 { 8377 /* slli.w */, Mips::SLLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7296 { 8384 /* sllv */, Mips::SllvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7297 { 8384 /* sllv */, Mips::SLLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7298 { 8384 /* sllv */, Mips::SLLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7299 { 8389 /* slt */, Mips::SltRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7300 { 8389 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7301 { 8389 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7302 { 8389 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7303 { 8389 /* slt */, Mips::SLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7304 { 8389 /* slt */, Mips::SLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7305 { 8389 /* slt */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7306 { 8389 /* slt */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7307 { 8389 /* slt */, Mips::SLTImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7308 { 8393 /* slti */, Mips::SltiRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 7309 { 8393 /* slti */, Mips::SLTi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7310 { 8393 /* slti */, Mips::SLTi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7311 { 8393 /* slti */, Mips::SltiRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 7312 { 8398 /* sltiu */, Mips::SltiuRxImmX16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16 }, }, 7313 { 8398 /* sltiu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7314 { 8398 /* sltiu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm161_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm16 }, }, 7315 { 8398 /* sltiu */, Mips::SltiuRxImm16, Convert__Reg1_0__SImm161_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_SImm16, MCK__35_, MCK_16, MCK_bit, MCK_inst }, }, 7316 { 8404 /* sltu */, Mips::SltuRxRy16, Convert__Reg1_0__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7317 { 8404 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7318 { 8404 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7319 { 8404 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_Imm }, }, 7320 { 8404 /* sltu */, Mips::SLTu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7321 { 8404 /* sltu */, Mips::SLTu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7322 { 8404 /* sltu */, Mips::SLTiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7323 { 8404 /* sltu */, Mips::SLTiu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7324 { 8404 /* sltu */, Mips::SLTUImm64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_IsGP64bit, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7325 { 8409 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7326 { 8409 /* sne */, Mips::SNE, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7327 { 8413 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__ConstantSImm10_01_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7328 { 8413 /* snei */, Mips::SNEi, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__ConstantSImm10_01_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_ConstantSImm10_0 }, }, 7329 { 8418 /* splat.b */, Mips::SPLAT_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7330 { 8426 /* splat.d */, Mips::SPLAT_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7331 { 8434 /* splat.h */, Mips::SPLAT_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7332 { 8442 /* splat.w */, Mips::SPLAT_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__GPR32AsmReg1_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_GPR32AsmReg, MCK__93_ }, }, 7333 { 8450 /* splati.b */, Mips::SPLATI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm4_0, MCK__93_ }, }, 7334 { 8459 /* splati.d */, Mips::SPLATI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm1_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm1_0, MCK__93_ }, }, 7335 { 8468 /* splati.h */, Mips::SPLATI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm3_0, MCK__93_ }, }, 7336 { 8477 /* splati.w */, Mips::SPLATI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm2_01_3, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK__91_, MCK_ConstantUImm2_0, MCK__93_ }, }, 7337 { 8486 /* sqrt.d */, Mips::FSQRT_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7338 { 8486 /* sqrt.d */, Mips::FSQRT_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7339 { 8486 /* sqrt.d */, Mips::FSQRT_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7340 { 8486 /* sqrt.d */, Mips::FSQRT_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7341 { 8493 /* sqrt.s */, Mips::FSQRT_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7342 { 8493 /* sqrt.s */, Mips::FSQRT_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7343 { 8500 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7344 { 8500 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7345 { 8500 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7346 { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7347 { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7348 { 8500 /* sra */, Mips::SraX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, 7349 { 8500 /* sra */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7350 { 8500 /* sra */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7351 { 8500 /* sra */, Mips::SRA, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7352 { 8500 /* sra */, Mips::SRA_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7353 { 8504 /* sra.b */, Mips::SRA_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7354 { 8510 /* sra.d */, Mips::SRA_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7355 { 8516 /* sra.h */, Mips::SRA_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7356 { 8522 /* sra.w */, Mips::SRA_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7357 { 8528 /* srai.b */, Mips::SRAI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7358 { 8535 /* srai.d */, Mips::SRAI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7359 { 8542 /* srai.h */, Mips::SRAI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7360 { 8549 /* srai.w */, Mips::SRAI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7361 { 8556 /* srar.b */, Mips::SRAR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7362 { 8563 /* srar.d */, Mips::SRAR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7363 { 8570 /* srar.h */, Mips::SRAR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7364 { 8577 /* srar.w */, Mips::SRAR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7365 { 8584 /* srari.b */, Mips::SRARI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7366 { 8592 /* srari.d */, Mips::SRARI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7367 { 8600 /* srari.h */, Mips::SRARI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7368 { 8608 /* srari.w */, Mips::SRARI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7369 { 8616 /* srav */, Mips::SravRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7370 { 8616 /* srav */, Mips::SRAV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7371 { 8616 /* srav */, Mips::SRAV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7372 { 8621 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7373 { 8621 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7374 { 8621 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7375 { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7376 { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__ConstantUImm5_01_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7377 { 8621 /* srl */, Mips::SrlX16, Convert__Reg1_0__Reg1_1__ConstantUImm5_01_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_ConstantUImm5_0 }, }, 7378 { 8621 /* srl */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7379 { 8621 /* srl */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7380 { 8621 /* srl */, Mips::SRL, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7381 { 8621 /* srl */, Mips::SRL_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm5_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm5_0 }, }, 7382 { 8625 /* srl.b */, Mips::SRL_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7383 { 8631 /* srl.d */, Mips::SRL_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7384 { 8637 /* srl.h */, Mips::SRL_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7385 { 8643 /* srl.w */, Mips::SRL_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7386 { 8649 /* srl16 */, Mips::SRL16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7387 { 8649 /* srl16 */, Mips::SRL16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Imm1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_Imm }, }, 7388 { 8655 /* srli.b */, Mips::SRLI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7389 { 8662 /* srli.d */, Mips::SRLI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7390 { 8669 /* srli.h */, Mips::SRLI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7391 { 8676 /* srli.w */, Mips::SRLI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7392 { 8683 /* srlr.b */, Mips::SRLR_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7393 { 8690 /* srlr.d */, Mips::SRLR_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7394 { 8697 /* srlr.h */, Mips::SRLR_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7395 { 8704 /* srlr.w */, Mips::SRLR_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7396 { 8711 /* srlri.b */, Mips::SRLRI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm3_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm3_0 }, }, 7397 { 8719 /* srlri.d */, Mips::SRLRI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm6_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm6_0 }, }, 7398 { 8727 /* srlri.h */, Mips::SRLRI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm4_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm4_0 }, }, 7399 { 8735 /* srlri.w */, Mips::SRLRI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7400 { 8743 /* srlv */, Mips::SrlvRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7401 { 8743 /* srlv */, Mips::SRLV, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7402 { 8743 /* srlv */, Mips::SRLV_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7403 { 8748 /* ssnop */, Mips::SSNOP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 7404 { 8748 /* ssnop */, Mips::SSNOP_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 7405 { 8748 /* ssnop */, Mips::SSNOP_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 7406 { 8754 /* st.b */, Mips::ST_B, Convert__MSA128AsmReg1_0__MemOffsetSimm102_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10 }, }, 7407 { 8759 /* st.d */, Mips::ST_D, Convert__MSA128AsmReg1_0__MemOffsetSimm10_32_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_3 }, }, 7408 { 8764 /* st.h */, Mips::ST_H, Convert__MSA128AsmReg1_0__MemOffsetSimm10_12_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_1 }, }, 7409 { 8769 /* st.w */, Mips::ST_W, Convert__MSA128AsmReg1_0__MemOffsetSimm10_22_1, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MemOffsetSimm10_2 }, }, 7410 { 8774 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7411 { 8774 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7412 { 8774 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7413 { 8774 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_InvNum }, }, 7414 { 8774 /* sub */, Mips::SUB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7415 { 8774 /* sub */, Mips::SUB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7416 { 8774 /* sub */, Mips::SUB_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7417 { 8774 /* sub */, Mips::ADDi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, 7418 { 8778 /* sub.d */, Mips::FSUB_D32, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7419 { 8778 /* sub.d */, Mips::FSUB_D32_MM, Convert__AFGR64AsmReg1_0__AFGR64AsmReg1_1__AFGR64AsmReg1_2, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_AFGR64AsmReg, MCK_AFGR64AsmReg, MCK_AFGR64AsmReg }, }, 7420 { 8778 /* sub.d */, Mips::FSUB_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7421 { 8778 /* sub.d */, Mips::FSUB_D64_MM, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1__FGR64AsmReg1_2, Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7422 { 8784 /* sub.s */, Mips::FSUB_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7423 { 8784 /* sub.s */, Mips::FSUB_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_2__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7424 { 8784 /* sub.s */, Mips::FSUB_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__FGR32AsmReg1_2, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7425 { 8790 /* subq.ph */, Mips::SUBQ_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7426 { 8790 /* subq.ph */, Mips::SUBQ_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7427 { 8798 /* subq_s.ph */, Mips::SUBQ_S_PH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7428 { 8798 /* subq_s.ph */, Mips::SUBQ_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7429 { 8808 /* subq_s.w */, Mips::SUBQ_S_W_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7430 { 8808 /* subq_s.w */, Mips::SUBQ_S_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7431 { 8817 /* subqh.ph */, Mips::SUBQH_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7432 { 8817 /* subqh.ph */, Mips::SUBQH_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7433 { 8826 /* subqh.w */, Mips::SUBQH_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7434 { 8826 /* subqh.w */, Mips::SUBQH_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7435 { 8834 /* subqh_r.ph */, Mips::SUBQH_R_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7436 { 8834 /* subqh_r.ph */, Mips::SUBQH_R_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7437 { 8845 /* subqh_r.w */, Mips::SUBQH_R_W_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7438 { 8845 /* subqh_r.w */, Mips::SUBQH_R_W, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7439 { 8855 /* subs_s.b */, Mips::SUBS_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7440 { 8864 /* subs_s.d */, Mips::SUBS_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7441 { 8873 /* subs_s.h */, Mips::SUBS_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7442 { 8882 /* subs_s.w */, Mips::SUBS_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7443 { 8891 /* subs_u.b */, Mips::SUBS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7444 { 8900 /* subs_u.d */, Mips::SUBS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7445 { 8909 /* subs_u.h */, Mips::SUBS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7446 { 8918 /* subs_u.w */, Mips::SUBS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7447 { 8927 /* subsus_u.b */, Mips::SUBSUS_U_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7448 { 8938 /* subsus_u.d */, Mips::SUBSUS_U_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7449 { 8949 /* subsus_u.h */, Mips::SUBSUS_U_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7450 { 8960 /* subsus_u.w */, Mips::SUBSUS_U_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7451 { 8971 /* subsuu_s.b */, Mips::SUBSUU_S_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7452 { 8982 /* subsuu_s.d */, Mips::SUBSUU_S_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7453 { 8993 /* subsuu_s.h */, Mips::SUBSUU_S_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7454 { 9004 /* subsuu_s.w */, Mips::SUBSUU_S_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7455 { 9015 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7456 { 9015 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7457 { 9015 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7458 { 9015 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__InvNum1_1, 0, { MCK_GPR32AsmReg, MCK_InvNum }, }, 7459 { 9015 /* subu */, Mips::SubuRxRyRz16, Convert__Reg1_0__Reg1_1__Reg1_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_CPU16Regs }, }, 7460 { 9015 /* subu */, Mips::SUBU_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7461 { 9015 /* subu */, Mips::SUBu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7462 { 9015 /* subu */, Mips::SUBu_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7463 { 9015 /* subu */, Mips::ADDiu, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__InvNum1_2, 0, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_InvNum }, }, 7464 { 9020 /* subu.ph */, Mips::SUBU_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7465 { 9020 /* subu.ph */, Mips::SUBU_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7466 { 9028 /* subu.qb */, Mips::SUBU_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7467 { 9028 /* subu.qb */, Mips::SUBU_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7468 { 9036 /* subu16 */, Mips::SUBU16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7469 { 9036 /* subu16 */, Mips::SUBU16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__GPRMM16AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7470 { 9043 /* subu_s.ph */, Mips::SUBU_S_PH_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7471 { 9043 /* subu_s.ph */, Mips::SUBU_S_PH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7472 { 9053 /* subu_s.qb */, Mips::SUBU_S_QB_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7473 { 9053 /* subu_s.qb */, Mips::SUBU_S_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSP, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7474 { 9063 /* subuh.qb */, Mips::SUBUH_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7475 { 9063 /* subuh.qb */, Mips::SUBUH_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7476 { 9072 /* subuh_r.qb */, Mips::SUBUH_R_QB_MMR2, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7477 { 9072 /* subuh_r.qb */, Mips::SUBUH_R_QB, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasDSPR2, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7478 { 9083 /* subv.b */, Mips::SUBV_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7479 { 9090 /* subv.d */, Mips::SUBV_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7480 { 9097 /* subv.h */, Mips::SUBV_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7481 { 9104 /* subv.w */, Mips::SUBV_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7482 { 9111 /* subvi.b */, Mips::SUBVI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7483 { 9119 /* subvi.d */, Mips::SUBVI_D, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7484 { 9127 /* subvi.h */, Mips::SUBVI_H, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7485 { 9135 /* subvi.w */, Mips::SUBVI_W, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm5_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm5_0 }, }, 7486 { 9143 /* suxc1 */, Mips::SUXC1, Convert__AFGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_AFGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7487 { 9143 /* suxc1 */, Mips::SUXC164, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7488 { 9143 /* suxc1 */, Mips::SUXC1_MM, Convert__FGR64AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7489 { 9149 /* sw */, Mips::SWSP_MM, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 7490 { 9149 /* sw */, Mips::SWSP_MMR6, Convert__GPR32AsmReg1_0__MicroMipsMemSP2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_MicroMipsMemSP }, }, 7491 { 9149 /* sw */, Mips::SW, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7492 { 9149 /* sw */, Mips::SWDSP, Convert__GPR32AsmReg1_0__Mem2_1, Feature_NotInMips16Mode|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 7493 { 9149 /* sw */, Mips::SWDSP_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_Mem }, }, 7494 { 9149 /* sw */, Mips::SW_MMR6, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7495 { 9149 /* sw */, Mips::SW_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7496 { 9149 /* sw */, Mips::SwRxRyOffMemX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs, MCK_SImm16 }, }, 7497 { 9149 /* sw */, Mips::SwRxSpImmX16, Convert__Reg1_0__Reg1_1__SImm161_2, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16RegsPlusSP, MCK_SImm16 }, }, 7498 { 9152 /* sw16 */, Mips::SW16_MM, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7499 { 9152 /* sw16 */, Mips::SW16_MMR6, Convert__GPRMM16AsmRegZero1_0__MicroMipsMem2_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmRegZero, MCK_MicroMipsMem }, }, 7500 { 9157 /* swc1 */, Mips::SWC1, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 7501 { 9157 /* swc1 */, Mips::SWC1_MM, Convert__FGR32AsmReg1_0__MemOffsetSimm162_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_MemOffsetSimm16 }, }, 7502 { 9162 /* swc2 */, Mips::SWC2_R6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 7503 { 9162 /* swc2 */, Mips::SWC2_MMR6, Convert__COP2AsmReg1_0__MemOffsetSimm112_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_COP2AsmReg, MCK_MemOffsetSimm11 }, }, 7504 { 9162 /* swc2 */, Mips::SWC2, Convert__COP2AsmReg1_0__MemOffsetSimm162_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_COP2AsmReg, MCK_MemOffsetSimm16 }, }, 7505 { 9167 /* swc3 */, Mips::SWC3, Convert__COP3AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, { MCK_COP3AsmReg, MCK_Mem }, }, 7506 { 9172 /* swe */, Mips::SWE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7507 { 9172 /* swe */, Mips::SWE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7508 { 9176 /* swl */, Mips::SWL, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7509 { 9176 /* swl */, Mips::SWL_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7510 { 9180 /* swle */, Mips::SWLE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7511 { 9180 /* swle */, Mips::SWLE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7512 { 9185 /* swm */, Mips::SWM_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, }, 7513 { 9189 /* swm16 */, Mips::SWM16_MM, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 7514 { 9189 /* swm16 */, Mips::SWM16_MMR6, Convert__RegList161_0__MemOffsetUimm42_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_RegList16, MCK_MemOffsetUimm4 }, }, 7515 { 9195 /* swm32 */, Mips::SWM32_MM, Convert__RegList1_0__Mem2_1, Feature_InMicroMips, { MCK_RegList, MCK_Mem }, }, 7516 { 9201 /* swp */, Mips::SWP_MM, ConvertCustom_ConvertXWPOperands, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm12 }, }, 7517 { 9205 /* swr */, Mips::SWR, Convert__GPR32AsmReg1_0__Mem2_1, Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_Mem }, }, 7518 { 9205 /* swr */, Mips::SWR_MM, Convert__GPR32AsmReg1_0__Mem2_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_Mem }, }, 7519 { 9209 /* swre */, Mips::SWRE, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7520 { 9209 /* swre */, Mips::SWRE_MM, Convert__GPR32AsmReg1_0__MemOffsetSimm92_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, { MCK_GPR32AsmReg, MCK_MemOffsetSimm9 }, }, 7521 { 9214 /* swxc1 */, Mips::SWXC1, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7522 { 9214 /* swxc1 */, Mips::SWXC1_MM, Convert__FGR32AsmReg1_0__GPR32AsmReg1_3__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_GPR32AsmReg, MCK__40_, MCK_GPR32AsmReg, MCK__41_ }, }, 7523 { 9220 /* sync */, Mips::SYNC, Convert__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { }, }, 7524 { 9220 /* sync */, Mips::SYNC_MMR6, Convert__imm_95_0, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 7525 { 9220 /* sync */, Mips::SYNC_MM, Convert__imm_95_0, Feature_InMicroMips, { }, }, 7526 { 9220 /* sync */, Mips::SYNC, Convert__ConstantUImm5_01_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_ConstantUImm5_0 }, }, 7527 { 9220 /* sync */, Mips::SYNC_MMR6, Convert__ConstantUImm5_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm5_0 }, }, 7528 { 9220 /* sync */, Mips::SYNC_MM, Convert__ConstantUImm5_01_0, Feature_InMicroMips, { MCK_ConstantUImm5_0 }, }, 7529 { 9225 /* synci */, Mips::SYNCI, Convert__MemOffsetSimm162_0, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_MemOffsetSimm16 }, }, 7530 { 9225 /* synci */, Mips::SYNCI_MM, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_NotMips32r6, { MCK_MemOffsetSimm16 }, }, 7531 { 9225 /* synci */, Mips::SYNCI_MMR6, Convert__MemOffsetSimm162_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_MemOffsetSimm16 }, }, 7532 { 9231 /* synciobdma */, Mips::SYNC, Convert__imm_95_2, Feature_HasMips64|Feature_HasCnMips, { }, }, 7533 { 9242 /* syncs */, Mips::SYNC, Convert__imm_95_6, Feature_HasMips64|Feature_HasCnMips, { }, }, 7534 { 9248 /* syncw */, Mips::SYNC, Convert__imm_95_4, Feature_HasMips64|Feature_HasCnMips, { }, }, 7535 { 9254 /* syncws */, Mips::SYNC, Convert__imm_95_5, Feature_HasMips64|Feature_HasCnMips, { }, }, 7536 { 9261 /* syscall */, Mips::SYSCALL, Convert__imm_95_0, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 7537 { 9261 /* syscall */, Mips::SYSCALL_MM, Convert__imm_95_0, Feature_InMicroMips, { }, }, 7538 { 9261 /* syscall */, Mips::SYSCALL_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, }, 7539 { 9261 /* syscall */, Mips::SYSCALL, Convert__ConstantUImm20_01_0, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_ConstantUImm20_0 }, }, 7540 { 9269 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7541 { 9269 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7542 { 9269 /* teq */, Mips::TEQ_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7543 { 9269 /* teq */, Mips::TEQ, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7544 { 9273 /* teqi */, Mips::TEQI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7545 { 9273 /* teqi */, Mips::TEQI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7546 { 9278 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7547 { 9278 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7548 { 9278 /* tge */, Mips::TGE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7549 { 9278 /* tge */, Mips::TGE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7550 { 9282 /* tgei */, Mips::TGEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7551 { 9282 /* tgei */, Mips::TGEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7552 { 9287 /* tgeiu */, Mips::TGEIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7553 { 9287 /* tgeiu */, Mips::TGEIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7554 { 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7555 { 9293 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7556 { 9293 /* tgeu */, Mips::TGEU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7557 { 9293 /* tgeu */, Mips::TGEU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7558 { 9298 /* tlbginv */, Mips::TLBGINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 7559 { 9298 /* tlbginv */, Mips::TLBGINV_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 7560 { 9306 /* tlbginvf */, Mips::TLBGINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 7561 { 9306 /* tlbginvf */, Mips::TLBGINVF_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 7562 { 9315 /* tlbgp */, Mips::TLBGP, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 7563 { 9315 /* tlbgp */, Mips::TLBGP_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 7564 { 9321 /* tlbgr */, Mips::TLBGR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 7565 { 9321 /* tlbgr */, Mips::TLBGR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 7566 { 9327 /* tlbgwi */, Mips::TLBGWI, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 7567 { 9327 /* tlbgwi */, Mips::TLBGWI_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 7568 { 9334 /* tlbgwr */, Mips::TLBGWR, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, { }, }, 7569 { 9334 /* tlbgwr */, Mips::TLBGWR_MM, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, { }, }, 7570 { 9341 /* tlbinv */, Mips::TLBINV, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { }, }, 7571 { 9341 /* tlbinv */, Mips::TLBINV_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 7572 { 9348 /* tlbinvf */, Mips::TLBINVF, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, { }, }, 7573 { 9348 /* tlbinvf */, Mips::TLBINVF_MMR6, Convert_NoOperands, Feature_InMicroMips|Feature_HasMips32r6, { }, }, 7574 { 9356 /* tlbp */, Mips::TLBP, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 7575 { 9356 /* tlbp */, Mips::TLBP_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 7576 { 9361 /* tlbr */, Mips::TLBR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 7577 { 9361 /* tlbr */, Mips::TLBR_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 7578 { 9366 /* tlbwi */, Mips::TLBWI, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 7579 { 9366 /* tlbwi */, Mips::TLBWI_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 7580 { 9372 /* tlbwr */, Mips::TLBWR, Convert_NoOperands, Feature_HasStdEnc|Feature_NotInMicroMips, { }, }, 7581 { 9372 /* tlbwr */, Mips::TLBWR_MM, Convert_NoOperands, Feature_InMicroMips, { }, }, 7582 { 9378 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7583 { 9378 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7584 { 9378 /* tlt */, Mips::TLT_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7585 { 9378 /* tlt */, Mips::TLT, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7586 { 9382 /* tlti */, Mips::TLTI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7587 { 9382 /* tlti */, Mips::TLTI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7588 { 9387 /* tltiu */, Mips::TTLTIU, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7589 { 9387 /* tltiu */, Mips::TLTIU_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7590 { 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7591 { 9393 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7592 { 9393 /* tltu */, Mips::TLTU_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7593 { 9393 /* tltu */, Mips::TLTU, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7594 { 9398 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7595 { 9398 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__imm_95_0, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7596 { 9398 /* tne */, Mips::TNE_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm4_01_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm4_0 }, }, 7597 { 9398 /* tne */, Mips::TNE, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__ConstantUImm10_01_2, Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7598 { 9402 /* tnei */, Mips::TNEI, Convert__GPR32AsmReg1_0__SImm161_1, Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7599 { 9402 /* tnei */, Mips::TNEI_MM, Convert__GPR32AsmReg1_0__SImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_SImm16 }, }, 7600 { 9407 /* trunc.l.d */, Mips::TRUNC_L_D64, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7601 { 9407 /* trunc.l.d */, Mips::TRUNC_L_D_MMR6, Convert__FGR64AsmReg1_0__FGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR64AsmReg }, }, 7602 { 9417 /* trunc.l.s */, Mips::TRUNC_L_S, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 7603 { 9417 /* trunc.l.s */, Mips::TRUNC_L_S_MMR6, Convert__FGR64AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR64AsmReg, MCK_FGR32AsmReg }, }, 7604 { 9427 /* trunc.w.d */, Mips::TRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7605 { 9427 /* trunc.w.d */, Mips::TRUNC_W_D_MMR6, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7606 { 9427 /* trunc.w.d */, Mips::TRUNC_W_MM, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1, Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg }, }, 7607 { 9427 /* trunc.w.d */, Mips::TRUNC_W_D64, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1, Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR64AsmReg }, }, 7608 { 9427 /* trunc.w.d */, Mips::PseudoTRUNC_W_D32, Convert__FGR32AsmReg1_0__AFGR64AsmReg1_1__GPR32AsmReg1_2, Feature_NotFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_AFGR64AsmReg, MCK_GPR32AsmReg }, }, 7609 { 9427 /* trunc.w.d */, Mips::PseudoTRUNC_W_D, Convert__FGR32AsmReg1_0__FGR64AsmReg1_1__GPR32AsmReg1_2, Feature_IsFP64bit|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR64AsmReg, MCK_GPR32AsmReg }, }, 7610 { 9437 /* trunc.w.s */, Mips::TRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7611 { 9437 /* trunc.w.s */, Mips::TRUNC_W_S_MMR6, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7612 { 9437 /* trunc.w.s */, Mips::TRUNC_W_S_MM, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1, Feature_InMicroMips|Feature_IsNotSoftFloat, { MCK_FGR32AsmReg, MCK_FGR32AsmReg }, }, 7613 { 9437 /* trunc.w.s */, Mips::PseudoTRUNC_W_S, Convert__FGR32AsmReg1_0__FGR32AsmReg1_1__GPR32AsmReg1_2, 0, { MCK_FGR32AsmReg, MCK_FGR32AsmReg, MCK_GPR32AsmReg }, }, 7614 { 9447 /* ulh */, Mips::Ulh, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, }, 7615 { 9451 /* ulhu */, Mips::Ulhu, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, }, 7616 { 9456 /* ulw */, Mips::Ulw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, }, 7617 { 9460 /* ush */, Mips::Ush, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, }, 7618 { 9464 /* usw */, Mips::Usw, Convert__GPR32AsmReg1_0__Mem2_1, 0, { MCK_GPR32AsmReg, MCK_Mem }, }, 7619 { 9468 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7620 { 9468 /* v3mulu */, Mips::V3MULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7621 { 9475 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7622 { 9475 /* vmm0 */, Mips::VMM0, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7623 { 9480 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__GPR64AsmReg1_1, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7624 { 9480 /* vmulu */, Mips::VMULU, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__GPR64AsmReg1_2, Feature_HasCnMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_GPR64AsmReg }, }, 7625 { 9486 /* vshf.b */, Mips::VSHF_B, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7626 { 9493 /* vshf.d */, Mips::VSHF_D, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7627 { 9500 /* vshf.h */, Mips::VSHF_H, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7628 { 9507 /* vshf.w */, Mips::VSHF_W, Convert__MSA128AsmReg1_0__Tie0_1_1__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7629 { 9514 /* wait */, Mips::WAIT, Convert_NoOperands, Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotInMicroMips, { }, }, 7630 { 9514 /* wait */, Mips::WAIT_MM, Convert__imm_95_0, Feature_InMicroMips, { }, }, 7631 { 9514 /* wait */, Mips::WAIT_MMR6, Convert__ConstantUImm10_01_0, Feature_InMicroMips|Feature_HasMips32r6, { MCK_ConstantUImm10_0 }, }, 7632 { 9514 /* wait */, Mips::WAIT_MM, Convert__ConstantUImm10_01_0, Feature_InMicroMips, { MCK_ConstantUImm10_0 }, }, 7633 { 9519 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7634 { 9519 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__imm_95_31, Feature_HasDSP|Feature_InMicroMips, { MCK_GPR32AsmReg }, }, 7635 { 9519 /* wrdsp */, Mips::WRDSP_MM, Convert__GPR32AsmReg1_0__ConstantUImm7_01_1, Feature_InMicroMips|Feature_HasDSP, { MCK_GPR32AsmReg, MCK_ConstantUImm7_0 }, }, 7636 { 9519 /* wrdsp */, Mips::WRDSP, Convert__GPR32AsmReg1_0__ConstantUImm10_01_1, Feature_HasDSP|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_ConstantUImm10_0 }, }, 7637 { 9525 /* wrpgpr */, Mips::WRPGPR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7638 { 9532 /* wsbh */, Mips::WSBH, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7639 { 9532 /* wsbh */, Mips::WSBH_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7640 { 9532 /* wsbh */, Mips::WSBH_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7641 { 9537 /* xor */, Mips::XorRxRxRy16, Convert__Reg1_0__Tie0_1_1__Reg1_1, Feature_InMips16Mode, { MCK_CPU16Regs, MCK_CPU16Regs }, }, 7642 { 9537 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7643 { 9537 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7644 { 9537 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7645 { 9537 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7646 { 9537 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7647 { 9537 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__SImm32_Relaxed1_1, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7648 { 9537 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_0__Imm1_1, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_Imm }, }, 7649 { 9537 /* xor */, Mips::XOR, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7650 { 9537 /* xor */, Mips::XOR_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7651 { 9537 /* xor */, Mips::XOR_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__GPR32AsmReg1_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7652 { 9537 /* xor */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7653 { 9537 /* xor */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7654 { 9537 /* xor */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__SImm32_Relaxed1_2, Feature_InMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_SImm32_Relaxed }, }, 7655 { 9537 /* xor */, Mips::XORi64, Convert__GPR64AsmReg1_0__GPR64AsmReg1_1__Imm1_2, Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, { MCK_GPR64AsmReg, MCK_GPR64AsmReg, MCK_Imm }, }, 7656 { 9541 /* xor.v */, Mips::XOR_V, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__MSA128AsmReg1_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_MSA128AsmReg }, }, 7657 { 9547 /* xor16 */, Mips::XOR16_MM, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7658 { 9547 /* xor16 */, Mips::XOR16_MMR6, Convert__GPRMM16AsmReg1_0__GPRMM16AsmReg1_1__Tie0_1_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPRMM16AsmReg, MCK_GPRMM16AsmReg }, }, 7659 { 9553 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7660 { 9553 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7661 { 9553 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_0__UImm161_1, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_UImm16 }, }, 7662 { 9553 /* xori */, Mips::XORI_MMR6, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_HasMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7663 { 9553 /* xori */, Mips::XORi, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_HasStdEnc|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7664 { 9553 /* xori */, Mips::XORi_MM, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1__UImm161_2, Feature_InMicroMips|Feature_NotMips32r6, { MCK_GPR32AsmReg, MCK_GPR32AsmReg, MCK_UImm16 }, }, 7665 { 9558 /* xori.b */, Mips::XORI_B, Convert__MSA128AsmReg1_0__MSA128AsmReg1_1__ConstantUImm8_01_2, Feature_HasStdEnc|Feature_HasMSA, { MCK_MSA128AsmReg, MCK_MSA128AsmReg, MCK_ConstantUImm8_0 }, }, 7666 { 9565 /* yield */, Mips::YIELD, Convert__regZERO__GPR32AsmReg1_0, Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg }, }, 7667 { 9565 /* yield */, Mips::YIELD, Convert__GPR32AsmReg1_0__GPR32AsmReg1_1, Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, { MCK_GPR32AsmReg, MCK_GPR32AsmReg }, }, 7668}; 7669 7670#include "llvm/Support/Debug.h" 7671#include "llvm/Support/Format.h" 7672 7673unsigned MipsAsmParser:: 7674MatchInstructionImpl(const OperandVector &Operands, 7675 MCInst &Inst, 7676 uint64_t &ErrorInfo, 7677 bool matchingInlineAsm, unsigned VariantID) { 7678 // Eliminate obvious mismatches. 7679 if (Operands.size() > 9) { 7680 ErrorInfo = 9; 7681 return Match_InvalidOperand; 7682 } 7683 7684 // Get the current feature set. 7685 uint64_t AvailableFeatures = getAvailableFeatures(); 7686 7687 // Get the instruction mnemonic, which is the first token. 7688 StringRef Mnemonic = ((MipsOperand&)*Operands[0]).getToken(); 7689 7690 // Some state to try to produce better error messages. 7691 bool HadMatchOtherThanFeatures = false; 7692 bool HadMatchOtherThanPredicate = false; 7693 unsigned RetCode = Match_InvalidOperand; 7694 uint64_t MissingFeatures = ~0ULL; 7695 // Set ErrorInfo to the operand that mismatches if it is 7696 // wrong for all instances of the instruction. 7697 ErrorInfo = ~0ULL; 7698 // Find the appropriate table for this asm variant. 7699 const MatchEntry *Start, *End; 7700 switch (VariantID) { 7701 default: llvm_unreachable("invalid variant!"); 7702 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 7703 } 7704 // Search the table. 7705 auto MnemonicRange = std::equal_range(Start, End, Mnemonic, LessOpcode()); 7706 7707 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "AsmMatcher: found " << 7708 std::distance(MnemonicRange.first, MnemonicRange.second) << 7709 " encodings with mnemonic '" << Mnemonic << "'\n"); 7710 7711 // Return a more specific error code if no mnemonics match. 7712 if (MnemonicRange.first == MnemonicRange.second) 7713 return Match_MnemonicFail; 7714 7715 for (const MatchEntry *it = MnemonicRange.first, *ie = MnemonicRange.second; 7716 it != ie; ++it) { 7717 bool HasRequiredFeatures = 7718 (AvailableFeatures & it->RequiredFeatures) == it->RequiredFeatures; 7719 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Trying to match opcode " 7720 << MII.getName(it->Opcode) << "\n"); 7721 // equal_range guarantees that instruction mnemonic matches. 7722 assert(Mnemonic == it->getMnemonic()); 7723 bool OperandsValid = true; 7724 for (unsigned FormalIdx = 0, ActualIdx = 1; FormalIdx != 8; ++FormalIdx) { 7725 auto Formal = static_cast<MatchClassKind>(it->Classes[FormalIdx]); 7726 DEBUG_WITH_TYPE("asm-matcher", 7727 dbgs() << " Matching formal operand class " << getMatchClassName(Formal) 7728 << " against actual operand at index " << ActualIdx); 7729 if (ActualIdx < Operands.size()) 7730 DEBUG_WITH_TYPE("asm-matcher", dbgs() << " ("; 7731 Operands[ActualIdx]->print(dbgs()); dbgs() << "): "); 7732 else 7733 DEBUG_WITH_TYPE("asm-matcher", dbgs() << ": "); 7734 if (ActualIdx >= Operands.size()) { 7735 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "actual operand index out of range "); 7736 OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass); 7737 if (!OperandsValid) ErrorInfo = ActualIdx; 7738 break; 7739 } 7740 MCParsedAsmOperand &Actual = *Operands[ActualIdx]; 7741 unsigned Diag = validateOperandClass(Actual, Formal); 7742 if (Diag == Match_Success) { 7743 DEBUG_WITH_TYPE("asm-matcher", 7744 dbgs() << "match success using generic matcher\n"); 7745 ++ActualIdx; 7746 continue; 7747 } 7748 // If the generic handler indicates an invalid operand 7749 // failure, check for a special case. 7750 if (Diag != Match_Success) { 7751 unsigned TargetDiag = validateTargetOperandClass(Actual, Formal); 7752 if (TargetDiag == Match_Success) { 7753 DEBUG_WITH_TYPE("asm-matcher", 7754 dbgs() << "match success using target matcher\n"); 7755 ++ActualIdx; 7756 continue; 7757 } 7758 // If the target matcher returned a specific error code use 7759 // that, else use the one from the generic matcher. 7760 if (TargetDiag != Match_InvalidOperand && HasRequiredFeatures) 7761 Diag = TargetDiag; 7762 } 7763 // If current formal operand wasn't matched and it is optional 7764 // then try to match next formal operand 7765 if (Diag == Match_InvalidOperand && isSubclass(Formal, OptionalMatchClass)) { 7766 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "ignoring optional operand\n"); 7767 continue; 7768 } 7769 // If this operand is broken for all of the instances of this 7770 // mnemonic, keep track of it so we can report loc info. 7771 // If we already had a match that only failed due to a 7772 // target predicate, that diagnostic is preferred. 7773 if (!HadMatchOtherThanPredicate && 7774 (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) { 7775 if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag != Match_InvalidOperand)) 7776 RetCode = Diag; 7777 ErrorInfo = ActualIdx; 7778 } 7779 // Otherwise, just reject this instance of the mnemonic. 7780 OperandsValid = false; 7781 break; 7782 } 7783 7784 if (!OperandsValid) { 7785 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Opcode result: multiple " 7786 "operand mismatches, ignoring " 7787 "this opcode\n"); 7788 continue; 7789 } 7790 if (!HasRequiredFeatures) { 7791 HadMatchOtherThanFeatures = true; 7792 uint64_t NewMissingFeatures = it->RequiredFeatures & ~AvailableFeatures; 7793 DEBUG_WITH_TYPE("asm-matcher", dbgs() << "Missing target features: " 7794 << format_hex(NewMissingFeatures, 18) 7795 << "\n"); 7796 if (countPopulation(NewMissingFeatures) <= 7797 countPopulation(MissingFeatures)) 7798 MissingFeatures = NewMissingFeatures; 7799 continue; 7800 } 7801 7802 Inst.clear(); 7803 7804 Inst.setOpcode(it->Opcode); 7805 // We have a potential match but have not rendered the operands. 7806 // Check the target predicate to handle any context sensitive 7807 // constraints. 7808 // For example, Ties that are referenced multiple times must be 7809 // checked here to ensure the input is the same for each match 7810 // constraints. If we leave it any later the ties will have been 7811 // canonicalized 7812 unsigned MatchResult; 7813 if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, Operands)) != Match_Success) { 7814 Inst.clear(); 7815 DEBUG_WITH_TYPE( 7816 "asm-matcher", 7817 dbgs() << "Early target match predicate failed with diag code " 7818 << MatchResult << "\n"); 7819 RetCode = MatchResult; 7820 HadMatchOtherThanPredicate = true; 7821 continue; 7822 } 7823 7824 if (matchingInlineAsm) { 7825 convertToMapAndConstraints(it->ConvertFn, Operands); 7826 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 7827 return Match_InvalidTiedOperand; 7828 7829 return Match_Success; 7830 } 7831 7832 // We have selected a definite instruction, convert the parsed 7833 // operands into the appropriate MCInst. 7834 convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands); 7835 7836 // We have a potential match. Check the target predicate to 7837 // handle any context sensitive constraints. 7838 if ((MatchResult = checkTargetMatchPredicate(Inst)) != Match_Success) { 7839 DEBUG_WITH_TYPE("asm-matcher", 7840 dbgs() << "Target match predicate failed with diag code " 7841 << MatchResult << "\n"); 7842 Inst.clear(); 7843 RetCode = MatchResult; 7844 HadMatchOtherThanPredicate = true; 7845 continue; 7846 } 7847 7848 if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, Operands, ErrorInfo)) 7849 return Match_InvalidTiedOperand; 7850 7851 DEBUG_WITH_TYPE( 7852 "asm-matcher", 7853 dbgs() << "Opcode result: complete match, selecting this opcode\n"); 7854 return Match_Success; 7855 } 7856 7857 // Okay, we had no match. Try to return a useful error code. 7858 if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures) 7859 return RetCode; 7860 7861 // Missing feature matches return which features were missing 7862 ErrorInfo = MissingFeatures; 7863 return Match_MissingFeature; 7864} 7865 7866namespace { 7867 struct OperandMatchEntry { 7868 uint64_t RequiredFeatures; 7869 uint16_t Mnemonic; 7870 uint8_t Class; 7871 uint8_t OperandMask; 7872 7873 StringRef getMnemonic() const { 7874 return StringRef(MnemonicTable + Mnemonic + 1, 7875 MnemonicTable[Mnemonic]); 7876 } 7877 }; 7878 7879 // Predicate for searching for an opcode. 7880 struct LessOpcodeOperand { 7881 bool operator()(const OperandMatchEntry &LHS, StringRef RHS) { 7882 return LHS.getMnemonic() < RHS; 7883 } 7884 bool operator()(StringRef LHS, const OperandMatchEntry &RHS) { 7885 return LHS < RHS.getMnemonic(); 7886 } 7887 bool operator()(const OperandMatchEntry &LHS, const OperandMatchEntry &RHS) { 7888 return LHS.getMnemonic() < RHS.getMnemonic(); 7889 } 7890 }; 7891} // end anonymous namespace. 7892 7893static const OperandMatchEntry OperandMatchTable[3237] = { 7894 /* Operand List Mask, Mnemonic, Operand Class, Features */ 7895 { 0, 0 /* abs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7896 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 7897 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 7898 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 7899 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 4 /* abs.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 7900 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 7901 { Feature_InMicroMips|Feature_IsNotSoftFloat, 10 /* abs.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 7902 { Feature_InMicroMips|Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7903 { Feature_HasDSP, 16 /* absq_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7904 { Feature_InMicroMips|Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7905 { Feature_HasDSPR2, 26 /* absq_s.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7906 { Feature_InMicroMips|Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7907 { Feature_HasDSP, 36 /* absq_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7908 { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7909 { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7910 { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7911 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7912 { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7913 { Feature_HasStdEnc|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7914 { Feature_InMicroMips|Feature_NotMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7915 { Feature_InMicroMips|Feature_HasMips32r6, 45 /* add */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7916 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7917 { Feature_InMicroMips, 45 /* add */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7918 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 7919 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 7920 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 7921 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 49 /* add.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 7922 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 7923 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 7924 { Feature_InMicroMips|Feature_IsNotSoftFloat, 55 /* add.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 7925 { Feature_HasStdEnc|Feature_HasMSA, 61 /* add_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7926 { Feature_HasStdEnc|Feature_HasMSA, 69 /* add_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7927 { Feature_HasStdEnc|Feature_HasMSA, 77 /* add_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7928 { Feature_HasStdEnc|Feature_HasMSA, 85 /* add_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7929 { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7930 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7931 { Feature_InMicroMips|Feature_NotMips32r6, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7932 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 93 /* addi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7933 { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7934 { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7935 { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7936 { Feature_InMicroMips|Feature_HasMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7937 { Feature_InMicroMips|Feature_NotMips32r6, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7938 { Feature_HasStdEnc|Feature_NotInMicroMips, 98 /* addiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7939 { Feature_HasStdEnc|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7940 { Feature_InMicroMips|Feature_HasMips32r6, 104 /* addiupc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7941 { Feature_InMicroMips|Feature_NotMips32r6, 104 /* addiupc */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 7942 { Feature_InMicroMips, 112 /* addiur1sp */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 7943 { Feature_InMicroMips, 122 /* addiur2 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 7944 { Feature_InMicroMips, 130 /* addius5 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7945 { Feature_InMicroMips|Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7946 { Feature_HasDSP, 146 /* addq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7947 { Feature_InMicroMips|Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7948 { Feature_HasDSP, 154 /* addq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7949 { Feature_InMicroMips|Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7950 { Feature_HasDSP, 164 /* addq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7951 { Feature_InMicroMips|Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7952 { Feature_HasDSPR2, 173 /* addqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7953 { Feature_InMicroMips|Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7954 { Feature_HasDSPR2, 182 /* addqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7955 { Feature_InMicroMips|Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7956 { Feature_HasDSPR2, 190 /* addqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7957 { Feature_InMicroMips|Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7958 { Feature_HasDSPR2, 201 /* addqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7959 { Feature_HasStdEnc|Feature_HasMSA, 211 /* adds_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7960 { Feature_HasStdEnc|Feature_HasMSA, 220 /* adds_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7961 { Feature_HasStdEnc|Feature_HasMSA, 229 /* adds_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7962 { Feature_HasStdEnc|Feature_HasMSA, 238 /* adds_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7963 { Feature_HasStdEnc|Feature_HasMSA, 247 /* adds_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7964 { Feature_HasStdEnc|Feature_HasMSA, 256 /* adds_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7965 { Feature_HasStdEnc|Feature_HasMSA, 265 /* adds_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7966 { Feature_HasStdEnc|Feature_HasMSA, 274 /* adds_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7967 { Feature_HasStdEnc|Feature_HasMSA, 283 /* adds_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7968 { Feature_HasStdEnc|Feature_HasMSA, 292 /* adds_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7969 { Feature_HasStdEnc|Feature_HasMSA, 301 /* adds_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7970 { Feature_HasStdEnc|Feature_HasMSA, 310 /* adds_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7971 { Feature_InMicroMips|Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7972 { Feature_HasDSP, 319 /* addsc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7973 { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7974 { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7975 { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7976 { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7977 { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 7978 { Feature_InMicroMips|Feature_HasMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7979 { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7980 { Feature_InMicroMips|Feature_NotMips32r6, 325 /* addu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7981 { Feature_HasStdEnc|Feature_NotInMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7982 { Feature_InMicroMips, 325 /* addu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 7983 { Feature_InMicroMips|Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7984 { Feature_HasDSPR2, 330 /* addu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7985 { Feature_InMicroMips|Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7986 { Feature_HasDSP, 338 /* addu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7987 { Feature_InMicroMips|Feature_NotMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ }, 7988 { Feature_InMicroMips|Feature_HasMips32r6, 346 /* addu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ }, 7989 { Feature_InMicroMips|Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7990 { Feature_HasDSPR2, 353 /* addu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7991 { Feature_InMicroMips|Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7992 { Feature_HasDSP, 363 /* addu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7993 { Feature_InMicroMips|Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7994 { Feature_HasDSPR2, 373 /* adduh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7995 { Feature_InMicroMips|Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7996 { Feature_HasDSPR2, 382 /* adduh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 7997 { Feature_HasStdEnc|Feature_HasMSA, 393 /* addv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7998 { Feature_HasStdEnc|Feature_HasMSA, 400 /* addv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 7999 { Feature_HasStdEnc|Feature_HasMSA, 407 /* addv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8000 { Feature_HasStdEnc|Feature_HasMSA, 414 /* addv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8001 { Feature_HasStdEnc|Feature_HasMSA, 421 /* addvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8002 { Feature_HasStdEnc|Feature_HasMSA, 429 /* addvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8003 { Feature_HasStdEnc|Feature_HasMSA, 437 /* addvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8004 { Feature_HasStdEnc|Feature_HasMSA, 445 /* addvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8005 { Feature_InMicroMips|Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8006 { Feature_HasDSP, 453 /* addwc */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8007 { Feature_HasStdEnc|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8008 { Feature_InMicroMips|Feature_HasMips32r6, 459 /* align */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8009 { Feature_HasStdEnc|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8010 { Feature_InMicroMips|Feature_HasMips32r6, 465 /* aluipc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8011 { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8012 { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8013 { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8014 { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8015 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8016 { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8017 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8018 { Feature_HasStdEnc|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8019 { Feature_InMicroMips|Feature_NotMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8020 { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8021 { Feature_InMicroMips|Feature_HasMips32r6, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8022 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8023 { Feature_InMicroMips, 472 /* and */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8024 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 472 /* and */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8025 { Feature_HasStdEnc|Feature_HasMSA, 476 /* and.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8026 { Feature_InMicroMips|Feature_NotMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 8027 { Feature_InMicroMips|Feature_HasMips32r6, 482 /* and16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 8028 { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8029 { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8030 { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8031 { Feature_InMicroMips|Feature_HasMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8032 { Feature_HasStdEnc|Feature_NotInMicroMips, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8033 { Feature_InMicroMips|Feature_NotMips32r6, 488 /* andi */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8034 { Feature_HasStdEnc|Feature_HasMSA, 493 /* andi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8035 { Feature_InMicroMips|Feature_NotMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 8036 { Feature_InMicroMips|Feature_HasMips32r6, 500 /* andi16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 8037 { Feature_InMicroMips|Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8038 { Feature_HasDSPR2, 507 /* append */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8039 { Feature_HasStdEnc|Feature_HasMSA, 514 /* asub_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8040 { Feature_HasStdEnc|Feature_HasMSA, 523 /* asub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8041 { Feature_HasStdEnc|Feature_HasMSA, 532 /* asub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8042 { Feature_HasStdEnc|Feature_HasMSA, 541 /* asub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8043 { Feature_HasStdEnc|Feature_HasMSA, 550 /* asub_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8044 { Feature_HasStdEnc|Feature_HasMSA, 559 /* asub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8045 { Feature_HasStdEnc|Feature_HasMSA, 568 /* asub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8046 { Feature_HasStdEnc|Feature_HasMSA, 577 /* asub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8047 { Feature_HasStdEnc|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8048 { Feature_InMicroMips|Feature_HasMips32r6, 586 /* aui */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8049 { Feature_HasStdEnc|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8050 { Feature_InMicroMips|Feature_HasMips32r6, 590 /* auipc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8051 { Feature_HasStdEnc|Feature_HasMSA, 596 /* ave_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8052 { Feature_HasStdEnc|Feature_HasMSA, 604 /* ave_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8053 { Feature_HasStdEnc|Feature_HasMSA, 612 /* ave_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8054 { Feature_HasStdEnc|Feature_HasMSA, 620 /* ave_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8055 { Feature_HasStdEnc|Feature_HasMSA, 628 /* ave_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8056 { Feature_HasStdEnc|Feature_HasMSA, 636 /* ave_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8057 { Feature_HasStdEnc|Feature_HasMSA, 644 /* ave_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8058 { Feature_HasStdEnc|Feature_HasMSA, 652 /* ave_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8059 { Feature_HasStdEnc|Feature_HasMSA, 660 /* aver_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8060 { Feature_HasStdEnc|Feature_HasMSA, 669 /* aver_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8061 { Feature_HasStdEnc|Feature_HasMSA, 678 /* aver_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8062 { Feature_HasStdEnc|Feature_HasMSA, 687 /* aver_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8063 { Feature_HasStdEnc|Feature_HasMSA, 696 /* aver_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8064 { Feature_HasStdEnc|Feature_HasMSA, 705 /* aver_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8065 { Feature_HasStdEnc|Feature_HasMSA, 714 /* aver_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8066 { Feature_HasStdEnc|Feature_HasMSA, 723 /* aver_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8067 { Feature_HasStdEnc|Feature_NotInMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ }, 8068 { Feature_InMicroMips, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ }, 8069 { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ }, 8070 { 0, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ }, 8071 { Feature_InMips16Mode, 732 /* b */, MCK_JumpTarget, 1 /* 0 */ }, 8072 { Feature_InMicroMips|Feature_HasMips32r6, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ }, 8073 { Feature_InMicroMips, 734 /* b16 */, MCK_JumpTarget, 1 /* 0 */ }, 8074 { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8075 { Feature_HasCnMips, 738 /* baddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 8076 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ }, 8077 { Feature_HasStdEnc|Feature_HasMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ }, 8078 { Feature_InMicroMips|Feature_NotMips32r6, 744 /* bal */, MCK_JumpTarget, 1 /* 0 */ }, 8079 { Feature_HasStdEnc|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ }, 8080 { Feature_InMicroMips|Feature_HasMips32r6, 748 /* balc */, MCK_JumpTarget, 1 /* 0 */ }, 8081 { Feature_InMicroMips|Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8082 { Feature_HasDSPR2, 753 /* balign */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8083 { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8084 { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ }, 8085 { Feature_HasCnMips, 760 /* bbit0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8086 { Feature_HasCnMips, 760 /* bbit0 */, MCK_JumpTarget, 4 /* 2 */ }, 8087 { Feature_HasCnMips, 766 /* bbit032 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8088 { Feature_HasCnMips, 766 /* bbit032 */, MCK_JumpTarget, 4 /* 2 */ }, 8089 { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8090 { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ }, 8091 { Feature_HasCnMips, 774 /* bbit1 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8092 { Feature_HasCnMips, 774 /* bbit1 */, MCK_JumpTarget, 4 /* 2 */ }, 8093 { Feature_HasCnMips, 780 /* bbit132 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8094 { Feature_HasCnMips, 780 /* bbit132 */, MCK_JumpTarget, 4 /* 2 */ }, 8095 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ }, 8096 { Feature_InMicroMips|Feature_HasMips32r6, 788 /* bc */, MCK_JumpTarget, 1 /* 0 */ }, 8097 { Feature_InMicroMips|Feature_HasMips32r6, 791 /* bc16 */, MCK_JumpTarget, 1 /* 0 */ }, 8098 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_FGR64AsmReg, 1 /* 0 */ }, 8099 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 796 /* bc1eqz */, MCK_JumpTarget, 2 /* 1 */ }, 8100 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_FGR64AsmReg, 1 /* 0 */ }, 8101 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 803 /* bc1eqzc */, MCK_JumpTarget, 2 /* 1 */ }, 8102 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ }, 8103 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 1 /* 0 */ }, 8104 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ }, 8105 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ }, 8106 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_FCCAsmReg, 1 /* 0 */ }, 8107 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 811 /* bc1f */, MCK_JumpTarget, 2 /* 1 */ }, 8108 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 1 /* 0 */ }, 8109 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_FCCAsmReg, 1 /* 0 */ }, 8110 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 816 /* bc1fl */, MCK_JumpTarget, 2 /* 1 */ }, 8111 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_FGR64AsmReg, 1 /* 0 */ }, 8112 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 822 /* bc1nez */, MCK_JumpTarget, 2 /* 1 */ }, 8113 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_FGR64AsmReg, 1 /* 0 */ }, 8114 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 829 /* bc1nezc */, MCK_JumpTarget, 2 /* 1 */ }, 8115 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ }, 8116 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 1 /* 0 */ }, 8117 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ }, 8118 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ }, 8119 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_FCCAsmReg, 1 /* 0 */ }, 8120 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 837 /* bc1t */, MCK_JumpTarget, 2 /* 1 */ }, 8121 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 1 /* 0 */ }, 8122 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_FCCAsmReg, 1 /* 0 */ }, 8123 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 842 /* bc1tl */, MCK_JumpTarget, 2 /* 1 */ }, 8124 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_COP2AsmReg, 1 /* 0 */ }, 8125 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 848 /* bc2eqz */, MCK_JumpTarget, 2 /* 1 */ }, 8126 { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_COP2AsmReg, 1 /* 0 */ }, 8127 { Feature_InMicroMips|Feature_HasMips32r6, 855 /* bc2eqzc */, MCK_JumpTarget, 2 /* 1 */ }, 8128 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_COP2AsmReg, 1 /* 0 */ }, 8129 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 863 /* bc2nez */, MCK_JumpTarget, 2 /* 1 */ }, 8130 { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_COP2AsmReg, 1 /* 0 */ }, 8131 { Feature_InMicroMips|Feature_HasMips32r6, 870 /* bc2nezc */, MCK_JumpTarget, 2 /* 1 */ }, 8132 { Feature_HasStdEnc|Feature_HasMSA, 878 /* bclr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8133 { Feature_HasStdEnc|Feature_HasMSA, 885 /* bclr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8134 { Feature_HasStdEnc|Feature_HasMSA, 892 /* bclr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8135 { Feature_HasStdEnc|Feature_HasMSA, 899 /* bclr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8136 { Feature_HasStdEnc|Feature_HasMSA, 906 /* bclri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8137 { Feature_HasStdEnc|Feature_HasMSA, 914 /* bclri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8138 { Feature_HasStdEnc|Feature_HasMSA, 922 /* bclri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8139 { Feature_HasStdEnc|Feature_HasMSA, 930 /* bclri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8140 { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8141 { Feature_HasStdEnc|Feature_NotInMicroMips, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ }, 8142 { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8143 { Feature_InMicroMips|Feature_NotMips32r6, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ }, 8144 { 0, 938 /* beq */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8145 { 0, 938 /* beq */, MCK_JumpTarget, 4 /* 2 */ }, 8146 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8147 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ }, 8148 { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8149 { Feature_InMicroMips|Feature_HasMips32r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ }, 8150 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8151 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 942 /* beqc */, MCK_JumpTarget, 4 /* 2 */ }, 8152 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8153 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ }, 8154 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8155 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 947 /* beql */, MCK_JumpTarget, 4 /* 2 */ }, 8156 { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ }, 8157 { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8158 { Feature_HasStdEnc|Feature_NotInMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ }, 8159 { Feature_InMicroMips, 952 /* beqz */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8160 { Feature_InMicroMips, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ }, 8161 { Feature_InMips16Mode, 952 /* beqz */, MCK_JumpTarget, 2 /* 1 */ }, 8162 { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 8163 { Feature_InMicroMips|Feature_NotMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ }, 8164 { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 8165 { Feature_InMicroMips|Feature_HasMips32r6, 957 /* beqz16 */, MCK_JumpTarget, 2 /* 1 */ }, 8166 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8167 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ }, 8168 { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8169 { Feature_InMicroMips|Feature_HasMips32r6, 964 /* beqzalc */, MCK_JumpTarget, 2 /* 1 */ }, 8170 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8171 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ }, 8172 { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8173 { Feature_InMicroMips|Feature_NotMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ }, 8174 { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8175 { Feature_InMicroMips|Feature_HasMips32r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ }, 8176 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8177 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 972 /* beqzc */, MCK_JumpTarget, 2 /* 1 */ }, 8178 { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 8179 { Feature_InMicroMips|Feature_HasMips32r6, 978 /* beqzc16 */, MCK_JumpTarget, 2 /* 1 */ }, 8180 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8181 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 986 /* beqzl */, MCK_JumpTarget, 2 /* 1 */ }, 8182 { 0, 992 /* bge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8183 { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ }, 8184 { 0, 992 /* bge */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8185 { 0, 992 /* bge */, MCK_JumpTarget, 4 /* 2 */ }, 8186 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8187 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ }, 8188 { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8189 { Feature_InMicroMips|Feature_HasMips32r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ }, 8190 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8191 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 996 /* bgec */, MCK_JumpTarget, 4 /* 2 */ }, 8192 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8193 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ }, 8194 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8195 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1001 /* bgel */, MCK_JumpTarget, 4 /* 2 */ }, 8196 { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8197 { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ }, 8198 { 0, 1006 /* bgeu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8199 { 0, 1006 /* bgeu */, MCK_JumpTarget, 4 /* 2 */ }, 8200 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8201 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ }, 8202 { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8203 { Feature_InMicroMips|Feature_HasMips32r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ }, 8204 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8205 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1011 /* bgeuc */, MCK_JumpTarget, 4 /* 2 */ }, 8206 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8207 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ }, 8208 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8209 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1017 /* bgeul */, MCK_JumpTarget, 4 /* 2 */ }, 8210 { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8211 { Feature_HasStdEnc|Feature_NotInMicroMips, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ }, 8212 { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8213 { Feature_InMicroMips|Feature_NotMips32r6, 1023 /* bgez */, MCK_JumpTarget, 2 /* 1 */ }, 8214 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8215 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ }, 8216 { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8217 { Feature_InMicroMips|Feature_NotMips32r6, 1028 /* bgezal */, MCK_JumpTarget, 2 /* 1 */ }, 8218 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8219 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ }, 8220 { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8221 { Feature_InMicroMips|Feature_HasMips32r6, 1035 /* bgezalc */, MCK_JumpTarget, 2 /* 1 */ }, 8222 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8223 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1043 /* bgezall */, MCK_JumpTarget, 2 /* 1 */ }, 8224 { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8225 { Feature_InMicroMips|Feature_NotMips32r6, 1051 /* bgezals */, MCK_JumpTarget, 2 /* 1 */ }, 8226 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8227 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ }, 8228 { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8229 { Feature_InMicroMips|Feature_HasMips32r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ }, 8230 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8231 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1059 /* bgezc */, MCK_JumpTarget, 2 /* 1 */ }, 8232 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8233 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1065 /* bgezl */, MCK_JumpTarget, 2 /* 1 */ }, 8234 { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8235 { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ }, 8236 { 0, 1071 /* bgt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8237 { 0, 1071 /* bgt */, MCK_JumpTarget, 4 /* 2 */ }, 8238 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8239 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ }, 8240 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8241 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1075 /* bgtl */, MCK_JumpTarget, 4 /* 2 */ }, 8242 { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8243 { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ }, 8244 { 0, 1080 /* bgtu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8245 { 0, 1080 /* bgtu */, MCK_JumpTarget, 4 /* 2 */ }, 8246 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8247 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ }, 8248 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8249 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1085 /* bgtul */, MCK_JumpTarget, 4 /* 2 */ }, 8250 { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8251 { Feature_HasStdEnc|Feature_NotInMicroMips, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ }, 8252 { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8253 { Feature_InMicroMips|Feature_NotMips32r6, 1091 /* bgtz */, MCK_JumpTarget, 2 /* 1 */ }, 8254 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8255 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ }, 8256 { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8257 { Feature_InMicroMips|Feature_HasMips32r6, 1096 /* bgtzalc */, MCK_JumpTarget, 2 /* 1 */ }, 8258 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8259 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ }, 8260 { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8261 { Feature_InMicroMips|Feature_HasMips32r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ }, 8262 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8263 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1104 /* bgtzc */, MCK_JumpTarget, 2 /* 1 */ }, 8264 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8265 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1110 /* bgtzl */, MCK_JumpTarget, 2 /* 1 */ }, 8266 { Feature_HasStdEnc|Feature_HasMSA, 1116 /* binsl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8267 { Feature_HasStdEnc|Feature_HasMSA, 1124 /* binsl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8268 { Feature_HasStdEnc|Feature_HasMSA, 1132 /* binsl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8269 { Feature_HasStdEnc|Feature_HasMSA, 1140 /* binsl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8270 { Feature_HasStdEnc|Feature_HasMSA, 1148 /* binsli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8271 { Feature_HasStdEnc|Feature_HasMSA, 1157 /* binsli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8272 { Feature_HasStdEnc|Feature_HasMSA, 1166 /* binsli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8273 { Feature_HasStdEnc|Feature_HasMSA, 1175 /* binsli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8274 { Feature_HasStdEnc|Feature_HasMSA, 1184 /* binsr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8275 { Feature_HasStdEnc|Feature_HasMSA, 1192 /* binsr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8276 { Feature_HasStdEnc|Feature_HasMSA, 1200 /* binsr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8277 { Feature_HasStdEnc|Feature_HasMSA, 1208 /* binsr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8278 { Feature_HasStdEnc|Feature_HasMSA, 1216 /* binsri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8279 { Feature_HasStdEnc|Feature_HasMSA, 1225 /* binsri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8280 { Feature_HasStdEnc|Feature_HasMSA, 1234 /* binsri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8281 { Feature_HasStdEnc|Feature_HasMSA, 1243 /* binsri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8282 { Feature_InMicroMips|Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8283 { Feature_HasDSP, 1252 /* bitrev */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8284 { Feature_HasStdEnc|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8285 { Feature_InMicroMips|Feature_HasMips32r6, 1259 /* bitswap */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8286 { 0, 1267 /* ble */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8287 { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ }, 8288 { 0, 1267 /* ble */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8289 { 0, 1267 /* ble */, MCK_JumpTarget, 4 /* 2 */ }, 8290 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8291 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ }, 8292 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8293 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1271 /* blel */, MCK_JumpTarget, 4 /* 2 */ }, 8294 { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8295 { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ }, 8296 { 0, 1276 /* bleu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8297 { 0, 1276 /* bleu */, MCK_JumpTarget, 4 /* 2 */ }, 8298 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8299 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ }, 8300 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8301 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1281 /* bleul */, MCK_JumpTarget, 4 /* 2 */ }, 8302 { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8303 { Feature_HasStdEnc|Feature_NotInMicroMips, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ }, 8304 { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8305 { Feature_InMicroMips|Feature_NotMips32r6, 1287 /* blez */, MCK_JumpTarget, 2 /* 1 */ }, 8306 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8307 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ }, 8308 { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8309 { Feature_InMicroMips|Feature_HasMips32r6, 1292 /* blezalc */, MCK_JumpTarget, 2 /* 1 */ }, 8310 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8311 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ }, 8312 { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8313 { Feature_InMicroMips|Feature_HasMips32r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ }, 8314 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8315 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1300 /* blezc */, MCK_JumpTarget, 2 /* 1 */ }, 8316 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8317 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1306 /* blezl */, MCK_JumpTarget, 2 /* 1 */ }, 8318 { 0, 1312 /* blt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8319 { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ }, 8320 { 0, 1312 /* blt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8321 { 0, 1312 /* blt */, MCK_JumpTarget, 4 /* 2 */ }, 8322 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8323 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ }, 8324 { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8325 { Feature_InMicroMips|Feature_HasMips32r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ }, 8326 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8327 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1316 /* bltc */, MCK_JumpTarget, 4 /* 2 */ }, 8328 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8329 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ }, 8330 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8331 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1321 /* bltl */, MCK_JumpTarget, 4 /* 2 */ }, 8332 { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8333 { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ }, 8334 { 0, 1326 /* bltu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8335 { 0, 1326 /* bltu */, MCK_JumpTarget, 4 /* 2 */ }, 8336 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8337 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ }, 8338 { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8339 { Feature_InMicroMips|Feature_HasMips32r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ }, 8340 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8341 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1331 /* bltuc */, MCK_JumpTarget, 4 /* 2 */ }, 8342 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8343 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ }, 8344 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8345 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1337 /* bltul */, MCK_JumpTarget, 4 /* 2 */ }, 8346 { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8347 { Feature_HasStdEnc|Feature_NotInMicroMips, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ }, 8348 { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8349 { Feature_InMicroMips|Feature_NotMips32r6, 1343 /* bltz */, MCK_JumpTarget, 2 /* 1 */ }, 8350 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8351 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ }, 8352 { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8353 { Feature_InMicroMips|Feature_NotMips32r6, 1348 /* bltzal */, MCK_JumpTarget, 2 /* 1 */ }, 8354 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8355 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ }, 8356 { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8357 { Feature_InMicroMips|Feature_HasMips32r6, 1355 /* bltzalc */, MCK_JumpTarget, 2 /* 1 */ }, 8358 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8359 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1363 /* bltzall */, MCK_JumpTarget, 2 /* 1 */ }, 8360 { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8361 { Feature_InMicroMips|Feature_NotMips32r6, 1371 /* bltzals */, MCK_JumpTarget, 2 /* 1 */ }, 8362 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8363 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ }, 8364 { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8365 { Feature_InMicroMips|Feature_HasMips32r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ }, 8366 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8367 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1379 /* bltzc */, MCK_JumpTarget, 2 /* 1 */ }, 8368 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8369 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1385 /* bltzl */, MCK_JumpTarget, 2 /* 1 */ }, 8370 { Feature_HasStdEnc|Feature_HasMSA, 1391 /* bmnz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8371 { Feature_HasStdEnc|Feature_HasMSA, 1398 /* bmnzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8372 { Feature_HasStdEnc|Feature_HasMSA, 1406 /* bmz.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8373 { Feature_HasStdEnc|Feature_HasMSA, 1412 /* bmzi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8374 { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8375 { Feature_HasStdEnc|Feature_NotInMicroMips, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ }, 8376 { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8377 { Feature_InMicroMips|Feature_NotMips32r6, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ }, 8378 { 0, 1419 /* bne */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8379 { 0, 1419 /* bne */, MCK_JumpTarget, 4 /* 2 */ }, 8380 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8381 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ }, 8382 { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8383 { Feature_InMicroMips|Feature_HasMips32r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ }, 8384 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8385 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1423 /* bnec */, MCK_JumpTarget, 4 /* 2 */ }, 8386 { Feature_HasStdEnc|Feature_HasMSA, 1428 /* bneg.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8387 { Feature_HasStdEnc|Feature_HasMSA, 1435 /* bneg.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8388 { Feature_HasStdEnc|Feature_HasMSA, 1442 /* bneg.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8389 { Feature_HasStdEnc|Feature_HasMSA, 1449 /* bneg.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8390 { Feature_HasStdEnc|Feature_HasMSA, 1456 /* bnegi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8391 { Feature_HasStdEnc|Feature_HasMSA, 1464 /* bnegi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8392 { Feature_HasStdEnc|Feature_HasMSA, 1472 /* bnegi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8393 { Feature_HasStdEnc|Feature_HasMSA, 1480 /* bnegi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8394 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8395 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ }, 8396 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8397 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6, 1488 /* bnel */, MCK_JumpTarget, 4 /* 2 */ }, 8398 { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ }, 8399 { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8400 { Feature_HasStdEnc|Feature_NotInMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ }, 8401 { Feature_InMicroMips, 1493 /* bnez */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8402 { Feature_InMicroMips, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ }, 8403 { Feature_InMips16Mode, 1493 /* bnez */, MCK_JumpTarget, 2 /* 1 */ }, 8404 { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 8405 { Feature_InMicroMips|Feature_NotMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ }, 8406 { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 8407 { Feature_InMicroMips|Feature_HasMips32r6, 1498 /* bnez16 */, MCK_JumpTarget, 2 /* 1 */ }, 8408 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8409 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ }, 8410 { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8411 { Feature_InMicroMips|Feature_HasMips32r6, 1505 /* bnezalc */, MCK_JumpTarget, 2 /* 1 */ }, 8412 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8413 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ }, 8414 { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8415 { Feature_InMicroMips|Feature_NotMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ }, 8416 { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8417 { Feature_InMicroMips|Feature_HasMips32r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ }, 8418 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8419 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 1513 /* bnezc */, MCK_JumpTarget, 2 /* 1 */ }, 8420 { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 8421 { Feature_InMicroMips|Feature_HasMips32r6, 1519 /* bnezc16 */, MCK_JumpTarget, 2 /* 1 */ }, 8422 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8423 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 1527 /* bnezl */, MCK_JumpTarget, 2 /* 1 */ }, 8424 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8425 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ }, 8426 { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8427 { Feature_InMicroMips|Feature_HasMips32r6, 1533 /* bnvc */, MCK_JumpTarget, 4 /* 2 */ }, 8428 { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8429 { Feature_HasStdEnc|Feature_HasMSA, 1538 /* bnz.b */, MCK_JumpTarget, 2 /* 1 */ }, 8430 { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8431 { Feature_HasStdEnc|Feature_HasMSA, 1544 /* bnz.d */, MCK_JumpTarget, 2 /* 1 */ }, 8432 { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8433 { Feature_HasStdEnc|Feature_HasMSA, 1550 /* bnz.h */, MCK_JumpTarget, 2 /* 1 */ }, 8434 { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8435 { Feature_HasStdEnc|Feature_HasMSA, 1556 /* bnz.v */, MCK_JumpTarget, 2 /* 1 */ }, 8436 { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8437 { Feature_HasStdEnc|Feature_HasMSA, 1562 /* bnz.w */, MCK_JumpTarget, 2 /* 1 */ }, 8438 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8439 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ }, 8440 { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8441 { Feature_InMicroMips|Feature_HasMips32r6, 1568 /* bovc */, MCK_JumpTarget, 4 /* 2 */ }, 8442 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasDSP, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ }, 8443 { Feature_HasDSP|Feature_NotInMicroMips, 1573 /* bposge32 */, MCK_JumpTarget, 1 /* 0 */ }, 8444 { Feature_InMicroMips|Feature_HasDSPR3, 1582 /* bposge32c */, MCK_JumpTarget, 1 /* 0 */ }, 8445 { Feature_HasStdEnc|Feature_HasMSA, 1606 /* bsel.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8446 { Feature_HasStdEnc|Feature_HasMSA, 1613 /* bseli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8447 { Feature_HasStdEnc|Feature_HasMSA, 1621 /* bset.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8448 { Feature_HasStdEnc|Feature_HasMSA, 1628 /* bset.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8449 { Feature_HasStdEnc|Feature_HasMSA, 1635 /* bset.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8450 { Feature_HasStdEnc|Feature_HasMSA, 1642 /* bset.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8451 { Feature_HasStdEnc|Feature_HasMSA, 1649 /* bseti.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8452 { Feature_HasStdEnc|Feature_HasMSA, 1657 /* bseti.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8453 { Feature_HasStdEnc|Feature_HasMSA, 1665 /* bseti.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8454 { Feature_HasStdEnc|Feature_HasMSA, 1673 /* bseti.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8455 { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8456 { Feature_HasStdEnc|Feature_HasMSA, 1693 /* bz.b */, MCK_JumpTarget, 2 /* 1 */ }, 8457 { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8458 { Feature_HasStdEnc|Feature_HasMSA, 1698 /* bz.d */, MCK_JumpTarget, 2 /* 1 */ }, 8459 { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8460 { Feature_HasStdEnc|Feature_HasMSA, 1703 /* bz.h */, MCK_JumpTarget, 2 /* 1 */ }, 8461 { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8462 { Feature_HasStdEnc|Feature_HasMSA, 1708 /* bz.v */, MCK_JumpTarget, 2 /* 1 */ }, 8463 { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 8464 { Feature_HasStdEnc|Feature_HasMSA, 1713 /* bz.w */, MCK_JumpTarget, 2 /* 1 */ }, 8465 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8466 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8467 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8468 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8469 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8470 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8471 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8472 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8473 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8474 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8475 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8476 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1718 /* c.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8477 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8478 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8479 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8480 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8481 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8482 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1725 /* c.eq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8483 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8484 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8485 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8486 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8487 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8488 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8489 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8490 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8491 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8492 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8493 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8494 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1732 /* c.f.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8495 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8496 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8497 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8498 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8499 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8500 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1738 /* c.f.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8501 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8502 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8503 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8504 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8505 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8506 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8507 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8508 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8509 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8510 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8511 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8512 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1744 /* c.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8513 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8514 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8515 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8516 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8517 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8518 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1751 /* c.le.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8519 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8520 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8521 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8522 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8523 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8524 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8525 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8526 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8527 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8528 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8529 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8530 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1758 /* c.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8531 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8532 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8533 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8534 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8535 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8536 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1765 /* c.lt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8537 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8538 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8539 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8540 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8541 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8542 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8543 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8544 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8545 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8546 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8547 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8548 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1772 /* c.nge.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8549 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8550 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8551 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8552 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8553 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8554 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1780 /* c.nge.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8555 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8556 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8557 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8558 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8559 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8560 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8561 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8562 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8563 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8564 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8565 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8566 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1788 /* c.ngl.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8567 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8568 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8569 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8570 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8571 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8572 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1796 /* c.ngl.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8573 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8574 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8575 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8576 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8577 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8578 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8579 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8580 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8581 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8582 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8583 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8584 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1804 /* c.ngle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8585 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8586 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8587 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8588 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8589 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8590 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1813 /* c.ngle.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8591 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8592 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8593 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8594 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8595 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8596 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8597 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8598 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8599 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8600 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8601 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8602 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1822 /* c.ngt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8603 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8604 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8605 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8606 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8607 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8608 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1830 /* c.ngt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8609 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8610 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8611 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8612 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8613 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8614 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8615 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8616 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8617 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8618 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8619 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8620 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1838 /* c.ole.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8621 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8622 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8623 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8624 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8625 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8626 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1846 /* c.ole.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8627 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8628 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8629 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8630 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8631 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8632 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8633 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8634 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8635 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8636 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8637 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8638 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1854 /* c.olt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8639 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8640 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8641 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8642 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8643 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8644 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1862 /* c.olt.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8645 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8646 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8647 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8648 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8649 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8650 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8651 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8652 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8653 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8654 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8655 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8656 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1870 /* c.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8657 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8658 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8659 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8660 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8661 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8662 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1878 /* c.seq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8663 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8664 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8665 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8666 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8667 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8668 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8669 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8670 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8671 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8672 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8673 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8674 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1886 /* c.sf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8675 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8676 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8677 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8678 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8679 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8680 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1893 /* c.sf.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8681 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8682 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8683 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8684 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8685 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8686 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8687 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8688 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8689 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8690 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8691 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8692 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1900 /* c.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8693 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8694 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8695 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8696 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8697 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8698 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1908 /* c.ueq.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8699 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8700 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8701 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8702 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8703 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8704 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8705 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8706 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8707 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8708 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8709 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8710 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1916 /* c.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8711 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8712 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8713 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8714 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8715 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8716 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1924 /* c.ule.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8717 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8718 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8719 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8720 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8721 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8722 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8723 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8724 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8725 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8726 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8727 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8728 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1932 /* c.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8729 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8730 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8731 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8732 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8733 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8734 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1940 /* c.ult.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8735 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8736 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 8737 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8738 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8739 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8740 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8741 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_AFGR64AsmReg, 6 /* 1, 2 */ }, 8742 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8743 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8744 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8745 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FCCAsmReg, 1 /* 0 */ }, 8746 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1948 /* c.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8747 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8748 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8749 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8750 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8751 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FCCAsmReg, 1 /* 0 */ }, 8752 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 1955 /* c.un.s */, MCK_FGR32AsmReg, 6 /* 1, 2 */ }, 8753 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 8754 { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 1962 /* cache */, MCK_Mem, 2 /* 1 */ }, 8755 { Feature_InMicroMips|Feature_NotMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ }, 8756 { Feature_InMicroMips|Feature_HasMips32r6, 1962 /* cache */, MCK_Mem, 2 /* 1 */ }, 8757 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 8758 { Feature_InMicroMips|Feature_HasEVA, 1968 /* cachee */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 8759 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8760 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1975 /* ceil.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8761 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 8762 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 8763 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 8764 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1984 /* ceil.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 8765 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 8766 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8767 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 8768 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8769 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 8770 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8771 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8772 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 1993 /* ceil.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 8773 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8774 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8775 { Feature_InMicroMips|Feature_IsNotSoftFloat, 2002 /* ceil.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8776 { Feature_HasStdEnc|Feature_HasMSA, 2011 /* ceq.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8777 { Feature_HasStdEnc|Feature_HasMSA, 2017 /* ceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8778 { Feature_HasStdEnc|Feature_HasMSA, 2023 /* ceq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8779 { Feature_HasStdEnc|Feature_HasMSA, 2029 /* ceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8780 { Feature_HasStdEnc|Feature_HasMSA, 2035 /* ceqi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8781 { Feature_HasStdEnc|Feature_HasMSA, 2042 /* ceqi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8782 { Feature_HasStdEnc|Feature_HasMSA, 2049 /* ceqi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8783 { Feature_HasStdEnc|Feature_HasMSA, 2056 /* ceqi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8784 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ }, 8785 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8786 { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_CCRAsmReg, 2 /* 1 */ }, 8787 { Feature_InMicroMips|Feature_IsNotSoftFloat, 2063 /* cfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8788 { Feature_InMicroMips, 2068 /* cfc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 8789 { Feature_InMicroMips, 2068 /* cfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8790 { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8791 { Feature_HasStdEnc|Feature_HasMSA, 2073 /* cfcmsa */, MCK_MSACtrlAsmReg, 2 /* 1 */ }, 8792 { Feature_HasMT, 2080 /* cftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 8793 { Feature_HasMT, 2080 /* cftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8794 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8795 { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8796 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8797 { Feature_HasMips64|Feature_HasCnMips, 2086 /* cins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8798 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8799 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 2091 /* cins32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 8800 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8801 { Feature_InMicroMips|Feature_HasMips32r6, 2098 /* class.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8802 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8803 { Feature_InMicroMips|Feature_HasMips32r6, 2106 /* class.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 8804 { Feature_HasStdEnc|Feature_HasMSA, 2114 /* cle_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8805 { Feature_HasStdEnc|Feature_HasMSA, 2122 /* cle_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8806 { Feature_HasStdEnc|Feature_HasMSA, 2130 /* cle_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8807 { Feature_HasStdEnc|Feature_HasMSA, 2138 /* cle_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8808 { Feature_HasStdEnc|Feature_HasMSA, 2146 /* cle_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8809 { Feature_HasStdEnc|Feature_HasMSA, 2154 /* cle_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8810 { Feature_HasStdEnc|Feature_HasMSA, 2162 /* cle_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8811 { Feature_HasStdEnc|Feature_HasMSA, 2170 /* cle_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8812 { Feature_HasStdEnc|Feature_HasMSA, 2178 /* clei_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8813 { Feature_HasStdEnc|Feature_HasMSA, 2187 /* clei_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8814 { Feature_HasStdEnc|Feature_HasMSA, 2196 /* clei_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8815 { Feature_HasStdEnc|Feature_HasMSA, 2205 /* clei_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8816 { Feature_HasStdEnc|Feature_HasMSA, 2214 /* clei_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8817 { Feature_HasStdEnc|Feature_HasMSA, 2223 /* clei_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8818 { Feature_HasStdEnc|Feature_HasMSA, 2232 /* clei_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8819 { Feature_HasStdEnc|Feature_HasMSA, 2241 /* clei_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8820 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8821 { Feature_InMicroMips|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8822 { Feature_HasStdEnc|Feature_HasMips32r6, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8823 { Feature_InMicroMips, 2250 /* clo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8824 { Feature_HasStdEnc|Feature_HasMSA, 2254 /* clt_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8825 { Feature_HasStdEnc|Feature_HasMSA, 2262 /* clt_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8826 { Feature_HasStdEnc|Feature_HasMSA, 2270 /* clt_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8827 { Feature_HasStdEnc|Feature_HasMSA, 2278 /* clt_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8828 { Feature_HasStdEnc|Feature_HasMSA, 2286 /* clt_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8829 { Feature_HasStdEnc|Feature_HasMSA, 2294 /* clt_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8830 { Feature_HasStdEnc|Feature_HasMSA, 2302 /* clt_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8831 { Feature_HasStdEnc|Feature_HasMSA, 2310 /* clt_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 8832 { Feature_HasStdEnc|Feature_HasMSA, 2318 /* clti_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8833 { Feature_HasStdEnc|Feature_HasMSA, 2327 /* clti_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8834 { Feature_HasStdEnc|Feature_HasMSA, 2336 /* clti_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8835 { Feature_HasStdEnc|Feature_HasMSA, 2345 /* clti_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8836 { Feature_HasStdEnc|Feature_HasMSA, 2354 /* clti_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8837 { Feature_HasStdEnc|Feature_HasMSA, 2363 /* clti_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8838 { Feature_HasStdEnc|Feature_HasMSA, 2372 /* clti_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8839 { Feature_HasStdEnc|Feature_HasMSA, 2381 /* clti_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 8840 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8841 { Feature_InMicroMips|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8842 { Feature_HasStdEnc|Feature_HasMips32r6, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8843 { Feature_InMicroMips, 2390 /* clz */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8844 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8845 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8846 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8847 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2398 /* cmp.af.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8848 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8849 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2407 /* cmp.af.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8850 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8851 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8852 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8853 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2416 /* cmp.eq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8854 { Feature_InMicroMips|Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8855 { Feature_HasDSP, 2425 /* cmp.eq.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8856 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8857 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2435 /* cmp.eq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8858 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8859 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8860 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8861 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2444 /* cmp.le.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8862 { Feature_InMicroMips|Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8863 { Feature_HasDSP, 2453 /* cmp.le.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8864 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8865 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2463 /* cmp.le.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8866 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8867 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8868 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8869 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2472 /* cmp.lt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8870 { Feature_InMicroMips|Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8871 { Feature_HasDSP, 2481 /* cmp.lt.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8872 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8873 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2491 /* cmp.lt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8874 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8875 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8876 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8877 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2500 /* cmp.saf.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8878 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8879 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2510 /* cmp.saf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8880 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8881 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8882 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8883 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2520 /* cmp.seq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8884 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8885 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2530 /* cmp.seq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8886 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8887 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8888 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8889 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2540 /* cmp.sle.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8890 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8891 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2550 /* cmp.sle.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8892 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8893 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8894 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8895 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2560 /* cmp.slt.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8896 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8897 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2570 /* cmp.slt.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8898 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8899 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8900 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8901 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2580 /* cmp.sueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8902 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8903 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2591 /* cmp.sueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8904 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8905 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8906 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8907 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2602 /* cmp.sule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8908 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8909 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2613 /* cmp.sule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8910 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8911 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8912 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8913 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2624 /* cmp.sult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8914 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8915 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2635 /* cmp.sult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8916 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8917 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8918 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8919 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2646 /* cmp.sun.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8920 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8921 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2656 /* cmp.sun.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8922 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8923 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8924 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8925 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2666 /* cmp.ueq.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8926 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8927 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2676 /* cmp.ueq.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8928 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8929 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8930 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8931 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2686 /* cmp.ule.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8932 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8933 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2696 /* cmp.ule.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8934 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8935 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8936 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8937 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2706 /* cmp.ult.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8938 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8939 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2716 /* cmp.ult.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8940 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8941 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8942 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 8943 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2726 /* cmp.un.d */, MCK_FGR64AsmReg, 6 /* 1, 2 */ }, 8944 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8945 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 2735 /* cmp.un.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 8946 { Feature_InMicroMips|Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8947 { Feature_HasDSPR2, 2744 /* cmpgdu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8948 { Feature_InMicroMips|Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8949 { Feature_HasDSPR2, 2757 /* cmpgdu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8950 { Feature_InMicroMips|Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8951 { Feature_HasDSPR2, 2770 /* cmpgdu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8952 { Feature_InMicroMips|Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8953 { Feature_HasDSP, 2783 /* cmpgu.eq.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8954 { Feature_InMicroMips|Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8955 { Feature_HasDSP, 2795 /* cmpgu.le.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8956 { Feature_InMicroMips|Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8957 { Feature_HasDSP, 2807 /* cmpgu.lt.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8958 { Feature_InMicroMips|Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8959 { Feature_HasDSP, 2824 /* cmpu.eq.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8960 { Feature_InMicroMips|Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8961 { Feature_HasDSP, 2835 /* cmpu.le.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8962 { Feature_InMicroMips|Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8963 { Feature_HasDSP, 2846 /* cmpu.lt.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 8964 { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8965 { Feature_HasStdEnc|Feature_HasMSA, 2857 /* copy_s.b */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8966 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_GPR64AsmReg, 1 /* 0 */ }, 8967 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2866 /* copy_s.d */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8968 { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8969 { Feature_HasStdEnc|Feature_HasMSA, 2875 /* copy_s.h */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8970 { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8971 { Feature_HasStdEnc|Feature_HasMSA, 2884 /* copy_s.w */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8972 { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8973 { Feature_HasStdEnc|Feature_HasMSA, 2893 /* copy_u.b */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8974 { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8975 { Feature_HasStdEnc|Feature_HasMSA, 2902 /* copy_u.h */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8976 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8977 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 2911 /* copy_u.w */, MCK_MSA128AsmReg, 2 /* 1 */ }, 8978 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2920 /* crc32b */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8979 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2927 /* crc32cb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8980 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2935 /* crc32cd */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8981 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2943 /* crc32ch */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8982 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2951 /* crc32cw */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8983 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_HasCRC|Feature_NotInMicroMips, 2959 /* crc32d */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8984 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2966 /* crc32h */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8985 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasCRC|Feature_NotInMicroMips, 2973 /* crc32w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 8986 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ }, 8987 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8988 { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_CCRAsmReg, 2 /* 1 */ }, 8989 { Feature_InMicroMips|Feature_IsNotSoftFloat, 2980 /* ctc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8990 { Feature_InMicroMips, 2985 /* ctc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 8991 { Feature_InMicroMips, 2985 /* ctc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8992 { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_GPR32AsmReg, 2 /* 1 */ }, 8993 { Feature_HasStdEnc|Feature_HasMSA, 2990 /* ctcmsa */, MCK_MSACtrlAsmReg, 1 /* 0 */ }, 8994 { Feature_HasMT, 2997 /* cttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 8995 { Feature_HasMT, 2997 /* cttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 8996 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8997 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3003 /* cvt.d.l */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 8998 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 8999 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9000 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9001 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9002 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9003 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9004 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9005 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3011 /* cvt.d.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9006 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9007 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9008 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9009 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9010 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9011 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9012 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9013 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3019 /* cvt.d.w */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9014 { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 9015 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 9016 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3027 /* cvt.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 9017 { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9018 { Feature_HasStdEnc|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9019 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9020 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9021 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9022 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3035 /* cvt.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9023 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9024 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9025 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9026 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9027 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9028 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3043 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9029 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9030 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3043 /* cvt.s.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9031 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3051 /* cvt.s.l */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9032 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3051 /* cvt.s.l */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9033 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3051 /* cvt.s.l */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9034 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3051 /* cvt.s.l */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9035 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9036 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9037 { Feature_InMicroMips|Feature_IsNotSoftFloat, 3059 /* cvt.s.w */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9038 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9039 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9040 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9041 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9042 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9043 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3067 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9044 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9045 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3067 /* cvt.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9046 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9047 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9048 { Feature_InMicroMips|Feature_IsNotSoftFloat, 3075 /* cvt.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9049 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9050 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9051 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9052 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3083 /* dadd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9053 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3088 /* daddi */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9054 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3088 /* daddi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9055 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3094 /* daddiu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9056 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3094 /* daddiu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9057 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9058 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9059 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9060 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3101 /* daddu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9061 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3107 /* dahi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9062 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3112 /* dalign */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9063 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3119 /* dati */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9064 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3124 /* daui */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9065 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3129 /* dbitswap */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9066 { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3138 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9067 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3138 /* dclo */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9068 { Feature_HasStdEnc|Feature_HasMips64|Feature_NotMips64r6|Feature_NotInMicroMips, 3143 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9069 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3143 /* dclz */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9070 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9071 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9072 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 6 /* 1, 2 */ }, 9073 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9074 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9075 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3148 /* ddiv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9076 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9077 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9078 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 6 /* 1, 2 */ }, 9079 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9080 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9081 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3153 /* ddivu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9082 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9083 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9084 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3165 /* dext */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9085 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3170 /* dextm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9086 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3176 /* dextu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9087 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9088 { Feature_InMicroMips|Feature_HasMips32r6, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9089 { Feature_InMicroMips, 3182 /* di */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9090 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9091 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9092 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3185 /* dins */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9093 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3190 /* dinsm */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9094 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3196 /* dinsu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9095 { Feature_HasStdEnc|Feature_HasMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9096 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9097 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9098 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ }, 9099 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9100 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ }, 9101 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9102 { Feature_InMicroMips|Feature_NotMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9103 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3202 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9104 { Feature_InMicroMips|Feature_HasMips32r6, 3202 /* div */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9105 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9106 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9107 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3202 /* div */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ }, 9108 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3206 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 9109 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 3206 /* div.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 9110 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3206 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9111 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 3206 /* div.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9112 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9113 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9114 { Feature_InMicroMips|Feature_IsNotSoftFloat, 3212 /* div.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9115 { Feature_HasStdEnc|Feature_HasMSA, 3218 /* div_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9116 { Feature_HasStdEnc|Feature_HasMSA, 3226 /* div_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9117 { Feature_HasStdEnc|Feature_HasMSA, 3234 /* div_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9118 { Feature_HasStdEnc|Feature_HasMSA, 3242 /* div_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9119 { Feature_HasStdEnc|Feature_HasMSA, 3250 /* div_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9120 { Feature_HasStdEnc|Feature_HasMSA, 3258 /* div_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9121 { Feature_HasStdEnc|Feature_HasMSA, 3266 /* div_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9122 { Feature_HasStdEnc|Feature_HasMSA, 3274 /* div_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9123 { Feature_HasStdEnc|Feature_HasMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9124 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9125 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9126 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32NonZeroAsmReg, 1 /* 0 */ }, 9127 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9128 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32ZeroAsmReg, 1 /* 0 */ }, 9129 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3282 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9130 { Feature_InMicroMips|Feature_NotMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9131 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9132 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9133 { Feature_InMicroMips|Feature_HasMips32r6, 3282 /* divu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9134 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 3282 /* divu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9135 { 0, 3287 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9136 { 0, 3287 /* dla */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9137 { 0, 3287 /* dla */, MCK_Mem, 2 /* 1 */ }, 9138 { 0, 3291 /* dli */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9139 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9140 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3295 /* dlsa */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9141 { Feature_NotInMicroMips, 3300 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9142 { Feature_NotInMicroMips, 3300 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9143 { Feature_HasMips64, 3300 /* dmfc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9144 { Feature_HasMips64, 3300 /* dmfc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9145 { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3306 /* dmfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9146 { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3306 /* dmfc1 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9147 { 0, 3312 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9148 { 0, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9149 { Feature_HasCnMips, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9150 { Feature_HasMips64, 3312 /* dmfc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9151 { Feature_HasMips64, 3312 /* dmfc2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9152 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3318 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9153 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3318 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9154 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3318 /* dmfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9155 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3318 /* dmfgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9156 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3325 /* dmod */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9157 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3330 /* dmodu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9158 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3336 /* dmt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9159 { Feature_NotInMicroMips, 3340 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9160 { Feature_NotInMicroMips, 3340 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9161 { Feature_HasMips64, 3340 /* dmtc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9162 { Feature_HasMips64, 3340 /* dmtc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9163 { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3346 /* dmtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9164 { Feature_HasStdEnc|Feature_HasMips3|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 3346 /* dmtc1 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9165 { 0, 3352 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9166 { 0, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9167 { Feature_HasCnMips, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9168 { Feature_HasMips64, 3352 /* dmtc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9169 { Feature_HasMips64, 3352 /* dmtc2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9170 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3358 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9171 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt|Feature_NotInMicroMips, 3358 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9172 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3358 /* dmtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9173 { Feature_HasStdEnc|Feature_HasMips64r5|Feature_HasVirt, 3358 /* dmtgc0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9174 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3365 /* dmuh */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9175 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3370 /* dmuhu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9176 { Feature_HasCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9177 { Feature_HasMips3|Feature_NotMips64r6|Feature_NotCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9178 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9179 { Feature_HasCnMips, 3376 /* dmul */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9180 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3376 /* dmul */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9181 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3381 /* dmulo */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9182 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3387 /* dmulou */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9183 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3394 /* dmult */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9184 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3400 /* dmultu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9185 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 3407 /* dmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9186 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3413 /* dneg */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9187 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3413 /* dneg */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9188 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3418 /* dnegu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9189 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3418 /* dnegu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9190 { Feature_HasStdEnc|Feature_HasMSA, 3424 /* dotp_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9191 { Feature_HasStdEnc|Feature_HasMSA, 3433 /* dotp_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9192 { Feature_HasStdEnc|Feature_HasMSA, 3442 /* dotp_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9193 { Feature_HasStdEnc|Feature_HasMSA, 3451 /* dotp_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9194 { Feature_HasStdEnc|Feature_HasMSA, 3460 /* dotp_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9195 { Feature_HasStdEnc|Feature_HasMSA, 3469 /* dotp_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9196 { Feature_InMicroMips|Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9197 { Feature_InMicroMips|Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9198 { Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9199 { Feature_HasDSPR2, 3478 /* dpa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9200 { Feature_HasStdEnc|Feature_HasMSA, 3487 /* dpadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9201 { Feature_HasStdEnc|Feature_HasMSA, 3497 /* dpadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9202 { Feature_HasStdEnc|Feature_HasMSA, 3507 /* dpadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9203 { Feature_HasStdEnc|Feature_HasMSA, 3517 /* dpadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9204 { Feature_HasStdEnc|Feature_HasMSA, 3527 /* dpadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9205 { Feature_HasStdEnc|Feature_HasMSA, 3537 /* dpadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9206 { Feature_InMicroMips|Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9207 { Feature_InMicroMips|Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9208 { Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9209 { Feature_HasDSP, 3547 /* dpaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9210 { Feature_InMicroMips|Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9211 { Feature_InMicroMips|Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9212 { Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9213 { Feature_HasDSP, 3559 /* dpaq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9214 { Feature_InMicroMips|Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9215 { Feature_InMicroMips|Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9216 { Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9217 { Feature_HasDSPR2, 3571 /* dpaqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9218 { Feature_InMicroMips|Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9219 { Feature_InMicroMips|Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9220 { Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9221 { Feature_HasDSPR2, 3584 /* dpaqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9222 { Feature_InMicroMips|Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9223 { Feature_InMicroMips|Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9224 { Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9225 { Feature_HasDSP, 3598 /* dpau.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9226 { Feature_InMicroMips|Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9227 { Feature_InMicroMips|Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9228 { Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9229 { Feature_HasDSP, 3609 /* dpau.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9230 { Feature_InMicroMips|Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9231 { Feature_InMicroMips|Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9232 { Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9233 { Feature_HasDSPR2, 3620 /* dpax.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9234 { Feature_HasCnMips, 3630 /* dpop */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9235 { Feature_HasCnMips, 3630 /* dpop */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9236 { Feature_InMicroMips|Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9237 { Feature_InMicroMips|Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9238 { Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9239 { Feature_HasDSPR2, 3635 /* dps.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9240 { Feature_InMicroMips|Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9241 { Feature_InMicroMips|Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9242 { Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9243 { Feature_HasDSP, 3644 /* dpsq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9244 { Feature_InMicroMips|Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9245 { Feature_InMicroMips|Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9246 { Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9247 { Feature_HasDSP, 3656 /* dpsq_sa.l.w */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9248 { Feature_InMicroMips|Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9249 { Feature_InMicroMips|Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9250 { Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9251 { Feature_HasDSPR2, 3668 /* dpsqx_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9252 { Feature_InMicroMips|Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9253 { Feature_InMicroMips|Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9254 { Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9255 { Feature_HasDSPR2, 3681 /* dpsqx_sa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9256 { Feature_InMicroMips|Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9257 { Feature_InMicroMips|Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9258 { Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9259 { Feature_HasDSP, 3695 /* dpsu.h.qbl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9260 { Feature_InMicroMips|Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9261 { Feature_InMicroMips|Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9262 { Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9263 { Feature_HasDSP, 3706 /* dpsu.h.qbr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9264 { Feature_HasStdEnc|Feature_HasMSA, 3717 /* dpsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9265 { Feature_HasStdEnc|Feature_HasMSA, 3727 /* dpsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9266 { Feature_HasStdEnc|Feature_HasMSA, 3737 /* dpsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9267 { Feature_HasStdEnc|Feature_HasMSA, 3747 /* dpsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9268 { Feature_HasStdEnc|Feature_HasMSA, 3757 /* dpsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9269 { Feature_HasStdEnc|Feature_HasMSA, 3767 /* dpsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9270 { Feature_InMicroMips|Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9271 { Feature_InMicroMips|Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9272 { Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9273 { Feature_HasDSPR2, 3777 /* dpsx.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9274 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9275 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9276 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9277 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3787 /* drem */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9278 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9279 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9280 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9281 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 3792 /* dremu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9282 { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9283 { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9284 { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9285 { Feature_HasStdEnc|Feature_HasMips64, 3798 /* drol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9286 { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9287 { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9288 { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9289 { Feature_HasStdEnc|Feature_HasMips64, 3803 /* dror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9290 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3808 /* drotr */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9291 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3808 /* drotr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9292 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3814 /* drotr32 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9293 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3814 /* drotr32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9294 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3822 /* drotrv */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9295 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3822 /* drotrv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9296 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3829 /* dsbh */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9297 { Feature_HasStdEnc|Feature_HasMips64r2|Feature_NotInMicroMips, 3834 /* dshd */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9298 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9299 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9300 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9301 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9302 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9303 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3839 /* dsll */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9304 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3844 /* dsll32 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9305 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3844 /* dsll32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9306 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3851 /* dsllv */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9307 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3851 /* dsllv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9308 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3857 /* dsra */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9309 { Feature_HasStdEnc|Feature_HasMips3, 3857 /* dsra */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9310 { Feature_HasStdEnc|Feature_HasMips3, 3857 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9311 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3857 /* dsra */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9312 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3862 /* dsra32 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9313 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3862 /* dsra32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9314 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3869 /* dsrav */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9315 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3869 /* dsrav */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9316 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9317 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9318 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9319 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9320 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9321 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3875 /* dsrl */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9322 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3880 /* dsrl32 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9323 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3880 /* dsrl32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9324 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3887 /* dsrlv */, MCK_GPR32AsmReg, 4 /* 2 */ }, 9325 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3887 /* dsrlv */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9326 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3893 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9327 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9328 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_InvNum, 2 /* 1 */ }, 9329 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3893 /* dsub */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9330 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9331 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3893 /* dsub */, MCK_InvNum, 4 /* 2 */ }, 9332 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9333 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_InvNum, 2 /* 1 */ }, 9334 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9335 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 3898 /* dsubi */, MCK_InvNum, 4 /* 2 */ }, 9336 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9337 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9338 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_InvNum, 2 /* 1 */ }, 9339 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 9340 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9341 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 3904 /* dsubu */, MCK_InvNum, 4 /* 2 */ }, 9342 { Feature_HasStdEnc|Feature_HasMips32r6, 3910 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9343 { Feature_InMicroMips|Feature_HasMips32r6, 3910 /* dvp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9344 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3914 /* dvpe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9345 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9346 { Feature_InMicroMips|Feature_HasMips32r6, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9347 { Feature_InMicroMips, 3923 /* ei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9348 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3926 /* emt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9349 { Feature_HasStdEnc|Feature_HasMips32r6, 3942 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9350 { Feature_InMicroMips|Feature_HasMips32r6, 3942 /* evp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9351 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 3946 /* evpe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9352 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9353 { Feature_InMicroMips|Feature_NotMips32r6, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9354 { Feature_InMicroMips|Feature_HasMips32r6, 3951 /* ext */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9355 { Feature_InMicroMips|Feature_HasDSP, 3955 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9356 { Feature_InMicroMips|Feature_HasDSP, 3955 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9357 { Feature_HasDSP, 3955 /* extp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9358 { Feature_HasDSP, 3955 /* extp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9359 { Feature_InMicroMips|Feature_HasDSP, 3960 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9360 { Feature_InMicroMips|Feature_HasDSP, 3960 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9361 { Feature_HasDSP, 3960 /* extpdp */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9362 { Feature_HasDSP, 3960 /* extpdp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9363 { Feature_InMicroMips|Feature_HasDSP, 3967 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9364 { Feature_InMicroMips|Feature_HasDSP, 3967 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9365 { Feature_HasDSP, 3967 /* extpdpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9366 { Feature_HasDSP, 3967 /* extpdpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9367 { Feature_InMicroMips|Feature_HasDSP, 3975 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9368 { Feature_InMicroMips|Feature_HasDSP, 3975 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9369 { Feature_HasDSP, 3975 /* extpv */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9370 { Feature_HasDSP, 3975 /* extpv */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9371 { Feature_InMicroMips|Feature_HasDSP, 3981 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9372 { Feature_InMicroMips|Feature_HasDSP, 3981 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9373 { Feature_HasDSP, 3981 /* extr.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9374 { Feature_HasDSP, 3981 /* extr.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9375 { Feature_InMicroMips|Feature_HasDSP, 3988 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9376 { Feature_InMicroMips|Feature_HasDSP, 3988 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9377 { Feature_HasDSP, 3988 /* extr_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9378 { Feature_HasDSP, 3988 /* extr_r.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9379 { Feature_InMicroMips|Feature_HasDSP, 3997 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9380 { Feature_InMicroMips|Feature_HasDSP, 3997 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9381 { Feature_HasDSP, 3997 /* extr_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9382 { Feature_HasDSP, 3997 /* extr_rs.w */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9383 { Feature_InMicroMips|Feature_HasDSP, 4007 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9384 { Feature_InMicroMips|Feature_HasDSP, 4007 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9385 { Feature_HasDSP, 4007 /* extr_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9386 { Feature_HasDSP, 4007 /* extr_s.h */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9387 { Feature_InMicroMips|Feature_HasDSP, 4016 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9388 { Feature_InMicroMips|Feature_HasDSP, 4016 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9389 { Feature_HasDSP, 4016 /* extrv.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9390 { Feature_HasDSP, 4016 /* extrv.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9391 { Feature_InMicroMips|Feature_HasDSP, 4024 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9392 { Feature_InMicroMips|Feature_HasDSP, 4024 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9393 { Feature_HasDSP, 4024 /* extrv_r.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9394 { Feature_HasDSP, 4024 /* extrv_r.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9395 { Feature_InMicroMips|Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9396 { Feature_InMicroMips|Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9397 { Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9398 { Feature_HasDSP, 4034 /* extrv_rs.w */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9399 { Feature_InMicroMips|Feature_HasDSP, 4045 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9400 { Feature_InMicroMips|Feature_HasDSP, 4045 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9401 { Feature_HasDSP, 4045 /* extrv_s.h */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9402 { Feature_HasDSP, 4045 /* extrv_s.h */, MCK_GPR32AsmReg, 5 /* 0, 2 */ }, 9403 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4055 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9404 { Feature_HasMips64|Feature_HasCnMips, 4055 /* exts */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9405 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4055 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9406 { Feature_HasMips64|Feature_HasCnMips, 4055 /* exts */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9407 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4060 /* exts32 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9408 { Feature_HasMips64|Feature_HasCnMips|Feature_NotInMicroMips, 4060 /* exts32 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9409 { Feature_HasStdEnc|Feature_HasMSA, 4067 /* fadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9410 { Feature_HasStdEnc|Feature_HasMSA, 4074 /* fadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9411 { Feature_HasStdEnc|Feature_HasMSA, 4081 /* fcaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9412 { Feature_HasStdEnc|Feature_HasMSA, 4088 /* fcaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9413 { Feature_HasStdEnc|Feature_HasMSA, 4095 /* fceq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9414 { Feature_HasStdEnc|Feature_HasMSA, 4102 /* fceq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9415 { Feature_HasStdEnc|Feature_HasMSA, 4109 /* fclass.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9416 { Feature_HasStdEnc|Feature_HasMSA, 4118 /* fclass.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9417 { Feature_HasStdEnc|Feature_HasMSA, 4127 /* fcle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9418 { Feature_HasStdEnc|Feature_HasMSA, 4134 /* fcle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9419 { Feature_HasStdEnc|Feature_HasMSA, 4141 /* fclt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9420 { Feature_HasStdEnc|Feature_HasMSA, 4148 /* fclt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9421 { Feature_HasStdEnc|Feature_HasMSA, 4155 /* fcne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9422 { Feature_HasStdEnc|Feature_HasMSA, 4162 /* fcne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9423 { Feature_HasStdEnc|Feature_HasMSA, 4169 /* fcor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9424 { Feature_HasStdEnc|Feature_HasMSA, 4176 /* fcor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9425 { Feature_HasStdEnc|Feature_HasMSA, 4183 /* fcueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9426 { Feature_HasStdEnc|Feature_HasMSA, 4191 /* fcueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9427 { Feature_HasStdEnc|Feature_HasMSA, 4199 /* fcule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9428 { Feature_HasStdEnc|Feature_HasMSA, 4207 /* fcule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9429 { Feature_HasStdEnc|Feature_HasMSA, 4215 /* fcult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9430 { Feature_HasStdEnc|Feature_HasMSA, 4223 /* fcult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9431 { Feature_HasStdEnc|Feature_HasMSA, 4231 /* fcun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9432 { Feature_HasStdEnc|Feature_HasMSA, 4238 /* fcun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9433 { Feature_HasStdEnc|Feature_HasMSA, 4245 /* fcune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9434 { Feature_HasStdEnc|Feature_HasMSA, 4253 /* fcune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9435 { Feature_HasStdEnc|Feature_HasMSA, 4261 /* fdiv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9436 { Feature_HasStdEnc|Feature_HasMSA, 4268 /* fdiv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9437 { Feature_HasStdEnc|Feature_HasMSA, 4275 /* fexdo.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9438 { Feature_HasStdEnc|Feature_HasMSA, 4283 /* fexdo.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9439 { Feature_HasStdEnc|Feature_HasMSA, 4291 /* fexp2.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9440 { Feature_HasStdEnc|Feature_HasMSA, 4299 /* fexp2.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9441 { Feature_HasStdEnc|Feature_HasMSA, 4307 /* fexupl.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9442 { Feature_HasStdEnc|Feature_HasMSA, 4316 /* fexupl.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9443 { Feature_HasStdEnc|Feature_HasMSA, 4325 /* fexupr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9444 { Feature_HasStdEnc|Feature_HasMSA, 4334 /* fexupr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9445 { Feature_HasStdEnc|Feature_HasMSA, 4343 /* ffint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9446 { Feature_HasStdEnc|Feature_HasMSA, 4353 /* ffint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9447 { Feature_HasStdEnc|Feature_HasMSA, 4363 /* ffint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9448 { Feature_HasStdEnc|Feature_HasMSA, 4373 /* ffint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9449 { Feature_HasStdEnc|Feature_HasMSA, 4383 /* ffql.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9450 { Feature_HasStdEnc|Feature_HasMSA, 4390 /* ffql.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9451 { Feature_HasStdEnc|Feature_HasMSA, 4397 /* ffqr.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9452 { Feature_HasStdEnc|Feature_HasMSA, 4404 /* ffqr.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9453 { Feature_HasStdEnc|Feature_HasMSA, 4411 /* fill.b */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9454 { Feature_HasStdEnc|Feature_HasMSA, 4411 /* fill.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9455 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4418 /* fill.d */, MCK_GPR64AsmReg, 2 /* 1 */ }, 9456 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 4418 /* fill.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9457 { Feature_HasStdEnc|Feature_HasMSA, 4425 /* fill.h */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9458 { Feature_HasStdEnc|Feature_HasMSA, 4425 /* fill.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9459 { Feature_HasStdEnc|Feature_HasMSA, 4432 /* fill.w */, MCK_GPR32AsmReg, 2 /* 1 */ }, 9460 { Feature_HasStdEnc|Feature_HasMSA, 4432 /* fill.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9461 { Feature_HasStdEnc|Feature_HasMSA, 4439 /* flog2.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9462 { Feature_HasStdEnc|Feature_HasMSA, 4447 /* flog2.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9463 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4455 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 9464 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4455 /* floor.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 9465 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4465 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9466 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4465 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9467 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4465 /* floor.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9468 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4465 /* floor.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9469 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9470 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9471 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9472 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9473 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9474 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9475 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9476 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4475 /* floor.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9477 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9478 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9479 { Feature_InMicroMips|Feature_IsNotSoftFloat, 4485 /* floor.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 9480 { Feature_HasStdEnc|Feature_HasMSA, 4495 /* fmadd.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9481 { Feature_HasStdEnc|Feature_HasMSA, 4503 /* fmadd.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9482 { Feature_HasStdEnc|Feature_HasMSA, 4511 /* fmax.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9483 { Feature_HasStdEnc|Feature_HasMSA, 4518 /* fmax.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9484 { Feature_HasStdEnc|Feature_HasMSA, 4525 /* fmax_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9485 { Feature_HasStdEnc|Feature_HasMSA, 4534 /* fmax_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9486 { Feature_HasStdEnc|Feature_HasMSA, 4543 /* fmin.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9487 { Feature_HasStdEnc|Feature_HasMSA, 4550 /* fmin.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9488 { Feature_HasStdEnc|Feature_HasMSA, 4557 /* fmin_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9489 { Feature_HasStdEnc|Feature_HasMSA, 4566 /* fmin_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9490 { Feature_HasStdEnc|Feature_HasMSA, 4575 /* fmsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9491 { Feature_HasStdEnc|Feature_HasMSA, 4583 /* fmsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9492 { Feature_HasStdEnc|Feature_HasMSA, 4591 /* fmul.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9493 { Feature_HasStdEnc|Feature_HasMSA, 4598 /* fmul.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9494 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 4605 /* fork */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9495 { Feature_HasStdEnc|Feature_HasMSA, 4610 /* frcp.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9496 { Feature_HasStdEnc|Feature_HasMSA, 4617 /* frcp.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9497 { Feature_HasStdEnc|Feature_HasMSA, 4624 /* frint.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9498 { Feature_HasStdEnc|Feature_HasMSA, 4632 /* frint.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9499 { Feature_HasStdEnc|Feature_HasMSA, 4640 /* frsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9500 { Feature_HasStdEnc|Feature_HasMSA, 4649 /* frsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9501 { Feature_HasStdEnc|Feature_HasMSA, 4658 /* fsaf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9502 { Feature_HasStdEnc|Feature_HasMSA, 4665 /* fsaf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9503 { Feature_HasStdEnc|Feature_HasMSA, 4672 /* fseq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9504 { Feature_HasStdEnc|Feature_HasMSA, 4679 /* fseq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9505 { Feature_HasStdEnc|Feature_HasMSA, 4686 /* fsle.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9506 { Feature_HasStdEnc|Feature_HasMSA, 4693 /* fsle.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9507 { Feature_HasStdEnc|Feature_HasMSA, 4700 /* fslt.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9508 { Feature_HasStdEnc|Feature_HasMSA, 4707 /* fslt.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9509 { Feature_HasStdEnc|Feature_HasMSA, 4714 /* fsne.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9510 { Feature_HasStdEnc|Feature_HasMSA, 4721 /* fsne.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9511 { Feature_HasStdEnc|Feature_HasMSA, 4728 /* fsor.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9512 { Feature_HasStdEnc|Feature_HasMSA, 4735 /* fsor.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9513 { Feature_HasStdEnc|Feature_HasMSA, 4742 /* fsqrt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9514 { Feature_HasStdEnc|Feature_HasMSA, 4750 /* fsqrt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9515 { Feature_HasStdEnc|Feature_HasMSA, 4758 /* fsub.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9516 { Feature_HasStdEnc|Feature_HasMSA, 4765 /* fsub.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9517 { Feature_HasStdEnc|Feature_HasMSA, 4772 /* fsueq.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9518 { Feature_HasStdEnc|Feature_HasMSA, 4780 /* fsueq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9519 { Feature_HasStdEnc|Feature_HasMSA, 4788 /* fsule.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9520 { Feature_HasStdEnc|Feature_HasMSA, 4796 /* fsule.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9521 { Feature_HasStdEnc|Feature_HasMSA, 4804 /* fsult.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9522 { Feature_HasStdEnc|Feature_HasMSA, 4812 /* fsult.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9523 { Feature_HasStdEnc|Feature_HasMSA, 4820 /* fsun.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9524 { Feature_HasStdEnc|Feature_HasMSA, 4827 /* fsun.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9525 { Feature_HasStdEnc|Feature_HasMSA, 4834 /* fsune.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9526 { Feature_HasStdEnc|Feature_HasMSA, 4842 /* fsune.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9527 { Feature_HasStdEnc|Feature_HasMSA, 4850 /* ftint_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9528 { Feature_HasStdEnc|Feature_HasMSA, 4860 /* ftint_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9529 { Feature_HasStdEnc|Feature_HasMSA, 4870 /* ftint_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9530 { Feature_HasStdEnc|Feature_HasMSA, 4880 /* ftint_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9531 { Feature_HasStdEnc|Feature_HasMSA, 4890 /* ftq.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9532 { Feature_HasStdEnc|Feature_HasMSA, 4896 /* ftq.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9533 { Feature_HasStdEnc|Feature_HasMSA, 4902 /* ftrunc_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9534 { Feature_HasStdEnc|Feature_HasMSA, 4913 /* ftrunc_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9535 { Feature_HasStdEnc|Feature_HasMSA, 4924 /* ftrunc_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9536 { Feature_HasStdEnc|Feature_HasMSA, 4935 /* ftrunc_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9537 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4946 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9538 { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4946 /* ginvi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9539 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_HasGINV|Feature_NotInMicroMips, 4952 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9540 { Feature_InMicroMips|Feature_HasMips32r6|Feature_HasGINV, 4952 /* ginvt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9541 { Feature_HasStdEnc|Feature_HasMSA, 4958 /* hadd_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9542 { Feature_HasStdEnc|Feature_HasMSA, 4967 /* hadd_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9543 { Feature_HasStdEnc|Feature_HasMSA, 4976 /* hadd_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9544 { Feature_HasStdEnc|Feature_HasMSA, 4985 /* hadd_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9545 { Feature_HasStdEnc|Feature_HasMSA, 4994 /* hadd_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9546 { Feature_HasStdEnc|Feature_HasMSA, 5003 /* hadd_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9547 { Feature_HasStdEnc|Feature_HasMSA, 5012 /* hsub_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9548 { Feature_HasStdEnc|Feature_HasMSA, 5021 /* hsub_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9549 { Feature_HasStdEnc|Feature_HasMSA, 5030 /* hsub_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9550 { Feature_HasStdEnc|Feature_HasMSA, 5039 /* hsub_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9551 { Feature_HasStdEnc|Feature_HasMSA, 5048 /* hsub_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9552 { Feature_HasStdEnc|Feature_HasMSA, 5057 /* hsub_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9553 { Feature_HasStdEnc|Feature_HasMSA, 5074 /* ilvev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9554 { Feature_HasStdEnc|Feature_HasMSA, 5082 /* ilvev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9555 { Feature_HasStdEnc|Feature_HasMSA, 5090 /* ilvev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9556 { Feature_HasStdEnc|Feature_HasMSA, 5098 /* ilvev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9557 { Feature_HasStdEnc|Feature_HasMSA, 5106 /* ilvl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9558 { Feature_HasStdEnc|Feature_HasMSA, 5113 /* ilvl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9559 { Feature_HasStdEnc|Feature_HasMSA, 5120 /* ilvl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9560 { Feature_HasStdEnc|Feature_HasMSA, 5127 /* ilvl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9561 { Feature_HasStdEnc|Feature_HasMSA, 5134 /* ilvod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9562 { Feature_HasStdEnc|Feature_HasMSA, 5142 /* ilvod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9563 { Feature_HasStdEnc|Feature_HasMSA, 5150 /* ilvod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9564 { Feature_HasStdEnc|Feature_HasMSA, 5158 /* ilvod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9565 { Feature_HasStdEnc|Feature_HasMSA, 5166 /* ilvr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9566 { Feature_HasStdEnc|Feature_HasMSA, 5173 /* ilvr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9567 { Feature_HasStdEnc|Feature_HasMSA, 5180 /* ilvr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9568 { Feature_HasStdEnc|Feature_HasMSA, 5187 /* ilvr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9569 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9570 { Feature_InMicroMips|Feature_NotMips32r6, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9571 { Feature_InMicroMips|Feature_HasMips32r6, 5194 /* ins */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9572 { Feature_HasStdEnc|Feature_HasMSA, 5198 /* insert.b */, MCK_GPR32AsmReg, 16 /* 4 */ }, 9573 { Feature_HasStdEnc|Feature_HasMSA, 5198 /* insert.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9574 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5207 /* insert.d */, MCK_GPR64AsmReg, 16 /* 4 */ }, 9575 { Feature_HasStdEnc|Feature_HasMSA|Feature_HasMips64, 5207 /* insert.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9576 { Feature_HasStdEnc|Feature_HasMSA, 5216 /* insert.h */, MCK_GPR32AsmReg, 16 /* 4 */ }, 9577 { Feature_HasStdEnc|Feature_HasMSA, 5216 /* insert.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9578 { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.w */, MCK_GPR32AsmReg, 16 /* 4 */ }, 9579 { Feature_HasStdEnc|Feature_HasMSA, 5225 /* insert.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9580 { Feature_InMicroMips|Feature_HasDSP, 5234 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9581 { Feature_HasDSP, 5234 /* insv */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9582 { Feature_HasStdEnc|Feature_HasMSA, 5239 /* insve.b */, MCK_MSA128AsmReg, 17 /* 0, 4 */ }, 9583 { Feature_HasStdEnc|Feature_HasMSA, 5247 /* insve.d */, MCK_MSA128AsmReg, 17 /* 0, 4 */ }, 9584 { Feature_HasStdEnc|Feature_HasMSA, 5255 /* insve.h */, MCK_MSA128AsmReg, 17 /* 0, 4 */ }, 9585 { Feature_HasStdEnc|Feature_HasMSA, 5263 /* insve.w */, MCK_MSA128AsmReg, 17 /* 0, 4 */ }, 9586 { Feature_HasStdEnc|Feature_NotInMicroMips, 5271 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9587 { Feature_InMicroMips|Feature_NotMips32r6, 5271 /* j */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9588 { Feature_HasStdEnc|Feature_NotInMicroMips, 5271 /* j */, MCK_JumpTarget, 1 /* 0 */ }, 9589 { 0, 5273 /* jal */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9590 { Feature_HasStdEnc|Feature_NotInMicroMips, 5273 /* jal */, MCK_JumpTarget, 1 /* 0 */ }, 9591 { Feature_InMicroMips|Feature_HasMips32r6, 5273 /* jal */, MCK_JumpTarget, 1 /* 0 */ }, 9592 { 0, 5273 /* jal */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9593 { Feature_InMicroMips|Feature_NotMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9594 { Feature_InMicroMips|Feature_HasMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9595 { Feature_NotInMicroMips, 5277 /* jalr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9596 { Feature_HasStdEnc|Feature_NotInMicroMips|Feature_NoIndirectJumpGuards, 5277 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9597 { Feature_InMicroMips|Feature_NotMips32r6, 5277 /* jalr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9598 { Feature_NotInMips16Mode, 5277 /* jalr */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9599 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9600 { Feature_HasStdEnc|Feature_HasMips64|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9601 { Feature_HasStdEnc|Feature_HasMips32, 5282 /* jalr.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9602 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 5282 /* jalr.hb */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 9603 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5290 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9604 { Feature_InMicroMips|Feature_HasMips32r6, 5290 /* jalrc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9605 { Feature_HasStdEnc|Feature_HasMips64r6, 5290 /* jalrc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9606 { Feature_InMicroMips|Feature_HasMips32r6, 5290 /* jalrc */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9607 { Feature_InMicroMips|Feature_HasMips32r6, 5296 /* jalrc.hb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9608 { Feature_InMicroMips|Feature_HasMips32r6, 5296 /* jalrc.hb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9609 { Feature_InMicroMips|Feature_NotMips32r6, 5305 /* jalrs */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9610 { Feature_InMicroMips|Feature_NotMips32r6, 5311 /* jalrs16 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9611 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5324 /* jalx */, MCK_JumpTarget, 1 /* 0 */ }, 9612 { Feature_InMicroMips|Feature_NotMips32r6, 5324 /* jalx */, MCK_JumpTarget, 1 /* 0 */ }, 9613 { Feature_HasStdEnc|Feature_HasMips32r6, 5329 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9614 { Feature_HasStdEnc|Feature_HasMips32r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ }, 9615 { Feature_InMicroMips|Feature_HasMips32r6, 5329 /* jialc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9616 { Feature_InMicroMips|Feature_HasMips32r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ }, 9617 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5329 /* jialc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9618 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5329 /* jialc */, MCK_JumpTarget, 2 /* 1 */ }, 9619 { Feature_HasStdEnc|Feature_HasMips32r6, 5335 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9620 { Feature_HasStdEnc|Feature_HasMips32r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ }, 9621 { Feature_InMicroMips|Feature_HasMips32r6, 5335 /* jic */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9622 { Feature_InMicroMips|Feature_HasMips32r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ }, 9623 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5335 /* jic */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9624 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips64r6, 5335 /* jic */, MCK_JumpTarget, 2 /* 1 */ }, 9625 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9626 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9627 { Feature_InMicroMips|Feature_NotMips32r6, 5339 /* jr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9628 { Feature_NotInMips16Mode|Feature_IsPTR64bit|Feature_NotInMicroMips, 5339 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9629 { Feature_HasStdEnc|Feature_HasMips64r6, 5339 /* jr */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9630 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6, 5342 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9631 { Feature_HasStdEnc|Feature_HasMips32r6, 5342 /* jr.hb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9632 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5342 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9633 { Feature_HasStdEnc|Feature_HasMips32r6, 5342 /* jr.hb */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9634 { Feature_InMicroMips|Feature_NotMips32r6, 5348 /* jr16 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9635 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6, 5363 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9636 { Feature_InMicroMips|Feature_NotMips32r6, 5363 /* jrc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9637 { Feature_HasStdEnc|Feature_HasMips64r6, 5363 /* jrc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9638 { Feature_InMicroMips|Feature_HasMips32r6, 5367 /* jrc16 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9639 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9640 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9641 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9642 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 5384 /* l.d */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9643 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5388 /* l.s */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9644 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 5388 /* l.s */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9645 { 0, 5392 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9646 { 0, 5392 /* la */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9647 { 0, 5392 /* la */, MCK_Mem, 2 /* 1 */ }, 9648 { Feature_HasStdEnc|Feature_HasMips32r6, 5395 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9649 { Feature_InMicroMips|Feature_HasMips32r6, 5395 /* lapc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9650 { Feature_InMicroMips|Feature_HasMips32r6, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9651 { Feature_InMicroMips|Feature_HasMips32r6, 5400 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9652 { Feature_InMicroMips, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9653 { Feature_InMicroMips, 5400 /* lb */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9654 { Feature_HasStdEnc|Feature_NotInMicroMips, 5400 /* lb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9655 { Feature_HasStdEnc|Feature_NotInMicroMips, 5400 /* lb */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9656 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5403 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9657 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5403 /* lbe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9658 { Feature_InMicroMips|Feature_HasEVA, 5403 /* lbe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9659 { Feature_InMicroMips|Feature_HasEVA, 5403 /* lbe */, MCK_Mem, 2 /* 1 */ }, 9660 { Feature_InMicroMips|Feature_HasMips32r6, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9661 { Feature_InMicroMips|Feature_HasMips32r6, 5407 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9662 { Feature_InMicroMips, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9663 { Feature_InMicroMips, 5407 /* lbu */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9664 { Feature_HasStdEnc|Feature_NotInMicroMips, 5407 /* lbu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9665 { Feature_HasStdEnc|Feature_NotInMicroMips, 5407 /* lbu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9666 { Feature_InMicroMips, 5411 /* lbu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 9667 { Feature_InMicroMips, 5411 /* lbu16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 9668 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5417 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9669 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5417 /* lbue */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9670 { Feature_InMicroMips|Feature_HasEVA, 5417 /* lbue */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9671 { Feature_InMicroMips|Feature_HasEVA, 5417 /* lbue */, MCK_Mem, 2 /* 1 */ }, 9672 { Feature_InMicroMips|Feature_HasDSP, 5422 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9673 { Feature_HasDSP, 5422 /* lbux */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9674 { Feature_HasStdEnc|Feature_NotMips3, 5427 /* ld */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9675 { Feature_HasStdEnc|Feature_NotMips3, 5427 /* ld */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9676 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5427 /* ld */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9677 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5427 /* ld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9678 { Feature_HasStdEnc|Feature_HasMSA, 5430 /* ld.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9679 { Feature_HasStdEnc|Feature_HasMSA, 5430 /* ld.b */, MCK_MemOffsetSimm10, 2 /* 1 */ }, 9680 { Feature_HasStdEnc|Feature_HasMSA, 5435 /* ld.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9681 { Feature_HasStdEnc|Feature_HasMSA, 5435 /* ld.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ }, 9682 { Feature_HasStdEnc|Feature_HasMSA, 5440 /* ld.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9683 { Feature_HasStdEnc|Feature_HasMSA, 5440 /* ld.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ }, 9684 { Feature_HasStdEnc|Feature_HasMSA, 5445 /* ld.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9685 { Feature_HasStdEnc|Feature_HasMSA, 5445 /* ld.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ }, 9686 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9687 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9688 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9689 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9690 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9691 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9692 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9693 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5450 /* ldc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9694 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 9695 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 9696 { Feature_InMicroMips|Feature_HasMips32r6, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 9697 { Feature_InMicroMips|Feature_HasMips32r6, 5455 /* ldc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 9698 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 9699 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5455 /* ldc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9700 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5460 /* ldc3 */, MCK_COP3AsmReg, 1 /* 0 */ }, 9701 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 5460 /* ldc3 */, MCK_Mem, 2 /* 1 */ }, 9702 { Feature_HasStdEnc|Feature_HasMSA, 5465 /* ldi.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9703 { Feature_HasStdEnc|Feature_HasMSA, 5471 /* ldi.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9704 { Feature_HasStdEnc|Feature_HasMSA, 5477 /* ldi.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9705 { Feature_HasStdEnc|Feature_HasMSA, 5483 /* ldi.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 9706 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5489 /* ldl */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9707 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5489 /* ldl */, MCK_Mem, 2 /* 1 */ }, 9708 { Feature_HasStdEnc|Feature_HasMips64r6, 5493 /* ldpc */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9709 { Feature_HasStdEnc|Feature_HasMips64r6, 5493 /* ldpc */, MCK_JumpTarget, 2 /* 1 */ }, 9710 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5498 /* ldr */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9711 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 5498 /* ldr */, MCK_Mem, 2 /* 1 */ }, 9712 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5502 /* ldxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9713 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5502 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9714 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5502 /* ldxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9715 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5502 /* ldxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9716 { Feature_HasStdEnc|Feature_NotInMicroMips, 5508 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9717 { Feature_HasStdEnc|Feature_NotInMicroMips, 5508 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9718 { Feature_InMicroMips, 5508 /* lh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9719 { Feature_InMicroMips, 5508 /* lh */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9720 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5511 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9721 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5511 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9722 { Feature_InMicroMips|Feature_HasEVA, 5511 /* lhe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9723 { Feature_InMicroMips|Feature_HasEVA, 5511 /* lhe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9724 { Feature_HasStdEnc|Feature_NotInMicroMips, 5515 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9725 { Feature_HasStdEnc|Feature_NotInMicroMips, 5515 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9726 { Feature_InMicroMips, 5515 /* lhu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9727 { Feature_InMicroMips, 5515 /* lhu */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9728 { Feature_InMicroMips, 5519 /* lhu16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 9729 { Feature_InMicroMips, 5519 /* lhu16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 9730 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5525 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9731 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5525 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9732 { Feature_InMicroMips|Feature_HasEVA, 5525 /* lhue */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9733 { Feature_InMicroMips|Feature_HasEVA, 5525 /* lhue */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9734 { Feature_InMicroMips|Feature_HasDSP, 5530 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9735 { Feature_HasDSP, 5530 /* lhx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9736 { 0, 5534 /* li */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9737 { 0, 5537 /* li.d */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9738 { Feature_NotFP64bit|Feature_IsNotSoftFloat, 5537 /* li.d */, MCK_StrictlyAFGR64AsmReg, 1 /* 0 */ }, 9739 { Feature_IsFP64bit|Feature_IsNotSoftFloat, 5537 /* li.d */, MCK_StrictlyFGR64AsmReg, 1 /* 0 */ }, 9740 { 0, 5542 /* li.s */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9741 { Feature_IsNotSoftFloat, 5542 /* li.s */, MCK_StrictlyFGR32AsmReg, 1 /* 0 */ }, 9742 { Feature_InMicroMips|Feature_NotMips32r6, 5547 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 9743 { Feature_InMicroMips|Feature_HasMips32r6, 5547 /* li16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 9744 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9745 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9746 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9747 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9748 { Feature_InMicroMips|Feature_HasMips32r6, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9749 { Feature_InMicroMips|Feature_HasMips32r6, 5552 /* ll */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9750 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9751 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_Mem, 2 /* 1 */ }, 9752 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9753 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5552 /* ll */, MCK_Mem, 2 /* 1 */ }, 9754 { Feature_InMicroMips|Feature_NotMips32r6, 5552 /* ll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9755 { Feature_InMicroMips|Feature_NotMips32r6, 5552 /* ll */, MCK_Mem, 2 /* 1 */ }, 9756 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9757 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9758 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9759 { Feature_HasStdEnc|Feature_HasMips64r6|Feature_NotInMicroMips, 5555 /* lld */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 9760 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5559 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9761 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5559 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9762 { Feature_InMicroMips|Feature_HasEVA, 5559 /* lle */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9763 { Feature_InMicroMips|Feature_HasEVA, 5559 /* lle */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9764 { Feature_HasStdEnc|Feature_HasMSA, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9765 { Feature_InMicroMips|Feature_HasMips32r6, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9766 { Feature_HasStdEnc|Feature_HasMips32r6, 5563 /* lsa */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 9767 { Feature_InMicroMips|Feature_HasMips32r6, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9768 { Feature_HasStdEnc|Feature_NotInMicroMips, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9769 { Feature_InMicroMips|Feature_NotMips32r6, 5567 /* lui */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9770 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 9771 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9772 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9773 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9774 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5571 /* luxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 9775 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5571 /* luxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9776 { Feature_InMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9777 { Feature_InMicroMips, 5577 /* lw */, MCK_MicroMipsMemSP, 2 /* 1 */ }, 9778 { Feature_HasStdEnc|Feature_NotInMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9779 { Feature_HasStdEnc|Feature_NotInMicroMips, 5577 /* lw */, MCK_Mem, 2 /* 1 */ }, 9780 { Feature_NotInMips16Mode|Feature_HasDSP, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9781 { Feature_NotInMips16Mode|Feature_HasDSP, 5577 /* lw */, MCK_Mem, 2 /* 1 */ }, 9782 { Feature_InMicroMips|Feature_HasDSP, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9783 { Feature_InMicroMips|Feature_HasDSP, 5577 /* lw */, MCK_Mem, 2 /* 1 */ }, 9784 { Feature_InMicroMips|Feature_HasMips32r6, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9785 { Feature_InMicroMips|Feature_HasMips32r6, 5577 /* lw */, MCK_Mem, 2 /* 1 */ }, 9786 { Feature_InMicroMips, 5577 /* lw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9787 { Feature_InMicroMips, 5577 /* lw */, MCK_Mem, 2 /* 1 */ }, 9788 { Feature_InMicroMips, 5577 /* lw */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 9789 { Feature_InMicroMips, 5577 /* lw */, MCK_MicroMipsMemGP, 2 /* 1 */ }, 9790 { Feature_InMicroMips, 5580 /* lw16 */, MCK_GPRMM16AsmReg, 1 /* 0 */ }, 9791 { Feature_InMicroMips, 5580 /* lw16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 9792 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5585 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9793 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5585 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9794 { Feature_InMicroMips|Feature_IsNotSoftFloat, 5585 /* lwc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9795 { Feature_InMicroMips|Feature_IsNotSoftFloat, 5585 /* lwc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9796 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 9797 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 9798 { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 9799 { Feature_InMicroMips|Feature_HasMips32r6, 5590 /* lwc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 9800 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 9801 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5590 /* lwc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 9802 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5595 /* lwc3 */, MCK_COP3AsmReg, 1 /* 0 */ }, 9803 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 5595 /* lwc3 */, MCK_Mem, 2 /* 1 */ }, 9804 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5600 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9805 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 5600 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9806 { Feature_InMicroMips|Feature_HasEVA, 5600 /* lwe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9807 { Feature_InMicroMips|Feature_HasEVA, 5600 /* lwe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9808 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5604 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9809 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5604 /* lwl */, MCK_Mem, 2 /* 1 */ }, 9810 { Feature_InMicroMips|Feature_NotMips32r6, 5604 /* lwl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9811 { Feature_InMicroMips|Feature_NotMips32r6, 5604 /* lwl */, MCK_Mem, 2 /* 1 */ }, 9812 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5608 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9813 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5608 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9814 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5608 /* lwle */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9815 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5608 /* lwle */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9816 { Feature_InMicroMips, 5613 /* lwm */, MCK_Mem, 2 /* 1 */ }, 9817 { Feature_InMicroMips, 5613 /* lwm */, MCK_RegList, 1 /* 0 */ }, 9818 { Feature_InMicroMips|Feature_NotMips32r6, 5617 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ }, 9819 { Feature_InMicroMips|Feature_NotMips32r6, 5617 /* lwm16 */, MCK_RegList16, 1 /* 0 */ }, 9820 { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ }, 9821 { Feature_InMicroMips|Feature_HasMips32r6, 5617 /* lwm16 */, MCK_RegList16, 1 /* 0 */ }, 9822 { Feature_InMicroMips, 5623 /* lwm32 */, MCK_Mem, 2 /* 1 */ }, 9823 { Feature_InMicroMips, 5623 /* lwm32 */, MCK_RegList, 1 /* 0 */ }, 9824 { Feature_InMicroMips, 5629 /* lwp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9825 { Feature_InMicroMips, 5629 /* lwp */, MCK_MemOffsetSimm12, 2 /* 1 */ }, 9826 { Feature_HasStdEnc|Feature_HasMips32r6, 5633 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9827 { Feature_InMicroMips|Feature_HasMips32r6, 5633 /* lwpc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9828 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5638 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9829 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5638 /* lwr */, MCK_Mem, 2 /* 1 */ }, 9830 { Feature_InMicroMips|Feature_NotMips32r6, 5638 /* lwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9831 { Feature_InMicroMips|Feature_NotMips32r6, 5638 /* lwr */, MCK_Mem, 2 /* 1 */ }, 9832 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5642 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9833 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 5642 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9834 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5642 /* lwre */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9835 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 5642 /* lwre */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 9836 { Feature_InMicroMips|Feature_NotMips32r6, 5647 /* lwu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9837 { Feature_InMicroMips|Feature_NotMips32r6, 5647 /* lwu */, MCK_MemOffsetSimm12, 2 /* 1 */ }, 9838 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5647 /* lwu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 9839 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 5647 /* lwu */, MCK_Mem, 2 /* 1 */ }, 9840 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 5651 /* lwupc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9841 { Feature_InMicroMips|Feature_HasDSP, 5657 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9842 { Feature_HasDSP, 5657 /* lwx */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9843 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9844 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9845 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 9846 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 5661 /* lwxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 9847 { Feature_InMicroMips, 5667 /* lwxs */, MCK_GPR32AsmReg, 11 /* 0, 1, 3 */ }, 9848 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5672 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9849 { Feature_InMicroMips|Feature_NotMips32r6, 5672 /* madd */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9850 { Feature_InMicroMips|Feature_HasDSP, 5672 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9851 { Feature_InMicroMips|Feature_HasDSP, 5672 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9852 { Feature_HasDSP, 5672 /* madd */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9853 { Feature_HasDSP, 5672 /* madd */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9854 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5677 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 9855 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5677 /* madd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 9856 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5677 /* madd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 9857 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 5684 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 9858 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 5684 /* madd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 9859 { Feature_HasStdEnc|Feature_HasMSA, 5691 /* madd_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9860 { Feature_HasStdEnc|Feature_HasMSA, 5700 /* madd_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9861 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5709 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9862 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5709 /* maddf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9863 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5717 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9864 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5717 /* maddf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9865 { Feature_HasStdEnc|Feature_HasMSA, 5725 /* maddr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9866 { Feature_HasStdEnc|Feature_HasMSA, 5735 /* maddr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9867 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 5745 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9868 { Feature_InMicroMips|Feature_NotMips32r6, 5745 /* maddu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9869 { Feature_InMicroMips|Feature_HasDSP, 5745 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9870 { Feature_InMicroMips|Feature_HasDSP, 5745 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9871 { Feature_HasDSP, 5745 /* maddu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9872 { Feature_HasDSP, 5745 /* maddu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9873 { Feature_HasStdEnc|Feature_HasMSA, 5751 /* maddv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9874 { Feature_HasStdEnc|Feature_HasMSA, 5759 /* maddv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9875 { Feature_HasStdEnc|Feature_HasMSA, 5767 /* maddv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9876 { Feature_HasStdEnc|Feature_HasMSA, 5775 /* maddv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9877 { Feature_InMicroMips|Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9878 { Feature_InMicroMips|Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9879 { Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9880 { Feature_HasDSP, 5783 /* maq_s.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9881 { Feature_InMicroMips|Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9882 { Feature_InMicroMips|Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9883 { Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9884 { Feature_HasDSP, 5795 /* maq_s.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9885 { Feature_InMicroMips|Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9886 { Feature_InMicroMips|Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9887 { Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9888 { Feature_HasDSP, 5807 /* maq_sa.w.phl */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9889 { Feature_InMicroMips|Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9890 { Feature_InMicroMips|Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9891 { Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 9892 { Feature_HasDSP, 5820 /* maq_sa.w.phr */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 9893 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5833 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9894 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5833 /* max.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9895 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5839 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9896 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5839 /* max.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9897 { Feature_HasStdEnc|Feature_HasMSA, 5845 /* max_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9898 { Feature_HasStdEnc|Feature_HasMSA, 5853 /* max_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9899 { Feature_HasStdEnc|Feature_HasMSA, 5861 /* max_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9900 { Feature_HasStdEnc|Feature_HasMSA, 5869 /* max_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9901 { Feature_HasStdEnc|Feature_HasMSA, 5877 /* max_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9902 { Feature_HasStdEnc|Feature_HasMSA, 5885 /* max_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9903 { Feature_HasStdEnc|Feature_HasMSA, 5893 /* max_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9904 { Feature_HasStdEnc|Feature_HasMSA, 5901 /* max_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9905 { Feature_HasStdEnc|Feature_HasMSA, 5909 /* max_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9906 { Feature_HasStdEnc|Feature_HasMSA, 5917 /* max_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9907 { Feature_HasStdEnc|Feature_HasMSA, 5925 /* max_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9908 { Feature_HasStdEnc|Feature_HasMSA, 5933 /* max_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 9909 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5941 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9910 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5941 /* maxa.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 9911 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 5948 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9912 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 5948 /* maxa.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 9913 { Feature_HasStdEnc|Feature_HasMSA, 5955 /* maxi_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9914 { Feature_HasStdEnc|Feature_HasMSA, 5964 /* maxi_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9915 { Feature_HasStdEnc|Feature_HasMSA, 5973 /* maxi_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9916 { Feature_HasStdEnc|Feature_HasMSA, 5982 /* maxi_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9917 { Feature_HasStdEnc|Feature_HasMSA, 5991 /* maxi_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9918 { Feature_HasStdEnc|Feature_HasMSA, 6000 /* maxi_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9919 { Feature_HasStdEnc|Feature_HasMSA, 6009 /* maxi_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9920 { Feature_HasStdEnc|Feature_HasMSA, 6018 /* maxi_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 9921 { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9922 { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9923 { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9924 { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9925 { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9926 { Feature_HasStdEnc|Feature_NotInMicroMips, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9927 { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9928 { Feature_InMicroMips|Feature_HasMips32r6, 6027 /* mfc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9929 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9930 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9931 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9932 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9933 { Feature_InMicroMips|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9934 { Feature_InMicroMips|Feature_IsNotSoftFloat, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9935 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9936 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6032 /* mfc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9937 { Feature_InMicroMips|Feature_HasMips32r6, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9938 { Feature_InMicroMips|Feature_HasMips32r6, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9939 { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9940 { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9941 { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9942 { Feature_HasStdEnc|Feature_NotInMicroMips, 6037 /* mfc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9943 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9944 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9945 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9946 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9947 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9948 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9949 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9950 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6042 /* mfgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9951 { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9952 { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9953 { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9954 { Feature_InMicroMips|Feature_HasMips32r6, 6048 /* mfhc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9955 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9956 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9957 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 9958 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9959 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9960 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9961 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 9962 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6054 /* mfhc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9963 { Feature_InMicroMips|Feature_HasMips32r6, 6060 /* mfhc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 9964 { Feature_InMicroMips|Feature_HasMips32r6, 6060 /* mfhc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9965 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9966 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9967 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9968 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9969 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9970 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9971 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9972 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6066 /* mfhgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9973 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9974 { Feature_InMicroMips|Feature_NotMips32r6, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9975 { Feature_InMicroMips|Feature_HasDSP, 6073 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9976 { Feature_InMicroMips|Feature_HasDSP, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9977 { Feature_HasDSP, 6073 /* mfhi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9978 { Feature_HasDSP, 6073 /* mfhi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9979 { Feature_InMicroMips|Feature_NotMips32r6, 6078 /* mfhi16 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9980 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9981 { Feature_InMicroMips|Feature_NotMips32r6, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9982 { Feature_InMicroMips|Feature_HasDSP, 6085 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9983 { Feature_InMicroMips|Feature_HasDSP, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9984 { Feature_HasDSP, 6085 /* mflo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9985 { Feature_HasDSP, 6085 /* mflo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9986 { Feature_InMicroMips|Feature_NotMips32r6, 6090 /* mflo16 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9987 { Feature_HasMT|Feature_NotInMicroMips, 6097 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9988 { Feature_HasMT, 6097 /* mftacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 9989 { Feature_HasMT, 6097 /* mftacx */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9990 { Feature_HasMT|Feature_NotInMicroMips, 6104 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9991 { Feature_HasMT|Feature_NotInMicroMips, 6104 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9992 { Feature_HasMT, 6104 /* mftc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 9993 { Feature_HasMT, 6104 /* mftc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9994 { Feature_HasMT, 6110 /* mftc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9995 { Feature_HasMT, 6110 /* mftc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9996 { Feature_HasMT, 6116 /* mftdsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 9997 { Feature_HasMT, 6123 /* mftgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 9998 { Feature_HasMT, 6130 /* mfthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 9999 { Feature_HasMT, 6130 /* mfthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10000 { Feature_HasMT|Feature_NotInMicroMips, 6137 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10001 { Feature_HasMT, 6137 /* mfthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10002 { Feature_HasMT, 6137 /* mfthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10003 { Feature_HasMT|Feature_NotInMicroMips, 6143 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10004 { Feature_HasMT, 6143 /* mftlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10005 { Feature_HasMT, 6143 /* mftlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10006 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6149 /* mftr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10007 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6154 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10008 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6154 /* min.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10009 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6160 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10010 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6160 /* min.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10011 { Feature_HasStdEnc|Feature_HasMSA, 6166 /* min_a.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10012 { Feature_HasStdEnc|Feature_HasMSA, 6174 /* min_a.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10013 { Feature_HasStdEnc|Feature_HasMSA, 6182 /* min_a.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10014 { Feature_HasStdEnc|Feature_HasMSA, 6190 /* min_a.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10015 { Feature_HasStdEnc|Feature_HasMSA, 6198 /* min_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10016 { Feature_HasStdEnc|Feature_HasMSA, 6206 /* min_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10017 { Feature_HasStdEnc|Feature_HasMSA, 6214 /* min_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10018 { Feature_HasStdEnc|Feature_HasMSA, 6222 /* min_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10019 { Feature_HasStdEnc|Feature_HasMSA, 6230 /* min_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10020 { Feature_HasStdEnc|Feature_HasMSA, 6238 /* min_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10021 { Feature_HasStdEnc|Feature_HasMSA, 6246 /* min_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10022 { Feature_HasStdEnc|Feature_HasMSA, 6254 /* min_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10023 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6262 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10024 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6262 /* mina.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10025 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6269 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10026 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6269 /* mina.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10027 { Feature_HasStdEnc|Feature_HasMSA, 6276 /* mini_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10028 { Feature_HasStdEnc|Feature_HasMSA, 6285 /* mini_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10029 { Feature_HasStdEnc|Feature_HasMSA, 6294 /* mini_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10030 { Feature_HasStdEnc|Feature_HasMSA, 6303 /* mini_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10031 { Feature_HasStdEnc|Feature_HasMSA, 6312 /* mini_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10032 { Feature_HasStdEnc|Feature_HasMSA, 6321 /* mini_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10033 { Feature_HasStdEnc|Feature_HasMSA, 6330 /* mini_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10034 { Feature_HasStdEnc|Feature_HasMSA, 6339 /* mini_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10035 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6348 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10036 { Feature_InMicroMips|Feature_HasMips32r6, 6348 /* mod */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10037 { Feature_HasStdEnc|Feature_HasMSA, 6352 /* mod_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10038 { Feature_HasStdEnc|Feature_HasMSA, 6360 /* mod_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10039 { Feature_HasStdEnc|Feature_HasMSA, 6368 /* mod_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10040 { Feature_HasStdEnc|Feature_HasMSA, 6376 /* mod_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10041 { Feature_HasStdEnc|Feature_HasMSA, 6384 /* mod_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10042 { Feature_HasStdEnc|Feature_HasMSA, 6392 /* mod_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10043 { Feature_HasStdEnc|Feature_HasMSA, 6400 /* mod_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10044 { Feature_HasStdEnc|Feature_HasMSA, 6408 /* mod_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10045 { Feature_InMicroMips|Feature_HasDSP, 6416 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10046 { Feature_HasDSP, 6416 /* modsub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10047 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6423 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10048 { Feature_InMicroMips|Feature_HasMips32r6, 6423 /* modu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10049 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6428 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10050 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6428 /* mov.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10051 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6428 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10052 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6428 /* mov.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10053 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10054 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10055 { Feature_InMicroMips|Feature_IsNotSoftFloat, 6434 /* mov.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10056 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10057 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10058 { Feature_InMicroMips|Feature_NotMips32r6, 6440 /* move */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10059 { Feature_IsGP64bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10060 { Feature_IsGP64bit|Feature_NotInMicroMips, 6440 /* move */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10061 { Feature_HasStdEnc|Feature_HasMSA, 6445 /* move.v */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10062 { Feature_InMicroMips|Feature_HasMips32r6, 6452 /* move16 */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10063 { Feature_InMicroMips|Feature_NotMips32r6, 6459 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ }, 10064 { Feature_InMicroMips|Feature_NotMips32r6, 6459 /* movep */, MCK_MovePRegPair, 1 /* 0 */ }, 10065 { Feature_InMicroMips|Feature_HasMips32r6, 6459 /* movep */, MCK_GPRMM16AsmRegMoveP, 6 /* 1, 2 */ }, 10066 { Feature_InMicroMips|Feature_HasMips32r6, 6459 /* movep */, MCK_MovePRegPair, 1 /* 0 */ }, 10067 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6465 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ }, 10068 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6465 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10069 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6465 /* movf */, MCK_FCCAsmReg, 4 /* 2 */ }, 10070 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6465 /* movf */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10071 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10072 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ }, 10073 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6470 /* movf.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10074 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ }, 10075 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FCCAsmReg, 4 /* 2 */ }, 10076 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6470 /* movf.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10077 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6477 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ }, 10078 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6477 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10079 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6477 /* movf.s */, MCK_FCCAsmReg, 4 /* 2 */ }, 10080 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6477 /* movf.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10081 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6484 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10082 { Feature_InMicroMips|Feature_NotMips32r6, 6484 /* movn */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10083 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10084 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10085 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6489 /* movn.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10086 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10087 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10088 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6489 /* movn.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10089 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6496 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10090 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6496 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10091 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6496 /* movn.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10092 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6496 /* movn.s */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10093 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6503 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ }, 10094 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6503 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10095 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6503 /* movt */, MCK_FCCAsmReg, 4 /* 2 */ }, 10096 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6503 /* movt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10097 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10098 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ }, 10099 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6508 /* movt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10100 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ }, 10101 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FCCAsmReg, 4 /* 2 */ }, 10102 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6508 /* movt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10103 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6515 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ }, 10104 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6515 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10105 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6515 /* movt.s */, MCK_FCCAsmReg, 4 /* 2 */ }, 10106 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6515 /* movt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10107 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6522 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10108 { Feature_InMicroMips|Feature_NotMips32r6, 6522 /* movz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10109 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10110 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10111 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6527 /* movz.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10112 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10113 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10114 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6527 /* movz.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10115 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6534 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10116 { Feature_HasStdEnc|Feature_HasMips4_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6534 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10117 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6534 /* movz.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10118 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 6534 /* movz.s */, MCK_GPR32AsmReg, 4 /* 2 */ }, 10119 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6541 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10120 { Feature_InMicroMips|Feature_NotMips32r6, 6541 /* msub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10121 { Feature_InMicroMips|Feature_HasDSP, 6541 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10122 { Feature_InMicroMips|Feature_HasDSP, 6541 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10123 { Feature_HasDSP, 6541 /* msub */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10124 { Feature_HasDSP, 6541 /* msub */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10125 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6546 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10126 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6546 /* msub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10127 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6546 /* msub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10128 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips|Feature_HasMadd4, 6553 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 10129 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 6553 /* msub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 10130 { Feature_HasStdEnc|Feature_HasMSA, 6560 /* msub_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10131 { Feature_HasStdEnc|Feature_HasMSA, 6569 /* msub_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10132 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6578 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10133 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6578 /* msubf.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10134 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6586 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10135 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6586 /* msubf.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10136 { Feature_HasStdEnc|Feature_HasMSA, 6594 /* msubr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10137 { Feature_HasStdEnc|Feature_HasMSA, 6604 /* msubr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10138 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6614 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10139 { Feature_InMicroMips|Feature_NotMips32r6, 6614 /* msubu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10140 { Feature_InMicroMips|Feature_HasDSP, 6614 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10141 { Feature_InMicroMips|Feature_HasDSP, 6614 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10142 { Feature_HasDSP, 6614 /* msubu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10143 { Feature_HasDSP, 6614 /* msubu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10144 { Feature_HasStdEnc|Feature_HasMSA, 6620 /* msubv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10145 { Feature_HasStdEnc|Feature_HasMSA, 6628 /* msubv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10146 { Feature_HasStdEnc|Feature_HasMSA, 6636 /* msubv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10147 { Feature_HasStdEnc|Feature_HasMSA, 6644 /* msubv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10148 { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10149 { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10150 { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10151 { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10152 { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10153 { Feature_HasStdEnc|Feature_NotInMicroMips, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10154 { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10155 { Feature_InMicroMips|Feature_HasMips32r6, 6652 /* mtc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10156 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10157 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10158 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10159 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10160 { Feature_InMicroMips|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10161 { Feature_InMicroMips|Feature_IsNotSoftFloat, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10162 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 10163 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6657 /* mtc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10164 { Feature_InMicroMips|Feature_HasMips32r6, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 10165 { Feature_InMicroMips|Feature_HasMips32r6, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10166 { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 10167 { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10168 { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 10169 { Feature_HasStdEnc|Feature_NotInMicroMips, 6662 /* mtc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10170 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10171 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10172 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10173 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10174 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10175 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10176 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10177 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6667 /* mtgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10178 { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10179 { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10180 { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10181 { Feature_InMicroMips|Feature_HasMips32r6, 6673 /* mthc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10182 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 10183 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10184 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 10185 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10186 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 10187 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10188 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_FGR64AsmReg, 2 /* 1 */ }, 10189 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6679 /* mthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10190 { Feature_InMicroMips|Feature_HasMips32r6, 6685 /* mthc2 */, MCK_COP2AsmReg, 2 /* 1 */ }, 10191 { Feature_InMicroMips|Feature_HasMips32r6, 6685 /* mthc2 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10192 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10193 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10194 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10195 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10196 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10197 { Feature_HasStdEnc|Feature_HasMips32r5|Feature_HasVirt|Feature_NotInMicroMips, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10198 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10199 { Feature_InMicroMips|Feature_HasMips32r5|Feature_HasVirt, 6691 /* mthgc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10200 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10201 { Feature_InMicroMips|Feature_NotMips32r6, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10202 { Feature_InMicroMips|Feature_HasDSP, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10203 { Feature_InMicroMips|Feature_HasDSP, 6698 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ }, 10204 { Feature_HasDSP, 6698 /* mthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10205 { Feature_HasDSP, 6698 /* mthi */, MCK_HI32DSPAsmReg, 2 /* 1 */ }, 10206 { Feature_InMicroMips|Feature_HasDSP, 6703 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10207 { Feature_InMicroMips|Feature_HasDSP, 6703 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10208 { Feature_HasDSP, 6703 /* mthlip */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10209 { Feature_HasDSP, 6703 /* mthlip */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10210 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10211 { Feature_InMicroMips|Feature_NotMips32r6, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10212 { Feature_InMicroMips|Feature_HasDSP, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10213 { Feature_InMicroMips|Feature_HasDSP, 6710 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ }, 10214 { Feature_HasDSP, 6710 /* mtlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10215 { Feature_HasDSP, 6710 /* mtlo */, MCK_LO32DSPAsmReg, 2 /* 1 */ }, 10216 { Feature_HasCnMips, 6715 /* mtm0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10217 { Feature_HasCnMips, 6720 /* mtm1 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10218 { Feature_HasCnMips, 6725 /* mtm2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10219 { Feature_HasCnMips, 6730 /* mtp0 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10220 { Feature_HasCnMips, 6735 /* mtp1 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10221 { Feature_HasCnMips, 6740 /* mtp2 */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10222 { Feature_HasMT|Feature_NotInMicroMips, 6745 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10223 { Feature_HasMT, 6745 /* mttacx */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10224 { Feature_HasMT, 6745 /* mttacx */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10225 { Feature_HasMT|Feature_NotInMicroMips, 6752 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10226 { Feature_HasMT|Feature_NotInMicroMips, 6752 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10227 { Feature_HasMT, 6752 /* mttc0 */, MCK_COP0AsmReg, 2 /* 1 */ }, 10228 { Feature_HasMT, 6752 /* mttc0 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10229 { Feature_HasMT, 6758 /* mttc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10230 { Feature_HasMT, 6758 /* mttc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10231 { Feature_HasMT, 6764 /* mttdsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10232 { Feature_HasMT, 6771 /* mttgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10233 { Feature_HasMT, 6778 /* mtthc1 */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10234 { Feature_HasMT, 6778 /* mtthc1 */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10235 { Feature_HasMT|Feature_NotInMicroMips, 6785 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10236 { Feature_HasMT, 6785 /* mtthi */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10237 { Feature_HasMT, 6785 /* mtthi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10238 { Feature_HasMT|Feature_NotInMicroMips, 6791 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10239 { Feature_HasMT, 6791 /* mttlo */, MCK_ACC64DSPAsmReg, 2 /* 1 */ }, 10240 { Feature_HasMT, 6791 /* mttlo */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10241 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 6797 /* mttr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10242 { Feature_InMicroMips|Feature_HasMips32r6, 6802 /* muh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10243 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6802 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10244 { Feature_InMicroMips|Feature_HasMips32r6, 6802 /* muh */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10245 { Feature_InMicroMips|Feature_HasMips32r6, 6806 /* muhu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10246 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6806 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10247 { Feature_InMicroMips|Feature_HasMips32r6, 6806 /* muhu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10248 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10249 { Feature_InMicroMips|Feature_NotMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10250 { Feature_InMicroMips|Feature_HasMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10251 { Feature_HasStdEnc|Feature_HasMips32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10252 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10253 { Feature_InMicroMips|Feature_NotMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10254 { Feature_InMicroMips|Feature_HasMips32r6, 6811 /* mul */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10255 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6811 /* mul */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10256 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6815 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 10257 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 6815 /* mul.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 10258 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6815 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10259 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 6815 /* mul.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10260 { Feature_InMicroMips|Feature_HasDSPR2, 6821 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10261 { Feature_HasDSPR2, 6821 /* mul.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10262 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10263 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10264 { Feature_InMicroMips|Feature_IsNotSoftFloat, 6828 /* mul.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10265 { Feature_HasStdEnc|Feature_HasMSA, 6834 /* mul_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10266 { Feature_HasStdEnc|Feature_HasMSA, 6842 /* mul_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10267 { Feature_InMicroMips|Feature_HasDSPR2, 6850 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10268 { Feature_HasDSPR2, 6850 /* mul_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10269 { Feature_InMicroMips|Feature_HasDSP, 6859 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10270 { Feature_HasDSP, 6859 /* muleq_s.w.phl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10271 { Feature_InMicroMips|Feature_HasDSP, 6873 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10272 { Feature_HasDSP, 6873 /* muleq_s.w.phr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10273 { Feature_InMicroMips|Feature_HasDSP, 6887 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10274 { Feature_HasDSP, 6887 /* muleu_s.ph.qbl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10275 { Feature_InMicroMips|Feature_HasDSP, 6902 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10276 { Feature_HasDSP, 6902 /* muleu_s.ph.qbr */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10277 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6917 /* mulo */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10278 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6917 /* mulo */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10279 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6922 /* mulou */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10280 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 6922 /* mulou */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10281 { Feature_InMicroMips|Feature_HasDSP, 6928 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10282 { Feature_HasDSP, 6928 /* mulq_rs.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10283 { Feature_InMicroMips|Feature_HasDSPR2, 6939 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10284 { Feature_HasDSPR2, 6939 /* mulq_rs.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10285 { Feature_InMicroMips|Feature_HasDSPR2, 6949 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10286 { Feature_HasDSPR2, 6949 /* mulq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10287 { Feature_InMicroMips|Feature_HasDSPR2, 6959 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10288 { Feature_HasDSPR2, 6959 /* mulq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10289 { Feature_HasStdEnc|Feature_HasMSA, 6968 /* mulr_q.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10290 { Feature_HasStdEnc|Feature_HasMSA, 6977 /* mulr_q.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10291 { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10292 { Feature_InMicroMips|Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10293 { Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10294 { Feature_HasDSPR2, 6986 /* mulsa.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10295 { Feature_InMicroMips|Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10296 { Feature_InMicroMips|Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10297 { Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10298 { Feature_HasDSP, 6997 /* mulsaq_s.w.ph */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10299 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7011 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10300 { Feature_InMicroMips|Feature_NotMips32r6, 7011 /* mult */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10301 { Feature_InMicroMips|Feature_HasDSP, 7011 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10302 { Feature_InMicroMips|Feature_HasDSP, 7011 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10303 { Feature_HasDSP, 7011 /* mult */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10304 { Feature_HasDSP, 7011 /* mult */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10305 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7016 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10306 { Feature_InMicroMips|Feature_NotMips32r6, 7016 /* multu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10307 { Feature_InMicroMips|Feature_HasDSP, 7016 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10308 { Feature_InMicroMips|Feature_HasDSP, 7016 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10309 { Feature_HasDSP, 7016 /* multu */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10310 { Feature_HasDSP, 7016 /* multu */, MCK_GPR32AsmReg, 6 /* 1, 2 */ }, 10311 { Feature_InMicroMips|Feature_HasMips32r6, 7022 /* mulu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10312 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7022 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10313 { Feature_InMicroMips|Feature_HasMips32r6, 7022 /* mulu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10314 { Feature_HasStdEnc|Feature_HasMSA, 7027 /* mulv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10315 { Feature_HasStdEnc|Feature_HasMSA, 7034 /* mulv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10316 { Feature_HasStdEnc|Feature_HasMSA, 7041 /* mulv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10317 { Feature_HasStdEnc|Feature_HasMSA, 7048 /* mulv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10318 { Feature_HasStdEnc|Feature_NotInMicroMips, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10319 { Feature_InMicroMips|Feature_NotMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10320 { Feature_InMicroMips|Feature_HasMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10321 { Feature_HasStdEnc|Feature_NotInMicroMips, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10322 { Feature_InMicroMips|Feature_NotMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10323 { Feature_InMicroMips|Feature_HasMips32r6, 7055 /* neg */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10324 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7059 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10325 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7059 /* neg.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10326 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7059 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10327 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7059 /* neg.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10328 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10329 { Feature_HasStdEnc|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10330 { Feature_InMicroMips|Feature_IsNotSoftFloat, 7065 /* neg.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10331 { Feature_HasStdEnc|Feature_NotInMicroMips, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10332 { Feature_InMicroMips|Feature_NotMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10333 { Feature_InMicroMips|Feature_HasMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10334 { Feature_HasStdEnc|Feature_NotInMicroMips, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10335 { Feature_InMicroMips|Feature_NotMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10336 { Feature_InMicroMips|Feature_HasMips32r6, 7071 /* negu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10337 { Feature_HasStdEnc|Feature_HasMSA, 7076 /* nloc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10338 { Feature_HasStdEnc|Feature_HasMSA, 7083 /* nloc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10339 { Feature_HasStdEnc|Feature_HasMSA, 7090 /* nloc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10340 { Feature_HasStdEnc|Feature_HasMSA, 7097 /* nloc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10341 { Feature_HasStdEnc|Feature_HasMSA, 7104 /* nlzc.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10342 { Feature_HasStdEnc|Feature_HasMSA, 7111 /* nlzc.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10343 { Feature_HasStdEnc|Feature_HasMSA, 7118 /* nlzc.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10344 { Feature_HasStdEnc|Feature_HasMSA, 7125 /* nlzc.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10345 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7132 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10346 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7132 /* nmadd.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10347 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7132 /* nmadd.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10348 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7140 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 10349 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7140 /* nmadd.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 10350 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7148 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10351 { Feature_InMicroMips|Feature_NotFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7148 /* nmsub.d */, MCK_AFGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10352 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7148 /* nmsub.d */, MCK_FGR64AsmReg, 15 /* 0, 1, 2, 3 */ }, 10353 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_HasMadd4|Feature_NotInMicroMips, 7156 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 10354 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat|Feature_HasMadd4, 7156 /* nmsub.s */, MCK_FGR32AsmReg, 15 /* 0, 1, 2, 3 */ }, 10355 { Feature_IsGP32bit, 7168 /* nor */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10356 { Feature_IsGP64bit, 7168 /* nor */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10357 { Feature_HasStdEnc|Feature_NotInMicroMips, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10358 { Feature_InMicroMips|Feature_NotMips32r6, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10359 { Feature_InMicroMips|Feature_HasMips32r6, 7168 /* nor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10360 { Feature_IsGP32bit, 7168 /* nor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10361 { Feature_IsGP64bit, 7168 /* nor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10362 { Feature_HasStdEnc|Feature_HasMSA, 7172 /* nor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10363 { Feature_HasStdEnc|Feature_HasMSA, 7178 /* nori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10364 { Feature_HasStdEnc|Feature_NotInMicroMips, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10365 { Feature_InMicroMips|Feature_NotMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10366 { Feature_InMicroMips|Feature_HasMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10367 { Feature_HasStdEnc|Feature_NotInMicroMips, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10368 { Feature_InMicroMips|Feature_NotMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10369 { Feature_InMicroMips|Feature_HasMips32r6, 7185 /* not */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10370 { Feature_InMicroMips|Feature_NotMips32r6, 7189 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10371 { Feature_InMicroMips|Feature_HasMips32r6, 7189 /* not16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10372 { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10373 { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10374 { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10375 { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10376 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10377 { Feature_InMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10378 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10379 { Feature_HasStdEnc|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10380 { Feature_InMicroMips|Feature_NotMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10381 { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10382 { Feature_InMicroMips|Feature_HasMips32r6, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10383 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10384 { Feature_InMicroMips, 7195 /* or */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10385 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 7195 /* or */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10386 { Feature_HasStdEnc|Feature_HasMSA, 7198 /* or.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10387 { Feature_InMicroMips|Feature_NotMips32r6, 7203 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10388 { Feature_InMicroMips|Feature_HasMips32r6, 7203 /* or16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10389 { Feature_InMicroMips|Feature_HasMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10390 { Feature_HasStdEnc|Feature_NotInMicroMips, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10391 { Feature_InMicroMips|Feature_NotMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10392 { Feature_InMicroMips|Feature_HasMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10393 { Feature_HasStdEnc|Feature_NotInMicroMips, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10394 { Feature_InMicroMips|Feature_NotMips32r6, 7208 /* ori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10395 { Feature_HasStdEnc|Feature_HasMSA, 7212 /* ori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10396 { Feature_InMicroMips|Feature_HasDSP, 7218 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10397 { Feature_HasDSP, 7218 /* packrl.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10398 { Feature_HasStdEnc|Feature_HasMSA, 7234 /* pckev.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10399 { Feature_HasStdEnc|Feature_HasMSA, 7242 /* pckev.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10400 { Feature_HasStdEnc|Feature_HasMSA, 7250 /* pckev.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10401 { Feature_HasStdEnc|Feature_HasMSA, 7258 /* pckev.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10402 { Feature_HasStdEnc|Feature_HasMSA, 7266 /* pckod.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10403 { Feature_HasStdEnc|Feature_HasMSA, 7274 /* pckod.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10404 { Feature_HasStdEnc|Feature_HasMSA, 7282 /* pckod.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10405 { Feature_HasStdEnc|Feature_HasMSA, 7290 /* pckod.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10406 { Feature_HasStdEnc|Feature_HasMSA, 7298 /* pcnt.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10407 { Feature_HasStdEnc|Feature_HasMSA, 7305 /* pcnt.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10408 { Feature_HasStdEnc|Feature_HasMSA, 7312 /* pcnt.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10409 { Feature_HasStdEnc|Feature_HasMSA, 7319 /* pcnt.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10410 { Feature_InMicroMips|Feature_HasDSP, 7326 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10411 { Feature_HasDSP, 7326 /* pick.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10412 { Feature_InMicroMips|Feature_HasDSP, 7334 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10413 { Feature_HasDSP, 7334 /* pick.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10414 { Feature_HasCnMips, 7342 /* pop */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10415 { Feature_HasCnMips, 7342 /* pop */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10416 { Feature_InMicroMips|Feature_HasDSP, 7346 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10417 { Feature_HasDSP, 7346 /* preceq.w.phl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10418 { Feature_InMicroMips|Feature_HasDSP, 7359 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10419 { Feature_HasDSP, 7359 /* preceq.w.phr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10420 { Feature_InMicroMips|Feature_HasDSP, 7372 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10421 { Feature_HasDSP, 7372 /* precequ.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10422 { Feature_InMicroMips|Feature_HasDSP, 7387 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10423 { Feature_HasDSP, 7387 /* precequ.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10424 { Feature_InMicroMips|Feature_HasDSP, 7403 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10425 { Feature_HasDSP, 7403 /* precequ.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10426 { Feature_InMicroMips|Feature_HasDSP, 7418 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10427 { Feature_HasDSP, 7418 /* precequ.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10428 { Feature_InMicroMips|Feature_HasDSP, 7434 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10429 { Feature_HasDSP, 7434 /* preceu.ph.qbl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10430 { Feature_InMicroMips|Feature_HasDSP, 7448 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10431 { Feature_HasDSP, 7448 /* preceu.ph.qbla */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10432 { Feature_InMicroMips|Feature_HasDSP, 7463 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10433 { Feature_HasDSP, 7463 /* preceu.ph.qbr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10434 { Feature_InMicroMips|Feature_HasDSP, 7477 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10435 { Feature_HasDSP, 7477 /* preceu.ph.qbra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10436 { Feature_InMicroMips|Feature_HasDSPR2, 7492 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10437 { Feature_HasDSPR2, 7492 /* precr.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10438 { Feature_InMicroMips|Feature_HasDSPR2, 7504 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10439 { Feature_HasDSPR2, 7504 /* precr_sra.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10440 { Feature_InMicroMips|Feature_HasDSPR2, 7519 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10441 { Feature_HasDSPR2, 7519 /* precr_sra_r.ph.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10442 { Feature_InMicroMips|Feature_HasDSP, 7536 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10443 { Feature_HasDSP, 7536 /* precrq.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10444 { Feature_InMicroMips|Feature_HasDSP, 7548 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10445 { Feature_HasDSP, 7548 /* precrq.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10446 { Feature_InMicroMips|Feature_HasDSP, 7561 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10447 { Feature_HasDSP, 7561 /* precrq_rs.ph.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10448 { Feature_InMicroMips|Feature_HasDSP, 7576 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10449 { Feature_HasDSP, 7576 /* precrqu_s.qb.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10450 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7592 /* pref */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10451 { Feature_HasStdEnc|Feature_HasMips3_32|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7592 /* pref */, MCK_Mem, 2 /* 1 */ }, 10452 { Feature_InMicroMips|Feature_NotMips32r6, 7592 /* pref */, MCK_Mem, 2 /* 1 */ }, 10453 { Feature_InMicroMips|Feature_HasMips32r6, 7592 /* pref */, MCK_Mem, 2 /* 1 */ }, 10454 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7597 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10455 { Feature_InMicroMips|Feature_HasEVA, 7597 /* prefe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10456 { Feature_InMicroMips|Feature_NotMips32r6, 7603 /* prefx */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 10457 { Feature_InMicroMips|Feature_HasDSPR2, 7609 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10458 { Feature_HasDSPR2, 7609 /* prepend */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10459 { Feature_InMicroMips|Feature_HasDSP, 7617 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10460 { Feature_HasDSP, 7617 /* raddu.w.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10461 { Feature_InMicroMips|Feature_HasDSP, 7628 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10462 { Feature_HasDSP, 7628 /* rddsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10463 { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10464 { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ }, 10465 { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10466 { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ }, 10467 { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10468 { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ }, 10469 { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10470 { Feature_InMicroMips|Feature_HasMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ }, 10471 { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10472 { Feature_HasStdEnc|Feature_NotInMicroMips, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ }, 10473 { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10474 { Feature_InMicroMips|Feature_NotMips32r6, 7634 /* rdhwr */, MCK_HWRegsAsmReg, 2 /* 1 */ }, 10475 { Feature_InMicroMips|Feature_HasMips32r6, 7640 /* rdpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10476 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7647 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10477 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7647 /* recip.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10478 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7647 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10479 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7647 /* recip.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10480 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7655 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10481 { Feature_InMicroMips|Feature_IsNotSoftFloat, 7655 /* recip.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10482 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10483 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10484 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10485 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7663 /* rem */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10486 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10487 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10488 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10489 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 7667 /* remu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10490 { Feature_InMicroMips|Feature_HasDSP, 7672 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10491 { Feature_HasDSP, 7672 /* repl.ph */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10492 { Feature_InMicroMips|Feature_HasDSP, 7680 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10493 { Feature_HasDSP, 7680 /* repl.qb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10494 { Feature_InMicroMips|Feature_HasDSP, 7688 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10495 { Feature_HasDSP, 7688 /* replv.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10496 { Feature_InMicroMips|Feature_HasDSP, 7697 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10497 { Feature_HasDSP, 7697 /* replv.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10498 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7706 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10499 { Feature_InMicroMips|Feature_HasMips32r6, 7706 /* rint.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10500 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7713 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10501 { Feature_InMicroMips|Feature_HasMips32r6, 7713 /* rint.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10502 { 0, 7720 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10503 { 0, 7720 /* rol */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10504 { 0, 7720 /* rol */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10505 { 0, 7720 /* rol */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10506 { 0, 7724 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10507 { 0, 7724 /* ror */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10508 { 0, 7724 /* ror */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10509 { 0, 7724 /* ror */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10510 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10511 { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10512 { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10513 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10514 { Feature_InMicroMips, 7728 /* rotr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10515 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7733 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10516 { Feature_InMicroMips, 7733 /* rotrv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10517 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7739 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10518 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7739 /* round.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10519 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7749 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10520 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7749 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10521 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7749 /* round.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 10522 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7749 /* round.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10523 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 10524 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 10525 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 10526 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 10527 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 10528 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7759 /* round.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 10529 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7759 /* round.w.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10530 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10531 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10532 { Feature_InMicroMips|Feature_IsNotSoftFloat, 7769 /* round.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10533 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7779 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10534 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7779 /* rsqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10535 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7779 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10536 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 7779 /* rsqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10537 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7787 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10538 { Feature_NotInMips16Mode|Feature_IsNotSoftFloat, 7787 /* rsqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10539 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 10540 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10541 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10542 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat, 7795 /* s.d */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10543 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7799 /* s.s */, MCK_FGR32AsmReg, 1 /* 0 */ }, 10544 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat, 7799 /* s.s */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10545 { Feature_HasStdEnc|Feature_HasMSA, 7803 /* sat_s.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10546 { Feature_HasStdEnc|Feature_HasMSA, 7811 /* sat_s.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10547 { Feature_HasStdEnc|Feature_HasMSA, 7819 /* sat_s.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10548 { Feature_HasStdEnc|Feature_HasMSA, 7827 /* sat_s.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10549 { Feature_HasStdEnc|Feature_HasMSA, 7835 /* sat_u.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10550 { Feature_HasStdEnc|Feature_HasMSA, 7843 /* sat_u.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10551 { Feature_HasStdEnc|Feature_HasMSA, 7851 /* sat_u.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10552 { Feature_HasStdEnc|Feature_HasMSA, 7859 /* sat_u.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10553 { Feature_HasStdEnc|Feature_NotInMicroMips, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10554 { Feature_HasStdEnc|Feature_NotInMicroMips, 7867 /* sb */, MCK_Mem, 2 /* 1 */ }, 10555 { Feature_InMicroMips|Feature_HasMips32r6, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10556 { Feature_InMicroMips|Feature_HasMips32r6, 7867 /* sb */, MCK_Mem, 2 /* 1 */ }, 10557 { Feature_InMicroMips, 7867 /* sb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10558 { Feature_InMicroMips, 7867 /* sb */, MCK_Mem, 2 /* 1 */ }, 10559 { Feature_InMicroMips|Feature_NotMips32r6, 7870 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ }, 10560 { Feature_InMicroMips|Feature_NotMips32r6, 7870 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 10561 { Feature_InMicroMips|Feature_HasMips32r6, 7870 /* sb16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ }, 10562 { Feature_InMicroMips|Feature_HasMips32r6, 7870 /* sb16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 10563 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7875 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10564 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7875 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10565 { Feature_InMicroMips|Feature_HasEVA, 7875 /* sbe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10566 { Feature_InMicroMips|Feature_HasEVA, 7875 /* sbe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10567 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10568 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10569 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10570 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10571 { Feature_InMicroMips|Feature_HasMips32r6, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10572 { Feature_InMicroMips|Feature_HasMips32r6, 7879 /* sc */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10573 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10574 { Feature_HasStdEnc|Feature_IsPTR32bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_Mem, 2 /* 1 */ }, 10575 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10576 { Feature_HasStdEnc|Feature_IsPTR64bit|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7879 /* sc */, MCK_Mem, 2 /* 1 */ }, 10577 { Feature_InMicroMips|Feature_NotMips32r6, 7879 /* sc */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10578 { Feature_InMicroMips|Feature_NotMips32r6, 7879 /* sc */, MCK_Mem, 2 /* 1 */ }, 10579 { Feature_HasStdEnc|Feature_HasMips32r6, 7882 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10580 { Feature_HasStdEnc|Feature_HasMips32r6, 7882 /* scd */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10581 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7882 /* scd */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10582 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7882 /* scd */, MCK_Mem, 2 /* 1 */ }, 10583 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7886 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10584 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 7886 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10585 { Feature_InMicroMips|Feature_HasEVA, 7886 /* sce */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10586 { Feature_InMicroMips|Feature_HasEVA, 7886 /* sce */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10587 { Feature_HasStdEnc|Feature_NotMips3, 7890 /* sd */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10588 { Feature_HasStdEnc|Feature_NotMips3, 7890 /* sd */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10589 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7890 /* sd */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10590 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotInMicroMips, 7890 /* sd */, MCK_MemOffsetSimmPtr, 2 /* 1 */ }, 10591 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 10592 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10593 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 10594 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10595 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10596 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10597 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10598 { Feature_InMicroMips|Feature_IsFP64bit|Feature_HasMips32r6|Feature_IsNotSoftFloat, 7907 /* sdc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10599 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 10600 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 10601 { Feature_InMicroMips|Feature_HasMips32r6, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 10602 { Feature_InMicroMips|Feature_HasMips32r6, 7912 /* sdc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 10603 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 10604 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 7912 /* sdc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10605 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7917 /* sdc3 */, MCK_COP3AsmReg, 1 /* 0 */ }, 10606 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotCnMips|Feature_NotInMicroMips, 7917 /* sdc3 */, MCK_Mem, 2 /* 1 */ }, 10607 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7922 /* sdl */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10608 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7922 /* sdl */, MCK_Mem, 2 /* 1 */ }, 10609 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7926 /* sdr */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10610 { Feature_HasStdEnc|Feature_HasMips3|Feature_NotMips32r6|Feature_NotMips64r6, 7926 /* sdr */, MCK_Mem, 2 /* 1 */ }, 10611 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7930 /* sdxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 10612 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7930 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 10613 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7930 /* sdxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10614 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 7930 /* sdxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 10615 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10616 { Feature_InMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10617 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10618 { Feature_InMicroMips, 7936 /* seb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10619 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10620 { Feature_InMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10621 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10622 { Feature_InMicroMips, 7940 /* seh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10623 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7944 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10624 { Feature_InMicroMips|Feature_HasMips32r6, 7944 /* sel.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10625 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7950 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10626 { Feature_InMicroMips|Feature_HasMips32r6, 7950 /* sel.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10627 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7956 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10628 { Feature_InMicroMips|Feature_HasMips32r6, 7956 /* seleqz */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10629 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7956 /* seleqz */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 10630 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7963 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10631 { Feature_InMicroMips|Feature_HasMips32r6, 7963 /* seleqz.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10632 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7972 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10633 { Feature_InMicroMips|Feature_HasMips32r6, 7972 /* seleqz.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10634 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_HasMips32r6|Feature_NotInMicroMips, 7981 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10635 { Feature_InMicroMips|Feature_HasMips32r6, 7981 /* selnez */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10636 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips32r6, 7981 /* selnez */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 10637 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7988 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10638 { Feature_InMicroMips|Feature_HasMips32r6, 7988 /* selnez.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10639 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 7997 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10640 { Feature_InMicroMips|Feature_HasMips32r6, 7997 /* selnez.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10641 { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10642 { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10643 { Feature_HasCnMips, 8006 /* seq */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10644 { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10645 { Feature_NotCnMips, 8006 /* seq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10646 { Feature_HasCnMips, 8006 /* seq */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 10647 { Feature_HasCnMips, 8010 /* seqi */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10648 { Feature_HasCnMips, 8010 /* seqi */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10649 { Feature_HasStdEnc|Feature_NotInMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10650 { Feature_InMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10651 { Feature_HasStdEnc|Feature_NotInMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10652 { Feature_InMicroMips, 8015 /* sgt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10653 { Feature_HasStdEnc|Feature_NotInMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10654 { Feature_InMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10655 { Feature_HasStdEnc|Feature_NotInMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10656 { Feature_InMicroMips, 8019 /* sgtu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10657 { Feature_HasStdEnc|Feature_NotInMicroMips, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10658 { Feature_HasStdEnc|Feature_NotInMicroMips, 8024 /* sh */, MCK_Mem, 2 /* 1 */ }, 10659 { Feature_InMicroMips|Feature_HasMips32r6, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10660 { Feature_InMicroMips|Feature_HasMips32r6, 8024 /* sh */, MCK_Mem, 2 /* 1 */ }, 10661 { Feature_InMicroMips, 8024 /* sh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10662 { Feature_InMicroMips, 8024 /* sh */, MCK_Mem, 2 /* 1 */ }, 10663 { Feature_InMicroMips|Feature_NotMips32r6, 8027 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ }, 10664 { Feature_InMicroMips|Feature_NotMips32r6, 8027 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 10665 { Feature_InMicroMips|Feature_HasMips32r6, 8027 /* sh16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ }, 10666 { Feature_InMicroMips|Feature_HasMips32r6, 8027 /* sh16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 10667 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8032 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10668 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 8032 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10669 { Feature_InMicroMips|Feature_HasEVA, 8032 /* she */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10670 { Feature_InMicroMips|Feature_HasEVA, 8032 /* she */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10671 { Feature_HasStdEnc|Feature_HasMSA, 8036 /* shf.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10672 { Feature_HasStdEnc|Feature_HasMSA, 8042 /* shf.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10673 { Feature_HasStdEnc|Feature_HasMSA, 8048 /* shf.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10674 { Feature_InMicroMips|Feature_HasDSP, 8054 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10675 { Feature_HasDSP, 8054 /* shilo */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10676 { Feature_InMicroMips|Feature_HasDSP, 8060 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10677 { Feature_InMicroMips|Feature_HasDSP, 8060 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ }, 10678 { Feature_HasDSP, 8060 /* shilov */, MCK_ACC64DSPAsmReg, 1 /* 0 */ }, 10679 { Feature_HasDSP, 8060 /* shilov */, MCK_GPR32AsmReg, 2 /* 1 */ }, 10680 { Feature_InMicroMips|Feature_HasDSP, 8067 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10681 { Feature_HasDSP, 8067 /* shll.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10682 { Feature_InMicroMips|Feature_HasDSP, 8075 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10683 { Feature_HasDSP, 8075 /* shll.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10684 { Feature_InMicroMips|Feature_HasDSP, 8083 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10685 { Feature_HasDSP, 8083 /* shll_s.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10686 { Feature_InMicroMips|Feature_HasDSP, 8093 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10687 { Feature_HasDSP, 8093 /* shll_s.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10688 { Feature_InMicroMips|Feature_HasDSP, 8102 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10689 { Feature_HasDSP, 8102 /* shllv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10690 { Feature_InMicroMips|Feature_HasDSP, 8111 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10691 { Feature_HasDSP, 8111 /* shllv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10692 { Feature_InMicroMips|Feature_HasDSP, 8120 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10693 { Feature_HasDSP, 8120 /* shllv_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10694 { Feature_InMicroMips|Feature_HasDSP, 8131 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10695 { Feature_HasDSP, 8131 /* shllv_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10696 { Feature_InMicroMips|Feature_HasDSP, 8141 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10697 { Feature_HasDSP, 8141 /* shra.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10698 { Feature_InMicroMips|Feature_HasDSPR2, 8149 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10699 { Feature_HasDSPR2, 8149 /* shra.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10700 { Feature_InMicroMips|Feature_HasDSP, 8157 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10701 { Feature_HasDSP, 8157 /* shra_r.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10702 { Feature_InMicroMips|Feature_HasDSPR2, 8167 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10703 { Feature_HasDSPR2, 8167 /* shra_r.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10704 { Feature_InMicroMips|Feature_HasDSP, 8177 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10705 { Feature_HasDSP, 8177 /* shra_r.w */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10706 { Feature_InMicroMips|Feature_HasDSP, 8186 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10707 { Feature_HasDSP, 8186 /* shrav.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10708 { Feature_InMicroMips|Feature_HasDSPR2, 8195 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10709 { Feature_HasDSPR2, 8195 /* shrav.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10710 { Feature_InMicroMips|Feature_HasDSP, 8204 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10711 { Feature_HasDSP, 8204 /* shrav_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10712 { Feature_InMicroMips|Feature_HasDSPR2, 8215 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10713 { Feature_HasDSPR2, 8215 /* shrav_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10714 { Feature_InMicroMips|Feature_HasDSP, 8226 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10715 { Feature_HasDSP, 8226 /* shrav_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10716 { Feature_InMicroMips|Feature_HasDSPR2, 8236 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10717 { Feature_HasDSPR2, 8236 /* shrl.ph */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10718 { Feature_InMicroMips|Feature_HasDSP, 8244 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10719 { Feature_HasDSP, 8244 /* shrl.qb */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10720 { Feature_InMicroMips|Feature_HasDSPR2, 8252 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10721 { Feature_HasDSPR2, 8252 /* shrlv.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10722 { Feature_InMicroMips|Feature_HasDSP, 8261 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10723 { Feature_HasDSP, 8261 /* shrlv.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10724 { Feature_HasStdEnc|Feature_HasMSA, 8270 /* sld.b */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10725 { Feature_HasStdEnc|Feature_HasMSA, 8270 /* sld.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10726 { Feature_HasStdEnc|Feature_HasMSA, 8276 /* sld.d */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10727 { Feature_HasStdEnc|Feature_HasMSA, 8276 /* sld.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10728 { Feature_HasStdEnc|Feature_HasMSA, 8282 /* sld.h */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10729 { Feature_HasStdEnc|Feature_HasMSA, 8282 /* sld.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10730 { Feature_HasStdEnc|Feature_HasMSA, 8288 /* sld.w */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10731 { Feature_HasStdEnc|Feature_HasMSA, 8288 /* sld.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10732 { Feature_HasStdEnc|Feature_HasMSA, 8294 /* sldi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10733 { Feature_HasStdEnc|Feature_HasMSA, 8301 /* sldi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10734 { Feature_HasStdEnc|Feature_HasMSA, 8308 /* sldi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10735 { Feature_HasStdEnc|Feature_HasMSA, 8315 /* sldi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10736 { Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10737 { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10738 { Feature_HasStdEnc|Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10739 { Feature_InMicroMips|Feature_HasMips32r6, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10740 { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10741 { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10742 { Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10743 { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10744 { Feature_HasStdEnc|Feature_NotInMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10745 { Feature_InMicroMips|Feature_HasMips32r6, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10746 { Feature_InMicroMips, 8322 /* sll */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10747 { Feature_HasStdEnc|Feature_HasMSA, 8326 /* sll.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10748 { Feature_HasStdEnc|Feature_HasMSA, 8332 /* sll.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10749 { Feature_HasStdEnc|Feature_HasMSA, 8338 /* sll.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10750 { Feature_HasStdEnc|Feature_HasMSA, 8344 /* sll.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10751 { Feature_InMicroMips|Feature_NotMips32r6, 8350 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10752 { Feature_InMicroMips|Feature_HasMips32r6, 8350 /* sll16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10753 { Feature_HasStdEnc|Feature_HasMSA, 8356 /* slli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10754 { Feature_HasStdEnc|Feature_HasMSA, 8363 /* slli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10755 { Feature_HasStdEnc|Feature_HasMSA, 8370 /* slli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10756 { Feature_HasStdEnc|Feature_HasMSA, 8377 /* slli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10757 { Feature_HasStdEnc|Feature_NotInMicroMips, 8384 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10758 { Feature_InMicroMips, 8384 /* sllv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10759 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10760 { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10761 { Feature_IsGP64bit, 8389 /* slt */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10762 { Feature_HasStdEnc|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10763 { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10764 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10765 { Feature_InMicroMips, 8389 /* slt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10766 { Feature_IsGP64bit, 8389 /* slt */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10767 { Feature_HasStdEnc|Feature_NotInMicroMips, 8393 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10768 { Feature_InMicroMips, 8393 /* slti */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10769 { Feature_HasStdEnc|Feature_NotInMicroMips, 8398 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10770 { Feature_InMicroMips, 8398 /* sltiu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10771 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10772 { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10773 { Feature_IsGP64bit, 8404 /* sltu */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10774 { Feature_HasStdEnc|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10775 { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10776 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10777 { Feature_InMicroMips, 8404 /* sltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10778 { Feature_IsGP64bit, 8404 /* sltu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10779 { Feature_HasCnMips, 8409 /* sne */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10780 { Feature_HasCnMips, 8409 /* sne */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 10781 { Feature_HasCnMips, 8413 /* snei */, MCK_GPR64AsmReg, 1 /* 0 */ }, 10782 { Feature_HasCnMips, 8413 /* snei */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 10783 { Feature_HasStdEnc|Feature_HasMSA, 8418 /* splat.b */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10784 { Feature_HasStdEnc|Feature_HasMSA, 8418 /* splat.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10785 { Feature_HasStdEnc|Feature_HasMSA, 8426 /* splat.d */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10786 { Feature_HasStdEnc|Feature_HasMSA, 8426 /* splat.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10787 { Feature_HasStdEnc|Feature_HasMSA, 8434 /* splat.h */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10788 { Feature_HasStdEnc|Feature_HasMSA, 8434 /* splat.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10789 { Feature_HasStdEnc|Feature_HasMSA, 8442 /* splat.w */, MCK_GPR32AsmReg, 8 /* 3 */ }, 10790 { Feature_HasStdEnc|Feature_HasMSA, 8442 /* splat.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10791 { Feature_HasStdEnc|Feature_HasMSA, 8450 /* splati.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10792 { Feature_HasStdEnc|Feature_HasMSA, 8459 /* splati.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10793 { Feature_HasStdEnc|Feature_HasMSA, 8468 /* splati.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10794 { Feature_HasStdEnc|Feature_HasMSA, 8477 /* splati.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10795 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8486 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10796 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8486 /* sqrt.d */, MCK_AFGR64AsmReg, 3 /* 0, 1 */ }, 10797 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8486 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10798 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8486 /* sqrt.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 10799 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8493 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10800 { Feature_InMicroMips|Feature_IsNotSoftFloat, 8493 /* sqrt.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 10801 { Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10802 { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10803 { Feature_HasStdEnc|Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10804 { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10805 { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10806 { Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10807 { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10808 { Feature_HasStdEnc|Feature_NotInMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10809 { Feature_InMicroMips, 8500 /* sra */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10810 { Feature_HasStdEnc|Feature_HasMSA, 8504 /* sra.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10811 { Feature_HasStdEnc|Feature_HasMSA, 8510 /* sra.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10812 { Feature_HasStdEnc|Feature_HasMSA, 8516 /* sra.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10813 { Feature_HasStdEnc|Feature_HasMSA, 8522 /* sra.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10814 { Feature_HasStdEnc|Feature_HasMSA, 8528 /* srai.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10815 { Feature_HasStdEnc|Feature_HasMSA, 8535 /* srai.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10816 { Feature_HasStdEnc|Feature_HasMSA, 8542 /* srai.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10817 { Feature_HasStdEnc|Feature_HasMSA, 8549 /* srai.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10818 { Feature_HasStdEnc|Feature_HasMSA, 8556 /* srar.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10819 { Feature_HasStdEnc|Feature_HasMSA, 8563 /* srar.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10820 { Feature_HasStdEnc|Feature_HasMSA, 8570 /* srar.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10821 { Feature_HasStdEnc|Feature_HasMSA, 8577 /* srar.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10822 { Feature_HasStdEnc|Feature_HasMSA, 8584 /* srari.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10823 { Feature_HasStdEnc|Feature_HasMSA, 8592 /* srari.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10824 { Feature_HasStdEnc|Feature_HasMSA, 8600 /* srari.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10825 { Feature_HasStdEnc|Feature_HasMSA, 8608 /* srari.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10826 { Feature_HasStdEnc|Feature_NotInMicroMips, 8616 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10827 { Feature_InMicroMips, 8616 /* srav */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10828 { Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10829 { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10830 { Feature_HasStdEnc|Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10831 { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10832 { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10833 { Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10834 { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10835 { Feature_HasStdEnc|Feature_NotInMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10836 { Feature_InMicroMips, 8621 /* srl */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10837 { Feature_HasStdEnc|Feature_HasMSA, 8625 /* srl.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10838 { Feature_HasStdEnc|Feature_HasMSA, 8631 /* srl.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10839 { Feature_HasStdEnc|Feature_HasMSA, 8637 /* srl.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10840 { Feature_HasStdEnc|Feature_HasMSA, 8643 /* srl.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10841 { Feature_InMicroMips|Feature_NotMips32r6, 8649 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10842 { Feature_InMicroMips|Feature_HasMips32r6, 8649 /* srl16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 10843 { Feature_HasStdEnc|Feature_HasMSA, 8655 /* srli.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10844 { Feature_HasStdEnc|Feature_HasMSA, 8662 /* srli.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10845 { Feature_HasStdEnc|Feature_HasMSA, 8669 /* srli.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10846 { Feature_HasStdEnc|Feature_HasMSA, 8676 /* srli.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10847 { Feature_HasStdEnc|Feature_HasMSA, 8683 /* srlr.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10848 { Feature_HasStdEnc|Feature_HasMSA, 8690 /* srlr.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10849 { Feature_HasStdEnc|Feature_HasMSA, 8697 /* srlr.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10850 { Feature_HasStdEnc|Feature_HasMSA, 8704 /* srlr.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10851 { Feature_HasStdEnc|Feature_HasMSA, 8711 /* srlri.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10852 { Feature_HasStdEnc|Feature_HasMSA, 8719 /* srlri.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10853 { Feature_HasStdEnc|Feature_HasMSA, 8727 /* srlri.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10854 { Feature_HasStdEnc|Feature_HasMSA, 8735 /* srlri.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10855 { Feature_HasStdEnc|Feature_NotInMicroMips, 8743 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10856 { Feature_InMicroMips, 8743 /* srlv */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10857 { Feature_HasStdEnc|Feature_HasMSA, 8754 /* st.b */, MCK_MSA128AsmReg, 1 /* 0 */ }, 10858 { Feature_HasStdEnc|Feature_HasMSA, 8754 /* st.b */, MCK_MemOffsetSimm10, 2 /* 1 */ }, 10859 { Feature_HasStdEnc|Feature_HasMSA, 8759 /* st.d */, MCK_MSA128AsmReg, 1 /* 0 */ }, 10860 { Feature_HasStdEnc|Feature_HasMSA, 8759 /* st.d */, MCK_MemOffsetSimm10_3, 2 /* 1 */ }, 10861 { Feature_HasStdEnc|Feature_HasMSA, 8764 /* st.h */, MCK_MSA128AsmReg, 1 /* 0 */ }, 10862 { Feature_HasStdEnc|Feature_HasMSA, 8764 /* st.h */, MCK_MemOffsetSimm10_1, 2 /* 1 */ }, 10863 { Feature_HasStdEnc|Feature_HasMSA, 8769 /* st.w */, MCK_MSA128AsmReg, 1 /* 0 */ }, 10864 { Feature_HasStdEnc|Feature_HasMSA, 8769 /* st.w */, MCK_MemOffsetSimm10_2, 2 /* 1 */ }, 10865 { Feature_HasStdEnc|Feature_NotInMicroMips, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10866 { Feature_InMicroMips|Feature_NotMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10867 { Feature_InMicroMips|Feature_HasMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10868 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10869 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_InvNum, 2 /* 1 */ }, 10870 { Feature_HasStdEnc|Feature_NotInMicroMips, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10871 { Feature_InMicroMips|Feature_NotMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10872 { Feature_InMicroMips|Feature_HasMips32r6, 8774 /* sub */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10873 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10874 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6, 8774 /* sub */, MCK_InvNum, 4 /* 2 */ }, 10875 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8778 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 10876 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 8778 /* sub.d */, MCK_AFGR64AsmReg, 7 /* 0, 1, 2 */ }, 10877 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8778 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10878 { Feature_InMicroMips|Feature_IsFP64bit|Feature_IsNotSoftFloat, 8778 /* sub.d */, MCK_FGR64AsmReg, 7 /* 0, 1, 2 */ }, 10879 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10880 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10881 { Feature_InMicroMips|Feature_IsNotSoftFloat, 8784 /* sub.s */, MCK_FGR32AsmReg, 7 /* 0, 1, 2 */ }, 10882 { Feature_InMicroMips|Feature_HasDSP, 8790 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10883 { Feature_HasDSP, 8790 /* subq.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10884 { Feature_InMicroMips|Feature_HasDSP, 8798 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10885 { Feature_HasDSP, 8798 /* subq_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10886 { Feature_InMicroMips|Feature_HasDSP, 8808 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10887 { Feature_HasDSP, 8808 /* subq_s.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10888 { Feature_InMicroMips|Feature_HasDSPR2, 8817 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10889 { Feature_HasDSPR2, 8817 /* subqh.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10890 { Feature_InMicroMips|Feature_HasDSPR2, 8826 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10891 { Feature_HasDSPR2, 8826 /* subqh.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10892 { Feature_InMicroMips|Feature_HasDSPR2, 8834 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10893 { Feature_HasDSPR2, 8834 /* subqh_r.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10894 { Feature_InMicroMips|Feature_HasDSPR2, 8845 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10895 { Feature_HasDSPR2, 8845 /* subqh_r.w */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10896 { Feature_HasStdEnc|Feature_HasMSA, 8855 /* subs_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10897 { Feature_HasStdEnc|Feature_HasMSA, 8864 /* subs_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10898 { Feature_HasStdEnc|Feature_HasMSA, 8873 /* subs_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10899 { Feature_HasStdEnc|Feature_HasMSA, 8882 /* subs_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10900 { Feature_HasStdEnc|Feature_HasMSA, 8891 /* subs_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10901 { Feature_HasStdEnc|Feature_HasMSA, 8900 /* subs_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10902 { Feature_HasStdEnc|Feature_HasMSA, 8909 /* subs_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10903 { Feature_HasStdEnc|Feature_HasMSA, 8918 /* subs_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10904 { Feature_HasStdEnc|Feature_HasMSA, 8927 /* subsus_u.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10905 { Feature_HasStdEnc|Feature_HasMSA, 8938 /* subsus_u.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10906 { Feature_HasStdEnc|Feature_HasMSA, 8949 /* subsus_u.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10907 { Feature_HasStdEnc|Feature_HasMSA, 8960 /* subsus_u.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10908 { Feature_HasStdEnc|Feature_HasMSA, 8971 /* subsuu_s.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10909 { Feature_HasStdEnc|Feature_HasMSA, 8982 /* subsuu_s.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10910 { Feature_HasStdEnc|Feature_HasMSA, 8993 /* subsuu_s.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10911 { Feature_HasStdEnc|Feature_HasMSA, 9004 /* subsuu_s.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10912 { Feature_InMicroMips|Feature_HasMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10913 { Feature_HasStdEnc|Feature_NotInMicroMips, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10914 { Feature_InMicroMips|Feature_NotMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10915 { 0, 9015 /* subu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10916 { 0, 9015 /* subu */, MCK_InvNum, 2 /* 1 */ }, 10917 { Feature_InMicroMips|Feature_HasMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10918 { Feature_HasStdEnc|Feature_NotInMicroMips, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10919 { Feature_InMicroMips|Feature_NotMips32r6, 9015 /* subu */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10920 { 0, 9015 /* subu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 10921 { 0, 9015 /* subu */, MCK_InvNum, 4 /* 2 */ }, 10922 { Feature_InMicroMips|Feature_HasDSPR2, 9020 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10923 { Feature_HasDSPR2, 9020 /* subu.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10924 { Feature_InMicroMips|Feature_HasDSP, 9028 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10925 { Feature_HasDSP, 9028 /* subu.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10926 { Feature_InMicroMips|Feature_NotMips32r6, 9036 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ }, 10927 { Feature_InMicroMips|Feature_HasMips32r6, 9036 /* subu16 */, MCK_GPRMM16AsmReg, 7 /* 0, 1, 2 */ }, 10928 { Feature_InMicroMips|Feature_HasDSPR2, 9043 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10929 { Feature_HasDSPR2, 9043 /* subu_s.ph */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10930 { Feature_InMicroMips|Feature_HasDSP, 9053 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10931 { Feature_HasDSP, 9053 /* subu_s.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10932 { Feature_InMicroMips|Feature_HasDSPR2, 9063 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10933 { Feature_HasDSPR2, 9063 /* subuh.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10934 { Feature_InMicroMips|Feature_HasDSPR2, 9072 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10935 { Feature_HasDSPR2, 9072 /* subuh_r.qb */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 10936 { Feature_HasStdEnc|Feature_HasMSA, 9083 /* subv.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10937 { Feature_HasStdEnc|Feature_HasMSA, 9090 /* subv.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10938 { Feature_HasStdEnc|Feature_HasMSA, 9097 /* subv.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10939 { Feature_HasStdEnc|Feature_HasMSA, 9104 /* subv.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 10940 { Feature_HasStdEnc|Feature_HasMSA, 9111 /* subvi.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10941 { Feature_HasStdEnc|Feature_HasMSA, 9119 /* subvi.d */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10942 { Feature_HasStdEnc|Feature_HasMSA, 9127 /* subvi.h */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10943 { Feature_HasStdEnc|Feature_HasMSA, 9135 /* subvi.w */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 10944 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_AFGR64AsmReg, 1 /* 0 */ }, 10945 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 10946 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10947 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips5_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 10948 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9143 /* suxc1 */, MCK_FGR64AsmReg, 1 /* 0 */ }, 10949 { Feature_InMicroMips|Feature_IsFP64bit|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9143 /* suxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 10950 { Feature_InMicroMips|Feature_NotMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10951 { Feature_InMicroMips|Feature_NotMips32r6, 9149 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ }, 10952 { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10953 { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_MicroMipsMemSP, 2 /* 1 */ }, 10954 { Feature_HasStdEnc|Feature_NotInMicroMips, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10955 { Feature_HasStdEnc|Feature_NotInMicroMips, 9149 /* sw */, MCK_Mem, 2 /* 1 */ }, 10956 { Feature_NotInMips16Mode|Feature_HasDSP, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10957 { Feature_NotInMips16Mode|Feature_HasDSP, 9149 /* sw */, MCK_Mem, 2 /* 1 */ }, 10958 { Feature_InMicroMips|Feature_HasDSP, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10959 { Feature_InMicroMips|Feature_HasDSP, 9149 /* sw */, MCK_Mem, 2 /* 1 */ }, 10960 { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10961 { Feature_InMicroMips|Feature_HasMips32r6, 9149 /* sw */, MCK_Mem, 2 /* 1 */ }, 10962 { Feature_InMicroMips, 9149 /* sw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10963 { Feature_InMicroMips, 9149 /* sw */, MCK_Mem, 2 /* 1 */ }, 10964 { Feature_InMicroMips|Feature_NotMips32r6, 9152 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ }, 10965 { Feature_InMicroMips|Feature_NotMips32r6, 9152 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 10966 { Feature_InMicroMips|Feature_HasMips32r6, 9152 /* sw16 */, MCK_GPRMM16AsmRegZero, 1 /* 0 */ }, 10967 { Feature_InMicroMips|Feature_HasMips32r6, 9152 /* sw16 */, MCK_MicroMipsMem, 2 /* 1 */ }, 10968 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9157 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 10969 { Feature_HasStdEnc|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9157 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10970 { Feature_InMicroMips|Feature_IsNotSoftFloat, 9157 /* swc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 10971 { Feature_InMicroMips|Feature_IsNotSoftFloat, 9157 /* swc1 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10972 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 10973 { Feature_HasStdEnc|Feature_HasMips32r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 10974 { Feature_InMicroMips|Feature_HasMips32r6, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 10975 { Feature_InMicroMips|Feature_HasMips32r6, 9162 /* swc2 */, MCK_MemOffsetSimm11, 2 /* 1 */ }, 10976 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_COP2AsmReg, 1 /* 0 */ }, 10977 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9162 /* swc2 */, MCK_MemOffsetSimm16, 2 /* 1 */ }, 10978 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9167 /* swc3 */, MCK_COP3AsmReg, 1 /* 0 */ }, 10979 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotCnMips|Feature_NotInMicroMips, 9167 /* swc3 */, MCK_Mem, 2 /* 1 */ }, 10980 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9172 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10981 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_HasEVA|Feature_NotInMicroMips, 9172 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10982 { Feature_InMicroMips|Feature_HasEVA, 9172 /* swe */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10983 { Feature_InMicroMips|Feature_HasEVA, 9172 /* swe */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10984 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9176 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10985 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9176 /* swl */, MCK_Mem, 2 /* 1 */ }, 10986 { Feature_InMicroMips|Feature_NotMips32r6, 9176 /* swl */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10987 { Feature_InMicroMips|Feature_NotMips32r6, 9176 /* swl */, MCK_Mem, 2 /* 1 */ }, 10988 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9180 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10989 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9180 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10990 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9180 /* swle */, MCK_GPR32AsmReg, 1 /* 0 */ }, 10991 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9180 /* swle */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 10992 { Feature_InMicroMips, 9185 /* swm */, MCK_Mem, 2 /* 1 */ }, 10993 { Feature_InMicroMips, 9185 /* swm */, MCK_RegList, 1 /* 0 */ }, 10994 { Feature_InMicroMips|Feature_NotMips32r6, 9189 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ }, 10995 { Feature_InMicroMips|Feature_NotMips32r6, 9189 /* swm16 */, MCK_RegList16, 1 /* 0 */ }, 10996 { Feature_InMicroMips|Feature_HasMips32r6, 9189 /* swm16 */, MCK_MemOffsetUimm4, 2 /* 1 */ }, 10997 { Feature_InMicroMips|Feature_HasMips32r6, 9189 /* swm16 */, MCK_RegList16, 1 /* 0 */ }, 10998 { Feature_InMicroMips, 9195 /* swm32 */, MCK_Mem, 2 /* 1 */ }, 10999 { Feature_InMicroMips, 9195 /* swm32 */, MCK_RegList, 1 /* 0 */ }, 11000 { Feature_InMicroMips, 9201 /* swp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11001 { Feature_InMicroMips, 9201 /* swp */, MCK_MemOffsetSimm12, 2 /* 1 */ }, 11002 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9205 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11003 { Feature_HasStdEnc|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9205 /* swr */, MCK_Mem, 2 /* 1 */ }, 11004 { Feature_InMicroMips|Feature_NotMips32r6, 9205 /* swr */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11005 { Feature_InMicroMips|Feature_NotMips32r6, 9205 /* swr */, MCK_Mem, 2 /* 1 */ }, 11006 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9209 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11007 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_HasEVA|Feature_NotInMicroMips, 9209 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 11008 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9209 /* swre */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11009 { Feature_InMicroMips|Feature_NotMips32r6|Feature_HasEVA, 9209 /* swre */, MCK_MemOffsetSimm9, 2 /* 1 */ }, 11010 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11011 { Feature_HasStdEnc|Feature_HasMips4_32r2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 11012 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11013 { Feature_InMicroMips|Feature_NotMips32r6|Feature_IsNotSoftFloat, 9214 /* swxc1 */, MCK_GPR32AsmReg, 10 /* 1, 3 */ }, 11014 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ }, 11015 { Feature_InMicroMips|Feature_NotMips32r6, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ }, 11016 { Feature_InMicroMips|Feature_HasMips32r6, 9225 /* synci */, MCK_MemOffsetSimm16, 1 /* 0 */ }, 11017 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11018 { Feature_InMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11019 { Feature_InMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11020 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9269 /* teq */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11021 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9273 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11022 { Feature_InMicroMips|Feature_NotMips32r6, 9273 /* teqi */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11023 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11024 { Feature_InMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11025 { Feature_InMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11026 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9278 /* tge */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11027 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9282 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11028 { Feature_InMicroMips|Feature_NotMips32r6, 9282 /* tgei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11029 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9287 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11030 { Feature_InMicroMips|Feature_NotMips32r6, 9287 /* tgeiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11031 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11032 { Feature_InMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11033 { Feature_InMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11034 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9293 /* tgeu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11035 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11036 { Feature_InMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11037 { Feature_InMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11038 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9378 /* tlt */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11039 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9382 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11040 { Feature_InMicroMips|Feature_NotMips32r6, 9382 /* tlti */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11041 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9387 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11042 { Feature_InMicroMips|Feature_NotMips32r6, 9387 /* tltiu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11043 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11044 { Feature_InMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11045 { Feature_InMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11046 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9393 /* tltu */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11047 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11048 { Feature_InMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11049 { Feature_InMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11050 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotInMicroMips, 9398 /* tne */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11051 { Feature_HasStdEnc|Feature_HasMips2|Feature_NotMips32r6|Feature_NotMips64r6|Feature_NotInMicroMips, 9402 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11052 { Feature_InMicroMips|Feature_NotMips32r6, 9402 /* tnei */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11053 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips3_32|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9407 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 11054 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9407 /* trunc.l.d */, MCK_FGR64AsmReg, 3 /* 0, 1 */ }, 11055 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9417 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 11056 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9417 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 11057 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9417 /* trunc.l.s */, MCK_FGR32AsmReg, 2 /* 1 */ }, 11058 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9417 /* trunc.l.s */, MCK_FGR64AsmReg, 1 /* 0 */ }, 11059 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 11060 { Feature_HasStdEnc|Feature_NotFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11061 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 11062 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11063 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 11064 { Feature_InMicroMips|Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11065 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11066 { Feature_HasStdEnc|Feature_IsFP64bit|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9427 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 11067 { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_AFGR64AsmReg, 2 /* 1 */ }, 11068 { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11069 { Feature_NotFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 11070 { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR32AsmReg, 1 /* 0 */ }, 11071 { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_FGR64AsmReg, 2 /* 1 */ }, 11072 { Feature_IsFP64bit|Feature_IsNotSoftFloat, 9427 /* trunc.w.d */, MCK_GPR32AsmReg, 4 /* 2 */ }, 11073 { Feature_HasStdEnc|Feature_HasMips2|Feature_IsNotSoftFloat|Feature_NotInMicroMips, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 11074 { Feature_InMicroMips|Feature_HasMips32r6|Feature_IsNotSoftFloat, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 11075 { Feature_InMicroMips|Feature_IsNotSoftFloat, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 11076 { 0, 9437 /* trunc.w.s */, MCK_FGR32AsmReg, 3 /* 0, 1 */ }, 11077 { 0, 9437 /* trunc.w.s */, MCK_GPR32AsmReg, 4 /* 2 */ }, 11078 { 0, 9447 /* ulh */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11079 { 0, 9447 /* ulh */, MCK_Mem, 2 /* 1 */ }, 11080 { 0, 9451 /* ulhu */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11081 { 0, 9451 /* ulhu */, MCK_Mem, 2 /* 1 */ }, 11082 { 0, 9456 /* ulw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11083 { 0, 9456 /* ulw */, MCK_Mem, 2 /* 1 */ }, 11084 { 0, 9460 /* ush */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11085 { 0, 9460 /* ush */, MCK_Mem, 2 /* 1 */ }, 11086 { 0, 9464 /* usw */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11087 { 0, 9464 /* usw */, MCK_Mem, 2 /* 1 */ }, 11088 { Feature_HasCnMips, 9468 /* v3mulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 11089 { Feature_HasCnMips, 9468 /* v3mulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 11090 { Feature_HasCnMips, 9475 /* vmm0 */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 11091 { Feature_HasCnMips, 9475 /* vmm0 */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 11092 { Feature_HasCnMips, 9480 /* vmulu */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 11093 { Feature_HasCnMips, 9480 /* vmulu */, MCK_GPR64AsmReg, 7 /* 0, 1, 2 */ }, 11094 { Feature_HasStdEnc|Feature_HasMSA, 9486 /* vshf.b */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 11095 { Feature_HasStdEnc|Feature_HasMSA, 9493 /* vshf.d */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 11096 { Feature_HasStdEnc|Feature_HasMSA, 9500 /* vshf.h */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 11097 { Feature_HasStdEnc|Feature_HasMSA, 9507 /* vshf.w */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 11098 { Feature_HasDSP|Feature_NotInMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11099 { Feature_HasDSP|Feature_InMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11100 { Feature_InMicroMips|Feature_HasDSP, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11101 { Feature_HasDSP|Feature_NotInMicroMips, 9519 /* wrdsp */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11102 { Feature_InMicroMips|Feature_HasMips32r6, 9525 /* wrpgpr */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11103 { Feature_HasStdEnc|Feature_HasMips32r2|Feature_NotInMicroMips, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11104 { Feature_InMicroMips|Feature_HasMips32r6, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11105 { Feature_InMicroMips, 9532 /* wsbh */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11106 { Feature_HasStdEnc|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11107 { Feature_InMicroMips|Feature_NotMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11108 { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11109 { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11110 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11111 { Feature_InMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11112 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR64AsmReg, 1 /* 0 */ }, 11113 { Feature_HasStdEnc|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 11114 { Feature_InMicroMips|Feature_NotMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 11115 { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 7 /* 0, 1, 2 */ }, 11116 { Feature_InMicroMips|Feature_HasMips32r6, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11117 { Feature_HasStdEnc|Feature_IsGP32bit|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11118 { Feature_InMicroMips, 9537 /* xor */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11119 { Feature_HasStdEnc|Feature_IsGP64bit|Feature_HasMips3|Feature_NotInMicroMips, 9537 /* xor */, MCK_GPR64AsmReg, 3 /* 0, 1 */ }, 11120 { Feature_HasStdEnc|Feature_HasMSA, 9541 /* xor.v */, MCK_MSA128AsmReg, 7 /* 0, 1, 2 */ }, 11121 { Feature_InMicroMips|Feature_NotMips32r6, 9547 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 11122 { Feature_InMicroMips|Feature_HasMips32r6, 9547 /* xor16 */, MCK_GPRMM16AsmReg, 3 /* 0, 1 */ }, 11123 { Feature_InMicroMips|Feature_HasMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11124 { Feature_HasStdEnc|Feature_NotInMicroMips, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11125 { Feature_InMicroMips|Feature_NotMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11126 { Feature_InMicroMips|Feature_HasMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11127 { Feature_HasStdEnc|Feature_NotInMicroMips, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11128 { Feature_InMicroMips|Feature_NotMips32r6, 9553 /* xori */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11129 { Feature_HasStdEnc|Feature_HasMSA, 9558 /* xori.b */, MCK_MSA128AsmReg, 3 /* 0, 1 */ }, 11130 { Feature_HasMT|Feature_NotInMicroMips, 9565 /* yield */, MCK_GPR32AsmReg, 1 /* 0 */ }, 11131 { Feature_HasStdEnc|Feature_HasMT|Feature_NotInMicroMips, 9565 /* yield */, MCK_GPR32AsmReg, 3 /* 0, 1 */ }, 11132}; 11133 11134OperandMatchResultTy MipsAsmParser:: 11135tryCustomParseOperand(OperandVector &Operands, 11136 unsigned MCK) { 11137 11138 switch(MCK) { 11139 case MCK_ACC64DSPAsmReg: 11140 return parseAnyRegister(Operands); 11141 case MCK_AFGR64AsmReg: 11142 return parseAnyRegister(Operands); 11143 case MCK_CCRAsmReg: 11144 return parseAnyRegister(Operands); 11145 case MCK_COP0AsmReg: 11146 return parseAnyRegister(Operands); 11147 case MCK_COP2AsmReg: 11148 return parseAnyRegister(Operands); 11149 case MCK_COP3AsmReg: 11150 return parseAnyRegister(Operands); 11151 case MCK_FCCAsmReg: 11152 return parseAnyRegister(Operands); 11153 case MCK_FGR32AsmReg: 11154 return parseAnyRegister(Operands); 11155 case MCK_FGR64AsmReg: 11156 return parseAnyRegister(Operands); 11157 case MCK_FGRH32AsmReg: 11158 return parseAnyRegister(Operands); 11159 case MCK_GPR32AsmReg: 11160 return parseAnyRegister(Operands); 11161 case MCK_GPR32NonZeroAsmReg: 11162 return parseAnyRegister(Operands); 11163 case MCK_GPR32ZeroAsmReg: 11164 return parseAnyRegister(Operands); 11165 case MCK_GPR64AsmReg: 11166 return parseAnyRegister(Operands); 11167 case MCK_GPRMM16AsmReg: 11168 return parseAnyRegister(Operands); 11169 case MCK_GPRMM16AsmRegMoveP: 11170 return parseAnyRegister(Operands); 11171 case MCK_GPRMM16AsmRegZero: 11172 return parseAnyRegister(Operands); 11173 case MCK_HI32DSPAsmReg: 11174 return parseAnyRegister(Operands); 11175 case MCK_HWRegsAsmReg: 11176 return parseAnyRegister(Operands); 11177 case MCK_LO32DSPAsmReg: 11178 return parseAnyRegister(Operands); 11179 case MCK_MSA128AsmReg: 11180 return parseAnyRegister(Operands); 11181 case MCK_MSACtrlAsmReg: 11182 return parseAnyRegister(Operands); 11183 case MCK_MicroMipsMemGP: 11184 return parseMemOperand(Operands); 11185 case MCK_MicroMipsMem: 11186 return parseMemOperand(Operands); 11187 case MCK_MicroMipsMemSP: 11188 return parseMemOperand(Operands); 11189 case MCK_InvNum: 11190 return parseInvNum(Operands); 11191 case MCK_JumpTarget: 11192 return parseJumpTarget(Operands); 11193 case MCK_MemOffsetSimm10: 11194 return parseMemOperand(Operands); 11195 case MCK_MemOffsetSimm10_1: 11196 return parseMemOperand(Operands); 11197 case MCK_MemOffsetSimm10_2: 11198 return parseMemOperand(Operands); 11199 case MCK_MemOffsetSimm10_3: 11200 return parseMemOperand(Operands); 11201 case MCK_MemOffsetSimm11: 11202 return parseMemOperand(Operands); 11203 case MCK_MemOffsetSimm12: 11204 return parseMemOperand(Operands); 11205 case MCK_MemOffsetSimm16: 11206 return parseMemOperand(Operands); 11207 case MCK_MemOffsetSimm9: 11208 return parseMemOperand(Operands); 11209 case MCK_MemOffsetSimmPtr: 11210 return parseMemOperand(Operands); 11211 case MCK_MemOffsetUimm4: 11212 return parseMemOperand(Operands); 11213 case MCK_Mem: 11214 return parseMemOperand(Operands); 11215 case MCK_MovePRegPair: 11216 return parseMovePRegPair(Operands); 11217 case MCK_RegList16: 11218 return parseRegisterList(Operands); 11219 case MCK_RegList: 11220 return parseRegisterList(Operands); 11221 case MCK_StrictlyAFGR64AsmReg: 11222 return parseAnyRegister(Operands); 11223 case MCK_StrictlyFGR32AsmReg: 11224 return parseAnyRegister(Operands); 11225 case MCK_StrictlyFGR64AsmReg: 11226 return parseAnyRegister(Operands); 11227 default: 11228 return MatchOperand_NoMatch; 11229 } 11230 return MatchOperand_NoMatch; 11231} 11232 11233OperandMatchResultTy MipsAsmParser:: 11234MatchOperandParserImpl(OperandVector &Operands, 11235 StringRef Mnemonic, 11236 bool ParseForAllFeatures) { 11237 // Get the current feature set. 11238 uint64_t AvailableFeatures = getAvailableFeatures(); 11239 11240 // Get the next operand index. 11241 unsigned NextOpNum = Operands.size() - 1; 11242 // Search the table. 11243 auto MnemonicRange = 11244 std::equal_range(std::begin(OperandMatchTable), std::end(OperandMatchTable), 11245 Mnemonic, LessOpcodeOperand()); 11246 11247 if (MnemonicRange.first == MnemonicRange.second) 11248 return MatchOperand_NoMatch; 11249 11250 for (const OperandMatchEntry *it = MnemonicRange.first, 11251 *ie = MnemonicRange.second; it != ie; ++it) { 11252 // equal_range guarantees that instruction mnemonic matches. 11253 assert(Mnemonic == it->getMnemonic()); 11254 11255 // check if the available features match 11256 if (!ParseForAllFeatures && (AvailableFeatures & it->RequiredFeatures) != it->RequiredFeatures) 11257 continue; 11258 11259 // check if the operand in question has a custom parser. 11260 if (!(it->OperandMask & (1 << NextOpNum))) 11261 continue; 11262 11263 // call custom parse method to handle the operand 11264 OperandMatchResultTy Result = tryCustomParseOperand(Operands, it->Class); 11265 if (Result != MatchOperand_NoMatch) 11266 return Result; 11267 } 11268 11269 // Okay, we had no match. 11270 return MatchOperand_NoMatch; 11271} 11272 11273#endif // GET_MATCHER_IMPLEMENTATION 11274 11275 11276#ifdef GET_MNEMONIC_SPELL_CHECKER 11277#undef GET_MNEMONIC_SPELL_CHECKER 11278 11279static std::string MipsMnemonicSpellCheck(StringRef S, uint64_t FBS, unsigned VariantID) { 11280 const unsigned MaxEditDist = 2; 11281 std::vector<StringRef> Candidates; 11282 StringRef Prev = ""; 11283 11284 // Find the appropriate table for this asm variant. 11285 const MatchEntry *Start, *End; 11286 switch (VariantID) { 11287 default: llvm_unreachable("invalid variant!"); 11288 case 0: Start = std::begin(MatchTable0); End = std::end(MatchTable0); break; 11289 } 11290 11291 for (auto I = Start; I < End; I++) { 11292 // Ignore unsupported instructions. 11293 if ((FBS & I->RequiredFeatures) != I->RequiredFeatures) 11294 continue; 11295 11296 StringRef T = I->getMnemonic(); 11297 // Avoid recomputing the edit distance for the same string. 11298 if (T.equals(Prev)) 11299 continue; 11300 11301 Prev = T; 11302 unsigned Dist = S.edit_distance(T, false, MaxEditDist); 11303 if (Dist <= MaxEditDist) 11304 Candidates.push_back(T); 11305 } 11306 11307 if (Candidates.empty()) 11308 return ""; 11309 11310 std::string Res = ", did you mean: "; 11311 unsigned i = 0; 11312 for( ; i < Candidates.size() - 1; i++) 11313 Res += Candidates[i].str() + ", "; 11314 return Res + Candidates[i].str() + "?"; 11315} 11316 11317#endif // GET_MNEMONIC_SPELL_CHECKER 11318 11319