Searched refs:SALU (Results 1 – 25 of 26) sorted by relevance
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 22 field bits<1> SALU = 0;
58 let TSFlags{3} = SALU;
288 let SALU = 1;
299 let SALU = 1;
311 let SALU = 1;
325 let SALU = 1;
337 let SALU = 1;
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| D | SIInstrInfo.h | 184 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
188 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
360 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
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| D | SIDefines.h | 19 SALU = 1 << 3, enumerator
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| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIInstructions.td | 1923 let usesCustomInserter = 1, SALU = 1 in {
1926 } // End let usesCustomInserter = 1, SALU = 1
1940 let SALU = 1;
2009 let SALU = 1;
2020 let SALU = 1;
2030 let SALU = 1;
2122 let SALU = 1;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 28 field bit SALU = 0;
31 // SALU instruction formats.
125 let TSFlags{0} = SALU;
202 let SALU = 1;
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| D | SIInstrInfo.h | 301 return MI.getDesc().TSFlags & SIInstrFlags::SALU; in isSALU()
305 return get(Opcode).TSFlags & SIInstrFlags::SALU; in isSALU()
535 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
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| D | SISchedule.td | 45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
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| D | SIDefines.h | 22 SALU = 1 << 0, enumerator
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| D | SIInstructions.td | 167 let usesCustomInserter = 1, SALU = 1 in {
170 } // End let usesCustomInserter = 1, SALU = 1
174 let SALU = 1;
181 let SALU = 1;
189 let SALU = 1;
334 let SALU = 1;
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| D | SOPInstructions.td | 48 let SALU = 1;
280 let SALU = 1;
524 let SALU = 1;
715 let SALU = 1;
813 let SALU = 1;
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | split-scalar-i64-add.ll | 6 ; SALU, but the upper half does not. The addc expects the carry bit
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| D | sgpr-control-flow.ll | 4 ; Most SALU instructions ignore control flow, so we need to make sure
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| D | bfi_int.ll | 118 ; FIXME: Should leave as 64-bit SALU ops
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| D | uniform-cfg.ll | 119 ; be selected for the SALU and then later moved to the VALU.
144 ; be selected for the SALU and then later moved to the VALU.
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| D | break-smem-soft-clauses.mir | 291 # Regular SALU instruction breaks clause, no nop needed
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| D | xor.ll | 152 ; use an SALU instruction for this.
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| D | ctpop16.ll | 305 ; FIXME: We currently disallow SALU instructions in all branches,
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| D | break-vmem-soft-clauses.mir | 318 # Regular SALU instruction breaks clause, no nop needed
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | sgpr-control-flow.ll | 4 ; Most SALU instructions ignore control flow, so we need to make sure
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| D | split-scalar-i64-add.ll | 6 ; SALU, but the upper half does not. The addc expects the carry bit
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| D | uniform-cfg.ll | 121 ; be selected for the SALU and then later moved to the VALU.
146 ; be selected for the SALU and then later moved to the VALU.
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| D | xor.ll | 152 ; use an SALU instruction for this.
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| D | ctpop.ll | 271 ; FIXME: We currently disallow SALU instructions in all branches,
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| D | and.ll | 59 ; FIXME: We should really duplicate the constant so that the SALU use
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