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Searched refs:SI_CONTEXT_REG_OFFSET (Results 1 – 5 of 5) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_cs.h44 assert(reg < SI_CONTEXT_REG_OFFSET); in radeon_set_config_reg_seq()
59 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_seq()
63 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
77 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_idx()
80 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h116 assert(reg < SI_CONTEXT_REG_OFFSET); in radeon_set_config_reg_seq()
130 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_seq()
133 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2); in radeon_set_context_reg_seq()
146 assert(reg >= SI_CONTEXT_REG_OFFSET); in radeon_set_context_reg_idx()
149 radeon_emit(cs, (reg - SI_CONTEXT_REG_OFFSET) >> 2 | (idx << 28)); in radeon_set_context_reg_idx()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_pm4.c62 } else if (reg >= SI_CONTEXT_REG_OFFSET && reg < SI_CONTEXT_REG_END) { in si_pm4_set_reg()
64 reg -= SI_CONTEXT_REG_OFFSET; in si_pm4_set_reg()
/external/mesa3d/src/amd/common/
Dac_debug.c249 ac_parse_set_reg_packet(f, count, SI_CONTEXT_REG_OFFSET, ib); in ac_parse_packet3()
Dsid.h32 #define SI_CONTEXT_REG_OFFSET 0x00028000 macro