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Searched refs:SLOT2 (Results 1 – 17 of 17) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepIICScalar.td177 InstrItinData <tc_00afc57e, [InstrStage<1, [SLOT2, SLOT3]>]>,
180 InstrItinData <tc_038a1342, [InstrStage<1, [SLOT2, SLOT3]>]>,
181 InstrItinData <tc_04c9decc, [InstrStage<1, [SLOT2, SLOT3]>]>,
186 InstrItinData <tc_10b97e27, [InstrStage<1, [SLOT2]>]>,
188 InstrItinData <tc_14cd4cfa, [InstrStage<1, [SLOT2]>]>,
189 InstrItinData <tc_15411484, [InstrStage<1, [SLOT2]>]>,
190 InstrItinData <tc_16d0d8d5, [InstrStage<1, [SLOT2, SLOT3]>]>,
191 InstrItinData <tc_181af5d0, [InstrStage<1, [SLOT2]>]>,
192 InstrItinData <tc_1853ea6d, [InstrStage<1, [SLOT2, SLOT3]>]>,
194 InstrItinData <tc_1b9c9ee5, [InstrStage<1, [SLOT2, SLOT3]>]>,
[all …]
DHexagonDepIICHVX.td109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
114 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
124 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
148 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
153 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
158 [InstrStage<1, [SLOT2, SLOT3], 0>,
163 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
168 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
191 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
201 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3], 0>,
[all …]
DHexagonScheduleV55.td13 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
15 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
16 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
35 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonScheduleV4.td15 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
16 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
17 InstrStage<1, [SLOT2, SLOT3]>]>,
33 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
DHexagonIICScalar.td16 InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
18 InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
19 InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
DHexagonScheduleV60.td21 // | SLOT2 | XTYPE ALU32 J JR |
65 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonIICHVX.td16 [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
DHexagonScheduleV62.td21 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonScheduleV65.td23 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
DHexagonSchedule.td16 def SLOT2 : FuncUnit;
/external/llvm/lib/Target/Hexagon/
DHexagonScheduleV55.td21 // | SLOT2 | XTYPE ALU32 J JR |
43 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
46 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
48 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
50 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
52 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
54 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
56 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
59 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
60 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
[all …]
DHexagonScheduleV60.td71 // | SLOT2 | XTYPE ALU32 J JR |
107 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
112 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
114 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
118 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
120 [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
122 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
125 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
126 InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
[all …]
DHexagonScheduleV4.td21 // | SLOT2 | XTYPE ALU32 J JR |
29 def SLOT2 : FuncUnit;
100 ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
103 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
105 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
107 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
109 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
111 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
113 [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
116 InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dbr-cond-not-merge.ll69 ; NOOPT: str w1, [sp, #[[SLOT2:[0-9]+]]]
74 ; NOOPT: ldr [[R3:w[0-9]+]], [sp, #[[SLOT2]]]
Dswifterror.ll181 ; CHECK-O0: str x0, [sp, [[SLOT2:#[0-9]+]]]
188 ; CHECK-O0: str x0, [sp, [[SLOT2]]]
190 ; CHECK-O0: ldr x0, [sp, [[SLOT2]]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dswifterror.ll756 ; CHECK-O0: movq %rax, [[SLOT2:[-a-z0-9\(\)\%]*]]
757 ; CHECK-O0: movq [[SLOT2]], %r12
776 ; CHECK-O0: movq %rax, [[SLOT2:[-a-z0-9\(\)\%]*]]
777 ; CHECK-O0: movq [[SLOT2]], %r12
803 ; CHECK-O0: movq %rax, [[SLOT2:[-a-z0-9\(\)\%]*]]
804 ; CHECK-O0: movq [[SLOT2]], %r12
/external/python/cpython2/Objects/
Dtypeobject.c5108 #define SLOT2(FUNCNAME, OPSTR, ARG1TYPE, ARG2TYPE, ARGCODES) \ macro