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Searched refs:SMLAL (Results 1 – 25 of 60) sorted by relevance

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/external/libxaac/decoder/armv7/
Dixheaacd_esbr_radix4bfly.s88 SMLAL r14, r8, r11, r4
95 SMLAL r14, r8, r11, r5
102 SMLAL r10, r8, r12, r11
110 SMLAL r10, r8, r12, r4
117 SMLAL r11, r12, r6, r4
124 SMLAL r10, r7, r6, r14
Dixheaacd_tns_ar_filter_fixed.s81 SMLAL r2 , r11, r10, r9
377 SMLAL r2 , r11, r10, r9
/external/libxaac/decoder/armv8/
Dixheaacd_overlap_add2.s83 SMLAL V23.4S, V1.4H, V2.4H
106 SMLAL V19.4S, V9.4H, V10.4H
110 SMLAL V23.4S, V1.4H, V2.4H
149 SMLAL V19.4S, V9.4H, V10.4H
201 SMLAL V23.4S, V0.4H, V3.4H
216 SMLAL V23.4S, V0.4H, V3.4H
254 SMLAL V19.4S, V8.4H, V11.4H
259 SMLAL V23.4S, V0.4H, V3.4H
293 SMLAL V19.4S, V8.4H, V11.4H
Dixheaacd_overlap_add1.s99 SMLAL V15.4S, V6.4H, V2.4H
116 SMLAL V12.4S, V30.4H, V3.4H
161 SMLAL V15.4S, V6.4H, V2.4H
163 SMLAL V12.4S, V0.4H, V3.4H
215 SMLAL V15.4S, V6.4H, V2.4H
219 SMLAL V12.4S, V0.4H, V3.4H
283 SMLAL V15.4S, V6.4H, V2.4H
285 SMLAL V12.4S, V0.4H, V3.4H
Dixheaacd_sbr_imdct_using_fft.s640 SMLAL V12.4S, V18.4H, V20.4H
657 SMLAL V14.4S, V28.4H, V22.4H
662 SMLAL V11.4S, V17.4H, V20.4H
670 SMLAL V12.4S, V17.4H, V21.4H
671 SMLAL V12.4S, V19.4H, V20.4H
674 SMLAL V5.4S, V2.4H, V24.4H
676 SMLAL V13.4S, V27.4H, V22.4H
679 SMLAL V14.4S, V27.4H, V23.4H
680 SMLAL V14.4S, V29.4H, V22.4H
682 SMLAL V15.4S, V1.4H, V24.4H
[all …]
Dixheaacd_imdct_using_fft.s668 SMLAL v12.4S, v18.4H, v20.4H
685 SMLAL v14.4S, v28.4H, v22.4H
690 SMLAL v11.4S, v17.4H, v20.4H
698 SMLAL v12.4S, v17.4H, v21.4H
699 SMLAL v12.4S, v19.4H, v20.4H
702 SMLAL v5.4S, v2.4H, v24.4H
704 SMLAL v13.4S, v27.4H, v22.4H
707 SMLAL v14.4S, v27.4H, v23.4H
708 SMLAL v14.4S, v29.4H, v22.4H
710 SMLAL v15.4S, v1.4H, v24.4H
[all …]
/external/tremolo/Tremolo/
DmdctARM.s329 SMLAL r8, r9, r6, r10 @ (r8, r9) += s0*T[0]
335 SMLAL r8, r12,r6, r11 @ (r8, r12) -= s0*T[1]
353 SMLAL r8, r9, r7, r11 @ (r8, r9) += s2*T[0]
359 SMLAL r8, r12,r6, r11 @ (r8, r12) -= s0*T[0]
389 SMLAL r14,r12,r9, r10 @ (r14,r12) += ro2*T[0]
395 SMLAL r14,r3, r8, r10 @ (r14,r3) -= ro0*T[0]
406 SMLAL r14,r12,r7, r11 @ (r14,r12) += ri2*T[1]
412 SMLAL r14,r3, r6, r11 @ (r14,r3) -= ri0*T[1]
502 SMLAL r4, r3, r11,r10 @ (r4, r3) += s1*T[0]
505 SMLAL r11,r4, r2, r10 @ (r11,r4) += s0*T[0]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
/external/llvm/test/MC/ARM/
Dmul-v4.s1 @ PR17647: MUL/MLA/SMLAL/UMLAL should be avalaibe to IAS for ARMv4 and higher
/external/llvm/lib/Target/ARM/
DARMISelLowering.h167 SMLAL, // 64bit Signed Accumulate Multiply enumerator
DREADME.txt424 Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
DARMScheduleSwift.td291 (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
DARMInstrInfo.td3940 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
3969 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4105 // Halfword multiply accumulate long: SMLAL<x><y>.
5780 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
5791 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
DARMISelDAGToDAG.cpp2995 case ARMISD::SMLAL:{ in Select()
3009 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMISelLowering.h201 SMLAL, // 64bit Signed Accumulate Multiply enumerator
DARMInstrInfo.td4120 def SMLAL : AsMla1I64<0b0000111, (outs GPR:$RdLo, GPR:$RdHi),
4152 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, GPR:$RLo, GPR:$RHi,
4313 // Halfword multiply accumulate long: SMLAL<x><y>.
4314 class SMLAL<bits<2> opc1, string asm>
4323 def SMLALBB : SMLAL<0b00, "smlalbb">;
4324 def SMLALBT : SMLAL<0b10, "smlalbt">;
4325 def SMLALTB : SMLAL<0b01, "smlaltb">;
4326 def SMLALTT : SMLAL<0b11, "smlaltt">;
6096 // MUL/UMLAL/SMLAL/UMULL/SMULL are available on all arches, but
6107 (SMLAL GPR:$RdLo, GPR:$RdHi, GPR:$Rn, GPR:$Rm, pred:$p, cc_out:$s), 0>,
DREADME.txt424 Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
DARMScheduleSwift.td308 (instregex "SMLAL", "UMLAL", "SMLALBT",
DARMScheduleR52.td280 "SMLAL", "UMLAL", "SMLALBT",
DARMISelDAGToDAG.cpp2836 case ARMISD::SMLAL:{ in Select()
2850 Subtarget->hasV6Ops() ? ARM::SMLAL : ARM::SMLALv5, dl, in Select()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc123 TmpInst.setOpcode(ARM::SMLAL);
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DREADME.txt424 Should compile to use SMLAL (Signed Multiply Accumulate Long) which multiplies
/external/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td523 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SchedCyclone.td525 (instregex "MLA","MLS","SMLAL","SMLSL","UMLAL","UMLSL",
/external/vixl/doc/aarch64/
Dsupported-instructions-aarch64.md2994 ### SMLAL ### subsection
3004 ### SMLAL ### subsection

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