Searched refs:SOP1 (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 63 SOP1 Instructions
65 All SOP1 instructions are supported.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 25 field bits<1> SOP1 = 0;
61 let TSFlags{5} = SOP1;
282 class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
289 let SOP1 = 1;
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| D | SIDefines.h | 22 SOP1 = 1 << 5, enumerator
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| D | SIInstrInfo.h | 208 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
212 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
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| D | SIInstrInfo.td | 718 SOP1 <outs, ins, "", pattern>,
725 SOP1 <outs, ins, asm, []>,
735 SOP1 <outs, ins, asm, []>,
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| D | SIInstructions.td | 87 // SOP1 Instructions
2421 // SOP1 Patterns
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 32 field bit SOP1 = 0;
128 let TSFlags{2} = SOP1;
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| D | SIDefines.h | 26 SOP1 = 1 << 2, enumerator
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| D | SIInstrInfo.h | 325 return MI.getDesc().TSFlags & SIInstrFlags::SOP1; in isSOP1()
329 return get(Opcode).TSFlags & SIInstrFlags::SOP1; in isSOP1()
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| D | SOPInstructions.td | 38 // SOP1 Instructions
49 let SOP1 = 1;
1002 // SOP1 Patterns
1359 // SOP1 - GFX9.
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUUsage.rst | 4185 SOP1 subsubsection
4198 For full list of supported instructions, refer to "SOP1 Instructions" in ISA Manual.
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| D | AMDGPUAsmGFX7.rst | 364 SOP1 chapter
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| D | AMDGPUAsmGFX8.rst | 381 SOP1 chapter
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| D | AMDGPUAsmGFX9.rst | 519 SOP1 chapter
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