1.. 2 ************************************************** 3 * * 4 * Automatically generated file, do not edit! * 5 * * 6 ************************************************** 7 8=========================== 9Syntax of GFX8 Instructions 10=========================== 11 12.. contents:: 13 :local: 14 15 16DS 17=========================== 18 19.. parsed-literal:: 20 21 ds_add_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 22 ds_add_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 23 ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 24 ds_add_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 25 ds_add_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 26 ds_add_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 27 ds_add_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 28 ds_add_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 29 ds_add_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 30 ds_and_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 31 ds_and_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 32 ds_and_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 33 ds_and_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 34 ds_and_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 35 ds_and_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 36 ds_append dst :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 37 ds_bpermute_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` 38 ds_cmpst_b32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 39 ds_cmpst_b64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 40 ds_cmpst_f32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 41 ds_cmpst_f64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 42 ds_cmpst_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 43 ds_cmpst_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 44 ds_cmpst_rtn_f32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 45 ds_cmpst_rtn_f64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 46 ds_condxchg32_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 47 ds_consume dst :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 48 ds_dec_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 49 ds_dec_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 50 ds_dec_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 51 ds_dec_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 52 ds_dec_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 53 ds_dec_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 54 ds_gws_barrier src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 55 ds_gws_init src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 56 ds_gws_sema_br src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 57 ds_gws_sema_p :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 58 ds_gws_sema_release_all :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 59 ds_gws_sema_v :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 60 ds_inc_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 61 ds_inc_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 62 ds_inc_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 63 ds_inc_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 64 ds_inc_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 65 ds_inc_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 66 ds_max_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 67 ds_max_f64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 68 ds_max_i32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 69 ds_max_i64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 70 ds_max_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 71 ds_max_rtn_f64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 72 ds_max_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 73 ds_max_rtn_i64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 74 ds_max_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 75 ds_max_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 76 ds_max_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 77 ds_max_src2_f64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 78 ds_max_src2_i32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 79 ds_max_src2_i64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 80 ds_max_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 81 ds_max_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 82 ds_max_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 83 ds_max_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 84 ds_min_f32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 85 ds_min_f64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 86 ds_min_i32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 87 ds_min_i64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 88 ds_min_rtn_f32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 89 ds_min_rtn_f64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 90 ds_min_rtn_i32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 91 ds_min_rtn_i64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 92 ds_min_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 93 ds_min_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 94 ds_min_src2_f32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 95 ds_min_src2_f64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 96 ds_min_src2_i32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 97 ds_min_src2_i64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 98 ds_min_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 99 ds_min_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 100 ds_min_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 101 ds_min_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 102 ds_mskor_b32 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 103 ds_mskor_b64 src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 104 ds_mskor_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 105 ds_mskor_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 106 ds_nop 107 ds_or_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 108 ds_or_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 109 ds_or_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 110 ds_or_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 111 ds_or_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 112 ds_or_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 113 ds_ordered_count dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 114 ds_permute_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` 115 ds_read2_b32 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 116 ds_read2_b64 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 117 ds_read2st64_b32 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 118 ds_read2st64_b64 dst, src0 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 119 ds_read_b128 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 120 ds_read_b32 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 121 ds_read_b64 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 122 ds_read_b96 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 123 ds_read_i16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 124 ds_read_i8 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 125 ds_read_u16 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 126 ds_read_u8 dst, src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 127 ds_rsub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 128 ds_rsub_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 129 ds_rsub_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 130 ds_rsub_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 131 ds_rsub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 132 ds_rsub_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 133 ds_sub_rtn_u32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 134 ds_sub_rtn_u64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 135 ds_sub_src2_u32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 136 ds_sub_src2_u64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 137 ds_sub_u32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 138 ds_sub_u64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 139 ds_swizzle_b32 dst, src0 :ref:`sw_offset16<amdgpu_synid_sw_offset16>` :ref:`gds<amdgpu_synid_gds>` 140 ds_wrap_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 141 ds_write2_b32 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 142 ds_write2_b64 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 143 ds_write2st64_b32 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 144 ds_write2st64_b64 src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 145 ds_write_b128 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 146 ds_write_b16 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 147 ds_write_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 148 ds_write_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 149 ds_write_b8 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 150 ds_write_b96 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 151 ds_write_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 152 ds_write_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 153 ds_wrxchg2_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 154 ds_wrxchg2_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 155 ds_wrxchg2st64_rtn_b32 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 156 ds_wrxchg2st64_rtn_b64 dst, src0, src1, src2 :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`ds_offset8<amdgpu_synid_ds_offset8>` :ref:`gds<amdgpu_synid_gds>` 157 ds_wrxchg_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 158 ds_wrxchg_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 159 ds_xor_b32 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 160 ds_xor_b64 src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 161 ds_xor_rtn_b32 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 162 ds_xor_rtn_b64 dst, src0, src1 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 163 ds_xor_src2_b32 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 164 ds_xor_src2_b64 src0 :ref:`ds_offset16<amdgpu_synid_ds_offset16>` :ref:`gds<amdgpu_synid_gds>` 165 166EXP 167=========================== 168 169.. parsed-literal:: 170 171 exp dst, src0, src1, src2, src3 :ref:`done<amdgpu_synid_done>` :ref:`compr<amdgpu_synid_compr>` :ref:`vm<amdgpu_synid_vm>` 172 173FLAT 174=========================== 175 176.. parsed-literal:: 177 178 flat_atomic_add dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 179 flat_atomic_add_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 180 flat_atomic_and dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 181 flat_atomic_and_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 182 flat_atomic_cmpswap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 183 flat_atomic_cmpswap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 184 flat_atomic_dec dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 185 flat_atomic_dec_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 186 flat_atomic_inc dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 187 flat_atomic_inc_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 188 flat_atomic_or dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 189 flat_atomic_or_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 190 flat_atomic_smax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 191 flat_atomic_smax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 192 flat_atomic_smin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 193 flat_atomic_smin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 194 flat_atomic_sub dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 195 flat_atomic_sub_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 196 flat_atomic_swap dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 197 flat_atomic_swap_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 198 flat_atomic_umax dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 199 flat_atomic_umax_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 200 flat_atomic_umin dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 201 flat_atomic_umin_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 202 flat_atomic_xor dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 203 flat_atomic_xor_x2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 204 flat_load_dword dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 205 flat_load_dwordx2 dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 206 flat_load_dwordx3 dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 207 flat_load_dwordx4 dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 208 flat_load_sbyte dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 209 flat_load_sshort dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 210 flat_load_ubyte dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 211 flat_load_ushort dst, src0 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 212 flat_store_byte src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 213 flat_store_dword src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 214 flat_store_dwordx2 src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 215 flat_store_dwordx3 src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 216 flat_store_dwordx4 src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 217 flat_store_short src0, src1 :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 218 219MIMG 220=========================== 221 222.. parsed-literal:: 223 224 image_atomic_add dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 225 image_atomic_and dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 226 image_atomic_cmpswap dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 227 image_atomic_dec dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 228 image_atomic_inc dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 229 image_atomic_or dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 230 image_atomic_smax dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 231 image_atomic_smin dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 232 image_atomic_sub dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 233 image_atomic_swap dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 234 image_atomic_umax dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 235 image_atomic_umin dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 236 image_atomic_xor dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 237 image_gather4 dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 238 image_gather4_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 239 image_gather4_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 240 image_gather4_b_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 241 image_gather4_b_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 242 image_gather4_c dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 243 image_gather4_c_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 244 image_gather4_c_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 245 image_gather4_c_b_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 246 image_gather4_c_b_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 247 image_gather4_c_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 248 image_gather4_c_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 249 image_gather4_c_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 250 image_gather4_c_l_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 251 image_gather4_c_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 252 image_gather4_c_lz_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 253 image_gather4_c_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 254 image_gather4_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 255 image_gather4_cl_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 256 image_gather4_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 257 image_gather4_l_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 258 image_gather4_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 259 image_gather4_lz_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 260 image_gather4_o dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 261 image_get_lod dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 262 image_get_resinfo dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 263 image_load dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 264 image_load_mip dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 265 image_load_mip_pck dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 266 image_load_mip_pck_sgn dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 267 image_load_pck dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 268 image_load_pck_sgn dst, src0, src1 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 269 image_sample dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 270 image_sample_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 271 image_sample_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 272 image_sample_c dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 273 image_sample_c_b dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 274 image_sample_c_b_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 275 image_sample_c_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 276 image_sample_c_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 277 image_sample_c_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 278 image_sample_cl dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 279 image_sample_l dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 280 image_sample_lz dst, src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 281 image_store src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 282 image_store_mip src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` :ref:`d16<amdgpu_synid_d16>` 283 image_store_mip_pck src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 284 image_store_pck src0, src1, src2 :ref:`dmask<amdgpu_synid_dmask>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`da<amdgpu_synid_da>` 285 286MUBUF 287=========================== 288 289.. parsed-literal:: 290 291 buffer_atomic_add dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 292 buffer_atomic_add_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 293 buffer_atomic_and dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 294 buffer_atomic_and_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 295 buffer_atomic_cmpswap dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 296 buffer_atomic_cmpswap_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 297 buffer_atomic_dec dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 298 buffer_atomic_dec_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 299 buffer_atomic_inc dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 300 buffer_atomic_inc_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 301 buffer_atomic_or dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 302 buffer_atomic_or_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 303 buffer_atomic_smax dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 304 buffer_atomic_smax_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 305 buffer_atomic_smin dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 306 buffer_atomic_smin_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 307 buffer_atomic_sub dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 308 buffer_atomic_sub_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 309 buffer_atomic_swap dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 310 buffer_atomic_swap_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 311 buffer_atomic_umax dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 312 buffer_atomic_umax_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 313 buffer_atomic_umin dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 314 buffer_atomic_umin_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 315 buffer_atomic_xor dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 316 buffer_atomic_xor_x2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 317 buffer_load_dword dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` 318 buffer_load_dwordx2 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 319 buffer_load_dwordx3 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 320 buffer_load_dwordx4 dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 321 buffer_load_format_d16_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 322 buffer_load_format_d16_xy dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 323 buffer_load_format_d16_xyz dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 324 buffer_load_format_d16_xyzw dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 325 buffer_load_format_x dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` 326 buffer_load_format_xy dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 327 buffer_load_format_xyz dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 328 buffer_load_format_xyzw dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 329 buffer_load_sbyte dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` 330 buffer_load_sshort dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` 331 buffer_load_ubyte dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` 332 buffer_load_ushort dst, src0, src1, src2 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`lds<amdgpu_synid_lds>` 333 buffer_store_byte src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 334 buffer_store_dword src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 335 buffer_store_dwordx2 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 336 buffer_store_dwordx3 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 337 buffer_store_dwordx4 src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 338 buffer_store_format_d16_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 339 buffer_store_format_d16_xy src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 340 buffer_store_format_d16_xyz src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 341 buffer_store_format_d16_xyzw src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 342 buffer_store_format_x src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 343 buffer_store_format_xy src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 344 buffer_store_format_xyz src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 345 buffer_store_format_xyzw src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 346 buffer_store_lds_dword src0, src1 :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`lds<amdgpu_synid_lds>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 347 buffer_store_short src0, src1, src2, src3 :ref:`idxen<amdgpu_synid_idxen>` :ref:`offen<amdgpu_synid_offen>` :ref:`buf_offset12<amdgpu_synid_buf_offset12>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` 348 buffer_wbinvl1 349 buffer_wbinvl1_vol 350 351SMEM 352=========================== 353 354.. parsed-literal:: 355 356 s_atc_probe src0, src1, src2 357 s_atc_probe_buffer src0, src1, src2 358 s_buffer_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 359 s_buffer_load_dwordx16 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 360 s_buffer_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 361 s_buffer_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 362 s_buffer_load_dwordx8 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 363 s_buffer_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>` 364 s_buffer_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>` 365 s_buffer_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>` 366 s_dcache_inv 367 s_dcache_inv_vol 368 s_dcache_wb 369 s_dcache_wb_vol 370 s_load_dword dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 371 s_load_dwordx16 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 372 s_load_dwordx2 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 373 s_load_dwordx4 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 374 s_load_dwordx8 dst, src0, src1 :ref:`glc<amdgpu_synid_glc>` 375 s_memrealtime dst 376 s_memtime dst 377 s_store_dword src0, src1, src2 :ref:`glc<amdgpu_synid_glc>` 378 s_store_dwordx2 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>` 379 s_store_dwordx4 src0, src1, src2 :ref:`glc<amdgpu_synid_glc>` 380 381SOP1 382=========================== 383 384.. parsed-literal:: 385 386 s_abs_i32 dst, src0 387 s_and_saveexec_b64 dst, src0 388 s_andn2_saveexec_b64 dst, src0 389 s_bcnt0_i32_b32 dst, src0 390 s_bcnt0_i32_b64 dst, src0 391 s_bcnt1_i32_b32 dst, src0 392 s_bcnt1_i32_b64 dst, src0 393 s_bitset0_b32 dst, src0 394 s_bitset0_b64 dst, src0 395 s_bitset1_b32 dst, src0 396 s_bitset1_b64 dst, src0 397 s_brev_b32 dst, src0 398 s_brev_b64 dst, src0 399 s_cbranch_join src0 400 s_cmov_b32 dst, src0 401 s_cmov_b64 dst, src0 402 s_ff0_i32_b32 dst, src0 403 s_ff0_i32_b64 dst, src0 404 s_ff1_i32_b32 dst, src0 405 s_ff1_i32_b64 dst, src0 406 s_flbit_i32 dst, src0 407 s_flbit_i32_b32 dst, src0 408 s_flbit_i32_b64 dst, src0 409 s_flbit_i32_i64 dst, src0 410 s_getpc_b64 dst 411 s_mov_b32 dst, src0 412 s_mov_b64 dst, src0 413 s_mov_fed_b32 dst, src0 414 s_movreld_b32 dst, src0 415 s_movreld_b64 dst, src0 416 s_movrels_b32 dst, src0 417 s_movrels_b64 dst, src0 418 s_nand_saveexec_b64 dst, src0 419 s_nor_saveexec_b64 dst, src0 420 s_not_b32 dst, src0 421 s_not_b64 dst, src0 422 s_or_saveexec_b64 dst, src0 423 s_orn2_saveexec_b64 dst, src0 424 s_quadmask_b32 dst, src0 425 s_quadmask_b64 dst, src0 426 s_rfe_b64 src0 427 s_set_gpr_idx_idx src0 428 s_setpc_b64 src0 429 s_sext_i32_i16 dst, src0 430 s_sext_i32_i8 dst, src0 431 s_swappc_b64 dst, src0 432 s_wqm_b32 dst, src0 433 s_wqm_b64 dst, src0 434 s_xnor_saveexec_b64 dst, src0 435 s_xor_saveexec_b64 dst, src0 436 437SOP2 438=========================== 439 440.. parsed-literal:: 441 442 s_absdiff_i32 dst, src0, src1 443 s_add_i32 dst, src0, src1 444 s_add_u32 dst, src0, src1 445 s_addc_u32 dst, src0, src1 446 s_and_b32 dst, src0, src1 447 s_and_b64 dst, src0, src1 448 s_andn2_b32 dst, src0, src1 449 s_andn2_b64 dst, src0, src1 450 s_ashr_i32 dst, src0, src1 451 s_ashr_i64 dst, src0, src1 452 s_bfe_i32 dst, src0, src1 453 s_bfe_i64 dst, src0, src1 454 s_bfe_u32 dst, src0, src1 455 s_bfe_u64 dst, src0, src1 456 s_bfm_b32 dst, src0, src1 457 s_bfm_b64 dst, src0, src1 458 s_cbranch_g_fork src0, src1 459 s_cselect_b32 dst, src0, src1 460 s_cselect_b64 dst, src0, src1 461 s_lshl_b32 dst, src0, src1 462 s_lshl_b64 dst, src0, src1 463 s_lshr_b32 dst, src0, src1 464 s_lshr_b64 dst, src0, src1 465 s_max_i32 dst, src0, src1 466 s_max_u32 dst, src0, src1 467 s_min_i32 dst, src0, src1 468 s_min_u32 dst, src0, src1 469 s_mul_i32 dst, src0, src1 470 s_nand_b32 dst, src0, src1 471 s_nand_b64 dst, src0, src1 472 s_nor_b32 dst, src0, src1 473 s_nor_b64 dst, src0, src1 474 s_or_b32 dst, src0, src1 475 s_or_b64 dst, src0, src1 476 s_orn2_b32 dst, src0, src1 477 s_orn2_b64 dst, src0, src1 478 s_rfe_restore_b64 src0, src1 479 s_sub_i32 dst, src0, src1 480 s_sub_u32 dst, src0, src1 481 s_subb_u32 dst, src0, src1 482 s_xnor_b32 dst, src0, src1 483 s_xnor_b64 dst, src0, src1 484 s_xor_b32 dst, src0, src1 485 s_xor_b64 dst, src0, src1 486 487SOPC 488=========================== 489 490.. parsed-literal:: 491 492 s_bitcmp0_b32 src0, src1 493 s_bitcmp0_b64 src0, src1 494 s_bitcmp1_b32 src0, src1 495 s_bitcmp1_b64 src0, src1 496 s_cmp_eq_i32 src0, src1 497 s_cmp_eq_u32 src0, src1 498 s_cmp_eq_u64 src0, src1 499 s_cmp_ge_i32 src0, src1 500 s_cmp_ge_u32 src0, src1 501 s_cmp_gt_i32 src0, src1 502 s_cmp_gt_u32 src0, src1 503 s_cmp_le_i32 src0, src1 504 s_cmp_le_u32 src0, src1 505 s_cmp_lg_i32 src0, src1 506 s_cmp_lg_u32 src0, src1 507 s_cmp_lg_u64 src0, src1 508 s_cmp_lt_i32 src0, src1 509 s_cmp_lt_u32 src0, src1 510 s_set_gpr_idx_on src0, src1 511 s_setvskip src0, src1 512 513SOPK 514=========================== 515 516.. parsed-literal:: 517 518 s_addk_i32 dst, src0 519 s_cbranch_i_fork src0, src1 520 s_cmovk_i32 dst, src0 521 s_cmpk_eq_i32 src0, src1 522 s_cmpk_eq_u32 src0, src1 523 s_cmpk_ge_i32 src0, src1 524 s_cmpk_ge_u32 src0, src1 525 s_cmpk_gt_i32 src0, src1 526 s_cmpk_gt_u32 src0, src1 527 s_cmpk_le_i32 src0, src1 528 s_cmpk_le_u32 src0, src1 529 s_cmpk_lg_i32 src0, src1 530 s_cmpk_lg_u32 src0, src1 531 s_cmpk_lt_i32 src0, src1 532 s_cmpk_lt_u32 src0, src1 533 s_getreg_b32 dst, src0 534 s_movk_i32 dst, src0 535 s_mulk_i32 dst, src0 536 s_setreg_b32 dst, src0 537 s_setreg_imm32_b32 dst, src0 538 539SOPP 540=========================== 541 542.. parsed-literal:: 543 544 s_barrier 545 s_branch src0 546 s_cbranch_cdbgsys src0 547 s_cbranch_cdbgsys_and_user src0 548 s_cbranch_cdbgsys_or_user src0 549 s_cbranch_cdbguser src0 550 s_cbranch_execnz src0 551 s_cbranch_execz src0 552 s_cbranch_scc0 src0 553 s_cbranch_scc1 src0 554 s_cbranch_vccnz src0 555 s_cbranch_vccz src0 556 s_decperflevel src0 557 s_endpgm 558 s_endpgm_saved 559 s_icache_inv 560 s_incperflevel src0 561 s_nop src0 562 s_sendmsg src0 563 s_sendmsghalt src0 564 s_set_gpr_idx_mode src0 565 s_set_gpr_idx_off 566 s_sethalt src0 567 s_setkill src0 568 s_setprio src0 569 s_sleep src0 570 s_trap src0 571 s_ttracedata 572 s_waitcnt src0 573 s_wakeup 574 575VINTRP 576=========================== 577 578.. parsed-literal:: 579 580 v_interp_mov_f32 dst, src0, src1 581 v_interp_p1_f32 dst, src0, src1 582 v_interp_p2_f32 dst, src0, src1 583 584VOP1 585=========================== 586 587.. parsed-literal:: 588 589 v_bfrev_b32 dst, src0 590 v_bfrev_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 591 v_bfrev_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 592 v_ceil_f16 dst, src0 593 v_ceil_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 594 v_ceil_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 595 v_ceil_f32 dst, src0 596 v_ceil_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 597 v_ceil_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 598 v_ceil_f64 dst, src0 599 v_clrexcp 600 v_cos_f16 dst, src0 601 v_cos_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 602 v_cos_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 603 v_cos_f32 dst, src0 604 v_cos_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 605 v_cos_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 606 v_cvt_f16_f32 dst, src0 607 v_cvt_f16_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 608 v_cvt_f16_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 609 v_cvt_f16_i16 dst, src0 610 v_cvt_f16_i16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 611 v_cvt_f16_i16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 612 v_cvt_f16_u16 dst, src0 613 v_cvt_f16_u16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 614 v_cvt_f16_u16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 615 v_cvt_f32_f16 dst, src0 616 v_cvt_f32_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 617 v_cvt_f32_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 618 v_cvt_f32_f64 dst, src0 619 v_cvt_f32_i32 dst, src0 620 v_cvt_f32_i32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 621 v_cvt_f32_i32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 622 v_cvt_f32_u32 dst, src0 623 v_cvt_f32_u32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 624 v_cvt_f32_u32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 625 v_cvt_f32_ubyte0 dst, src0 626 v_cvt_f32_ubyte0_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 627 v_cvt_f32_ubyte0_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 628 v_cvt_f32_ubyte1 dst, src0 629 v_cvt_f32_ubyte1_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 630 v_cvt_f32_ubyte1_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 631 v_cvt_f32_ubyte2 dst, src0 632 v_cvt_f32_ubyte2_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 633 v_cvt_f32_ubyte2_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 634 v_cvt_f32_ubyte3 dst, src0 635 v_cvt_f32_ubyte3_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 636 v_cvt_f32_ubyte3_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 637 v_cvt_f64_f32 dst, src0 638 v_cvt_f64_i32 dst, src0 639 v_cvt_f64_u32 dst, src0 640 v_cvt_flr_i32_f32 dst, src0 641 v_cvt_flr_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 642 v_cvt_flr_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 643 v_cvt_i16_f16 dst, src0 644 v_cvt_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 645 v_cvt_i16_f16_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 646 v_cvt_i32_f32 dst, src0 647 v_cvt_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 648 v_cvt_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 649 v_cvt_i32_f64 dst, src0 650 v_cvt_off_f32_i4 dst, src0 651 v_cvt_off_f32_i4_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 652 v_cvt_off_f32_i4_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 653 v_cvt_rpi_i32_f32 dst, src0 654 v_cvt_rpi_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 655 v_cvt_rpi_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 656 v_cvt_u16_f16 dst, src0 657 v_cvt_u16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 658 v_cvt_u16_f16_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 659 v_cvt_u32_f32 dst, src0 660 v_cvt_u32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 661 v_cvt_u32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 662 v_cvt_u32_f64 dst, src0 663 v_exp_f16 dst, src0 664 v_exp_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 665 v_exp_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 666 v_exp_f32 dst, src0 667 v_exp_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 668 v_exp_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 669 v_exp_legacy_f32 dst, src0 670 v_exp_legacy_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 671 v_exp_legacy_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 672 v_ffbh_i32 dst, src0 673 v_ffbh_i32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 674 v_ffbh_i32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 675 v_ffbh_u32 dst, src0 676 v_ffbh_u32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 677 v_ffbh_u32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 678 v_ffbl_b32 dst, src0 679 v_ffbl_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 680 v_ffbl_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 681 v_floor_f16 dst, src0 682 v_floor_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 683 v_floor_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 684 v_floor_f32 dst, src0 685 v_floor_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 686 v_floor_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 687 v_floor_f64 dst, src0 688 v_fract_f16 dst, src0 689 v_fract_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 690 v_fract_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 691 v_fract_f32 dst, src0 692 v_fract_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 693 v_fract_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 694 v_fract_f64 dst, src0 695 v_frexp_exp_i16_f16 dst, src0 696 v_frexp_exp_i16_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 697 v_frexp_exp_i16_f16_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 698 v_frexp_exp_i32_f32 dst, src0 699 v_frexp_exp_i32_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 700 v_frexp_exp_i32_f32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 701 v_frexp_exp_i32_f64 dst, src0 702 v_frexp_mant_f16 dst, src0 703 v_frexp_mant_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 704 v_frexp_mant_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 705 v_frexp_mant_f32 dst, src0 706 v_frexp_mant_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 707 v_frexp_mant_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 708 v_frexp_mant_f64 dst, src0 709 v_log_f16 dst, src0 710 v_log_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 711 v_log_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 712 v_log_f32 dst, src0 713 v_log_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 714 v_log_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 715 v_log_legacy_f32 dst, src0 716 v_log_legacy_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 717 v_log_legacy_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 718 v_mov_b32 dst, src0 719 v_mov_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 720 v_mov_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 721 v_mov_fed_b32 dst, src0 722 v_mov_fed_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 723 v_mov_fed_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 724 v_movreld_b32 dst, src0 725 v_movrels_b32 dst, src0 726 v_movrelsd_b32 dst, src0 727 v_nop 728 v_not_b32 dst, src0 729 v_not_b32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 730 v_not_b32_sdwa dst, src0 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 731 v_rcp_f16 dst, src0 732 v_rcp_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 733 v_rcp_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 734 v_rcp_f32 dst, src0 735 v_rcp_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 736 v_rcp_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 737 v_rcp_f64 dst, src0 738 v_rcp_iflag_f32 dst, src0 739 v_rcp_iflag_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 740 v_rcp_iflag_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 741 v_readfirstlane_b32 dst, src0 742 v_rndne_f16 dst, src0 743 v_rndne_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 744 v_rndne_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 745 v_rndne_f32 dst, src0 746 v_rndne_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 747 v_rndne_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 748 v_rndne_f64 dst, src0 749 v_rsq_f16 dst, src0 750 v_rsq_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 751 v_rsq_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 752 v_rsq_f32 dst, src0 753 v_rsq_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 754 v_rsq_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 755 v_rsq_f64 dst, src0 756 v_sin_f16 dst, src0 757 v_sin_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 758 v_sin_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 759 v_sin_f32 dst, src0 760 v_sin_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 761 v_sin_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 762 v_sqrt_f16 dst, src0 763 v_sqrt_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 764 v_sqrt_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 765 v_sqrt_f32 dst, src0 766 v_sqrt_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 767 v_sqrt_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 768 v_sqrt_f64 dst, src0 769 v_trunc_f16 dst, src0 770 v_trunc_f16_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 771 v_trunc_f16_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 772 v_trunc_f32 dst, src0 773 v_trunc_f32_dpp dst, src0 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 774 v_trunc_f32_sdwa dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` 775 v_trunc_f64 dst, src0 776 777VOP2 778=========================== 779 780.. parsed-literal:: 781 782 v_add_f16 dst, src0, src1 783 v_add_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 784 v_add_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 785 v_add_f32 dst, src0, src1 786 v_add_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 787 v_add_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 788 v_add_u16 dst, src0, src1 789 v_add_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 790 v_add_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 791 v_add_u32 dst0, dst1, src0, src1 792 v_add_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 793 v_add_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 794 v_addc_u32 dst0, dst1, src0, src1, src2 795 v_addc_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 796 v_addc_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 797 v_and_b32 dst, src0, src1 798 v_and_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 799 v_and_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 800 v_ashrrev_i16 dst, src0, src1 801 v_ashrrev_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 802 v_ashrrev_i16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 803 v_ashrrev_i32 dst, src0, src1 804 v_ashrrev_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 805 v_ashrrev_i32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 806 v_cndmask_b32 dst, src0, src1, src2 807 v_cndmask_b32_dpp dst, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 808 v_cndmask_b32_sdwa dst, src0, src1, src2 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 809 v_ldexp_f16 dst, src0, src1 810 v_ldexp_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 811 v_ldexp_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 812 v_lshlrev_b16 dst, src0, src1 813 v_lshlrev_b16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 814 v_lshlrev_b16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 815 v_lshlrev_b32 dst, src0, src1 816 v_lshlrev_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 817 v_lshlrev_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 818 v_lshrrev_b16 dst, src0, src1 819 v_lshrrev_b16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 820 v_lshrrev_b16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 821 v_lshrrev_b32 dst, src0, src1 822 v_lshrrev_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 823 v_lshrrev_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 824 v_mac_f16 dst, src0, src1 825 v_mac_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 826 v_mac_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 827 v_mac_f32 dst, src0, src1 828 v_mac_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 829 v_mac_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 830 v_madak_f16 dst, src0, src1, src2 831 v_madak_f32 dst, src0, src1, src2 832 v_madmk_f16 dst, src0, src1, src2 833 v_madmk_f32 dst, src0, src1, src2 834 v_max_f16 dst, src0, src1 835 v_max_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 836 v_max_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 837 v_max_f32 dst, src0, src1 838 v_max_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 839 v_max_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 840 v_max_i16 dst, src0, src1 841 v_max_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 842 v_max_i16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 843 v_max_i32 dst, src0, src1 844 v_max_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 845 v_max_i32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 846 v_max_u16 dst, src0, src1 847 v_max_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 848 v_max_u16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 849 v_max_u32 dst, src0, src1 850 v_max_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 851 v_max_u32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 852 v_min_f16 dst, src0, src1 853 v_min_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 854 v_min_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 855 v_min_f32 dst, src0, src1 856 v_min_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 857 v_min_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 858 v_min_i16 dst, src0, src1 859 v_min_i16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 860 v_min_i16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 861 v_min_i32 dst, src0, src1 862 v_min_i32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 863 v_min_i32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 864 v_min_u16 dst, src0, src1 865 v_min_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 866 v_min_u16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 867 v_min_u32 dst, src0, src1 868 v_min_u32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 869 v_min_u32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 870 v_mul_f16 dst, src0, src1 871 v_mul_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 872 v_mul_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 873 v_mul_f32 dst, src0, src1 874 v_mul_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 875 v_mul_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 876 v_mul_hi_i32_i24 dst, src0, src1 877 v_mul_hi_i32_i24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 878 v_mul_hi_i32_i24_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 879 v_mul_hi_u32_u24 dst, src0, src1 880 v_mul_hi_u32_u24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 881 v_mul_hi_u32_u24_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 882 v_mul_i32_i24 dst, src0, src1 883 v_mul_i32_i24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 884 v_mul_i32_i24_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 885 v_mul_legacy_f32 dst, src0, src1 886 v_mul_legacy_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 887 v_mul_legacy_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 888 v_mul_lo_u16 dst, src0, src1 889 v_mul_lo_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 890 v_mul_lo_u16_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 891 v_mul_u32_u24 dst, src0, src1 892 v_mul_u32_u24_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 893 v_mul_u32_u24_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 894 v_or_b32 dst, src0, src1 895 v_or_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 896 v_or_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 897 v_sub_f16 dst, src0, src1 898 v_sub_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 899 v_sub_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 900 v_sub_f32 dst, src0, src1 901 v_sub_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 902 v_sub_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 903 v_sub_u16 dst, src0, src1 904 v_sub_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 905 v_sub_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 906 v_sub_u32 dst0, dst1, src0, src1 907 v_sub_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 908 v_sub_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 909 v_subb_u32 dst0, dst1, src0, src1, src2 910 v_subb_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 911 v_subb_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 912 v_subbrev_u32 dst0, dst1, src0, src1, src2 913 v_subbrev_u32_dpp dst0, dst1, src0, src1, src2 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 914 v_subbrev_u32_sdwa dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 915 v_subrev_f16 dst, src0, src1 916 v_subrev_f16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 917 v_subrev_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 918 v_subrev_f32 dst, src0, src1 919 v_subrev_f32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 920 v_subrev_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 921 v_subrev_u16 dst, src0, src1 922 v_subrev_u16_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 923 v_subrev_u16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 924 v_subrev_u32 dst0, dst1, src0, src1 925 v_subrev_u32_dpp dst0, dst1, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 926 v_subrev_u32_sdwa dst0, dst1, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 927 v_xor_b32 dst, src0, src1 928 v_xor_b32_dpp dst, src0, src1 :ref:`dpp_ctrl<amdgpu_synid_dpp_ctrl>` :ref:`row_mask<amdgpu_synid_row_mask>` :ref:`bank_mask<amdgpu_synid_bank_mask>` :ref:`bound_ctrl<amdgpu_synid_bound_ctrl>` 929 v_xor_b32_sdwa dst, src0, src1 :ref:`dst_sel<amdgpu_synid_dst_sel>` :ref:`dst_unused<amdgpu_synid_dst_unused>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 930 931VOP3 932=========================== 933 934.. parsed-literal:: 935 936 v_add_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 937 v_add_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 938 v_add_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 939 v_add_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 940 v_add_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>` 941 v_addc_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 942 v_alignbit_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 943 v_alignbyte_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 944 v_and_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 945 v_ashrrev_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 946 v_ashrrev_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 947 v_ashrrev_i64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 948 v_bcnt_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 949 v_bfe_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 950 v_bfe_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 951 v_bfi_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 952 v_bfm_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 953 v_bfrev_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 954 v_ceil_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 955 v_ceil_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 956 v_ceil_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 957 v_clrexcp_e64 :ref:`omod<amdgpu_synid_omod>` 958 v_cmp_class_f16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 959 v_cmp_class_f32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 960 v_cmp_class_f64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 961 v_cmp_eq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 962 v_cmp_eq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 963 v_cmp_eq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 964 v_cmp_eq_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 965 v_cmp_eq_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 966 v_cmp_eq_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 967 v_cmp_eq_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 968 v_cmp_eq_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 969 v_cmp_eq_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 970 v_cmp_f_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 971 v_cmp_f_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 972 v_cmp_f_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 973 v_cmp_f_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 974 v_cmp_f_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 975 v_cmp_f_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 976 v_cmp_f_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 977 v_cmp_f_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 978 v_cmp_f_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 979 v_cmp_ge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 980 v_cmp_ge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 981 v_cmp_ge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 982 v_cmp_ge_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 983 v_cmp_ge_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 984 v_cmp_ge_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 985 v_cmp_ge_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 986 v_cmp_ge_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 987 v_cmp_ge_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 988 v_cmp_gt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 989 v_cmp_gt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 990 v_cmp_gt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 991 v_cmp_gt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 992 v_cmp_gt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 993 v_cmp_gt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 994 v_cmp_gt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 995 v_cmp_gt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 996 v_cmp_gt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 997 v_cmp_le_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 998 v_cmp_le_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 999 v_cmp_le_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1000 v_cmp_le_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1001 v_cmp_le_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1002 v_cmp_le_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1003 v_cmp_le_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1004 v_cmp_le_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1005 v_cmp_le_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1006 v_cmp_lg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1007 v_cmp_lg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1008 v_cmp_lg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1009 v_cmp_lt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1010 v_cmp_lt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1011 v_cmp_lt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1012 v_cmp_lt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1013 v_cmp_lt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1014 v_cmp_lt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1015 v_cmp_lt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1016 v_cmp_lt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1017 v_cmp_lt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1018 v_cmp_ne_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1019 v_cmp_ne_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1020 v_cmp_ne_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1021 v_cmp_ne_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1022 v_cmp_ne_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1023 v_cmp_ne_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1024 v_cmp_neq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1025 v_cmp_neq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1026 v_cmp_neq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1027 v_cmp_nge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1028 v_cmp_nge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1029 v_cmp_nge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1030 v_cmp_ngt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1031 v_cmp_ngt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1032 v_cmp_ngt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1033 v_cmp_nle_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1034 v_cmp_nle_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1035 v_cmp_nle_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1036 v_cmp_nlg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1037 v_cmp_nlg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1038 v_cmp_nlg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1039 v_cmp_nlt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1040 v_cmp_nlt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1041 v_cmp_nlt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1042 v_cmp_o_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1043 v_cmp_o_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1044 v_cmp_o_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1045 v_cmp_t_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1046 v_cmp_t_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1047 v_cmp_t_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1048 v_cmp_t_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1049 v_cmp_t_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1050 v_cmp_t_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1051 v_cmp_tru_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1052 v_cmp_tru_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1053 v_cmp_tru_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1054 v_cmp_u_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1055 v_cmp_u_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1056 v_cmp_u_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1057 v_cmpx_class_f16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1058 v_cmpx_class_f32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1059 v_cmpx_class_f64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1060 v_cmpx_eq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1061 v_cmpx_eq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1062 v_cmpx_eq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1063 v_cmpx_eq_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1064 v_cmpx_eq_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1065 v_cmpx_eq_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1066 v_cmpx_eq_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1067 v_cmpx_eq_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1068 v_cmpx_eq_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1069 v_cmpx_f_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1070 v_cmpx_f_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1071 v_cmpx_f_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1072 v_cmpx_f_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1073 v_cmpx_f_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1074 v_cmpx_f_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1075 v_cmpx_f_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1076 v_cmpx_f_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1077 v_cmpx_f_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1078 v_cmpx_ge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1079 v_cmpx_ge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1080 v_cmpx_ge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1081 v_cmpx_ge_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1082 v_cmpx_ge_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1083 v_cmpx_ge_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1084 v_cmpx_ge_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1085 v_cmpx_ge_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1086 v_cmpx_ge_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1087 v_cmpx_gt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1088 v_cmpx_gt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1089 v_cmpx_gt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1090 v_cmpx_gt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1091 v_cmpx_gt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1092 v_cmpx_gt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1093 v_cmpx_gt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1094 v_cmpx_gt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1095 v_cmpx_gt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1096 v_cmpx_le_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1097 v_cmpx_le_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1098 v_cmpx_le_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1099 v_cmpx_le_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1100 v_cmpx_le_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1101 v_cmpx_le_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1102 v_cmpx_le_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1103 v_cmpx_le_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1104 v_cmpx_le_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1105 v_cmpx_lg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1106 v_cmpx_lg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1107 v_cmpx_lg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1108 v_cmpx_lt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1109 v_cmpx_lt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1110 v_cmpx_lt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1111 v_cmpx_lt_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1112 v_cmpx_lt_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1113 v_cmpx_lt_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1114 v_cmpx_lt_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1115 v_cmpx_lt_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1116 v_cmpx_lt_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1117 v_cmpx_ne_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1118 v_cmpx_ne_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1119 v_cmpx_ne_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1120 v_cmpx_ne_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1121 v_cmpx_ne_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1122 v_cmpx_ne_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1123 v_cmpx_neq_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1124 v_cmpx_neq_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1125 v_cmpx_neq_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1126 v_cmpx_nge_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1127 v_cmpx_nge_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1128 v_cmpx_nge_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1129 v_cmpx_ngt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1130 v_cmpx_ngt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1131 v_cmpx_ngt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1132 v_cmpx_nle_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1133 v_cmpx_nle_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1134 v_cmpx_nle_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1135 v_cmpx_nlg_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1136 v_cmpx_nlg_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1137 v_cmpx_nlg_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1138 v_cmpx_nlt_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1139 v_cmpx_nlt_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1140 v_cmpx_nlt_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1141 v_cmpx_o_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1142 v_cmpx_o_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1143 v_cmpx_o_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1144 v_cmpx_t_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1145 v_cmpx_t_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1146 v_cmpx_t_i64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1147 v_cmpx_t_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1148 v_cmpx_t_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1149 v_cmpx_t_u64_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1150 v_cmpx_tru_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1151 v_cmpx_tru_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1152 v_cmpx_tru_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1153 v_cmpx_u_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1154 v_cmpx_u_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1155 v_cmpx_u_f64_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1156 v_cndmask_b32_e64 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1157 v_cos_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1158 v_cos_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1159 v_cubeid_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1160 v_cubema_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1161 v_cubesc_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1162 v_cubetc_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1163 v_cvt_f16_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1164 v_cvt_f16_i16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1165 v_cvt_f16_u16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1166 v_cvt_f32_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1167 v_cvt_f32_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1168 v_cvt_f32_i32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1169 v_cvt_f32_u32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1170 v_cvt_f32_ubyte0_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1171 v_cvt_f32_ubyte1_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1172 v_cvt_f32_ubyte2_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1173 v_cvt_f32_ubyte3_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1174 v_cvt_f64_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1175 v_cvt_f64_i32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1176 v_cvt_f64_u32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1177 v_cvt_flr_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1178 v_cvt_i16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1179 v_cvt_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1180 v_cvt_i32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1181 v_cvt_off_f32_i4_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1182 v_cvt_pk_i16_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1183 v_cvt_pk_u16_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1184 v_cvt_pk_u8_f32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1185 v_cvt_pkaccum_u8_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1186 v_cvt_pknorm_i16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1187 v_cvt_pknorm_u16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1188 v_cvt_pkrtz_f16_f32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1189 v_cvt_rpi_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1190 v_cvt_u16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1191 v_cvt_u32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1192 v_cvt_u32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1193 v_div_fixup_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1194 v_div_fixup_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1195 v_div_fixup_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1196 v_div_fmas_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1197 v_div_fmas_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1198 v_div_scale_f32 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1199 v_div_scale_f64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1200 v_exp_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1201 v_exp_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1202 v_exp_legacy_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1203 v_ffbh_i32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1204 v_ffbh_u32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1205 v_ffbl_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1206 v_floor_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1207 v_floor_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1208 v_floor_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1209 v_fma_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1210 v_fma_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1211 v_fma_f64 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1212 v_fract_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1213 v_fract_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1214 v_fract_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1215 v_frexp_exp_i16_f16_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1216 v_frexp_exp_i32_f32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1217 v_frexp_exp_i32_f64_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1218 v_frexp_mant_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1219 v_frexp_mant_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1220 v_frexp_mant_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1221 v_interp_mov_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1222 v_interp_p1_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1223 v_interp_p1ll_f16 dst, src0, src1 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1224 v_interp_p1lv_f16 dst, src0, src1, src2 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1225 v_interp_p2_f16 dst, src0, src1, src2 :ref:`high<amdgpu_synid_high>` :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1226 v_interp_p2_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1227 v_ldexp_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1228 v_ldexp_f32 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1229 v_ldexp_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1230 v_lerp_u8 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1231 v_log_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1232 v_log_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1233 v_log_legacy_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1234 v_lshlrev_b16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1235 v_lshlrev_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1236 v_lshlrev_b64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1237 v_lshrrev_b16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1238 v_lshrrev_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1239 v_lshrrev_b64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1240 v_mac_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1241 v_mac_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1242 v_mad_f16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1243 v_mad_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1244 v_mad_i16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1245 v_mad_i32_i24 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1246 v_mad_i64_i32 dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1247 v_mad_legacy_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1248 v_mad_u16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1249 v_mad_u32_u24 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1250 v_mad_u64_u32 dst0, dst1, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1251 v_max3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1252 v_max3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1253 v_max3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1254 v_max_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1255 v_max_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1256 v_max_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1257 v_max_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1258 v_max_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1259 v_max_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1260 v_max_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1261 v_mbcnt_hi_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1262 v_mbcnt_lo_u32_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1263 v_med3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1264 v_med3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1265 v_med3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1266 v_min3_f32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1267 v_min3_i32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1268 v_min3_u32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1269 v_min_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1270 v_min_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1271 v_min_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1272 v_min_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1273 v_min_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1274 v_min_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1275 v_min_u32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1276 v_mov_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1277 v_mov_fed_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1278 v_movreld_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1279 v_movrels_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1280 v_movrelsd_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1281 v_mqsad_pk_u16_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1282 v_mqsad_u32_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1283 v_msad_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1284 v_mul_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1285 v_mul_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1286 v_mul_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1287 v_mul_hi_i32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1288 v_mul_hi_i32_i24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1289 v_mul_hi_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1290 v_mul_hi_u32_u24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1291 v_mul_i32_i24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1292 v_mul_legacy_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1293 v_mul_lo_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1294 v_mul_lo_u32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1295 v_mul_u32_u24_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1296 v_nop_e64 :ref:`omod<amdgpu_synid_omod>` 1297 v_not_b32_e64 dst, src0 :ref:`omod<amdgpu_synid_omod>` 1298 v_or_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1299 v_perm_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1300 v_qsad_pk_u16_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1301 v_rcp_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1302 v_rcp_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1303 v_rcp_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1304 v_rcp_iflag_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1305 v_readlane_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1306 v_rndne_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1307 v_rndne_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1308 v_rndne_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1309 v_rsq_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1310 v_rsq_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1311 v_rsq_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1312 v_sad_hi_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1313 v_sad_u16 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1314 v_sad_u32 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1315 v_sad_u8 dst, src0, src1, src2 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1316 v_sin_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1317 v_sin_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1318 v_sqrt_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1319 v_sqrt_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1320 v_sqrt_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1321 v_sub_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1322 v_sub_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1323 v_sub_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1324 v_sub_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1325 v_subb_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1326 v_subbrev_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>` 1327 v_subrev_f16_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1328 v_subrev_f32_e64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1329 v_subrev_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1330 v_subrev_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1331 v_trig_preop_f64 dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1332 v_trunc_f16_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1333 v_trunc_f32_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1334 v_trunc_f64_e64 dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>` 1335 v_writelane_b32 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1336 v_xor_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>` 1337 1338VOPC 1339=========================== 1340 1341.. parsed-literal:: 1342 1343 v_cmp_class_f16 dst, src0, src1 1344 v_cmp_class_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1345 v_cmp_class_f32 dst, src0, src1 1346 v_cmp_class_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1347 v_cmp_class_f64 dst, src0, src1 1348 v_cmp_eq_f16 dst, src0, src1 1349 v_cmp_eq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1350 v_cmp_eq_f32 dst, src0, src1 1351 v_cmp_eq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1352 v_cmp_eq_f64 dst, src0, src1 1353 v_cmp_eq_i16 dst, src0, src1 1354 v_cmp_eq_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1355 v_cmp_eq_i32 dst, src0, src1 1356 v_cmp_eq_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1357 v_cmp_eq_i64 dst, src0, src1 1358 v_cmp_eq_u16 dst, src0, src1 1359 v_cmp_eq_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1360 v_cmp_eq_u32 dst, src0, src1 1361 v_cmp_eq_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1362 v_cmp_eq_u64 dst, src0, src1 1363 v_cmp_f_f16 dst, src0, src1 1364 v_cmp_f_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1365 v_cmp_f_f32 dst, src0, src1 1366 v_cmp_f_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1367 v_cmp_f_f64 dst, src0, src1 1368 v_cmp_f_i16 dst, src0, src1 1369 v_cmp_f_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1370 v_cmp_f_i32 dst, src0, src1 1371 v_cmp_f_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1372 v_cmp_f_i64 dst, src0, src1 1373 v_cmp_f_u16 dst, src0, src1 1374 v_cmp_f_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1375 v_cmp_f_u32 dst, src0, src1 1376 v_cmp_f_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1377 v_cmp_f_u64 dst, src0, src1 1378 v_cmp_ge_f16 dst, src0, src1 1379 v_cmp_ge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1380 v_cmp_ge_f32 dst, src0, src1 1381 v_cmp_ge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1382 v_cmp_ge_f64 dst, src0, src1 1383 v_cmp_ge_i16 dst, src0, src1 1384 v_cmp_ge_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1385 v_cmp_ge_i32 dst, src0, src1 1386 v_cmp_ge_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1387 v_cmp_ge_i64 dst, src0, src1 1388 v_cmp_ge_u16 dst, src0, src1 1389 v_cmp_ge_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1390 v_cmp_ge_u32 dst, src0, src1 1391 v_cmp_ge_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1392 v_cmp_ge_u64 dst, src0, src1 1393 v_cmp_gt_f16 dst, src0, src1 1394 v_cmp_gt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1395 v_cmp_gt_f32 dst, src0, src1 1396 v_cmp_gt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1397 v_cmp_gt_f64 dst, src0, src1 1398 v_cmp_gt_i16 dst, src0, src1 1399 v_cmp_gt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1400 v_cmp_gt_i32 dst, src0, src1 1401 v_cmp_gt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1402 v_cmp_gt_i64 dst, src0, src1 1403 v_cmp_gt_u16 dst, src0, src1 1404 v_cmp_gt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1405 v_cmp_gt_u32 dst, src0, src1 1406 v_cmp_gt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1407 v_cmp_gt_u64 dst, src0, src1 1408 v_cmp_le_f16 dst, src0, src1 1409 v_cmp_le_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1410 v_cmp_le_f32 dst, src0, src1 1411 v_cmp_le_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1412 v_cmp_le_f64 dst, src0, src1 1413 v_cmp_le_i16 dst, src0, src1 1414 v_cmp_le_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1415 v_cmp_le_i32 dst, src0, src1 1416 v_cmp_le_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1417 v_cmp_le_i64 dst, src0, src1 1418 v_cmp_le_u16 dst, src0, src1 1419 v_cmp_le_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1420 v_cmp_le_u32 dst, src0, src1 1421 v_cmp_le_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1422 v_cmp_le_u64 dst, src0, src1 1423 v_cmp_lg_f16 dst, src0, src1 1424 v_cmp_lg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1425 v_cmp_lg_f32 dst, src0, src1 1426 v_cmp_lg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1427 v_cmp_lg_f64 dst, src0, src1 1428 v_cmp_lt_f16 dst, src0, src1 1429 v_cmp_lt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1430 v_cmp_lt_f32 dst, src0, src1 1431 v_cmp_lt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1432 v_cmp_lt_f64 dst, src0, src1 1433 v_cmp_lt_i16 dst, src0, src1 1434 v_cmp_lt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1435 v_cmp_lt_i32 dst, src0, src1 1436 v_cmp_lt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1437 v_cmp_lt_i64 dst, src0, src1 1438 v_cmp_lt_u16 dst, src0, src1 1439 v_cmp_lt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1440 v_cmp_lt_u32 dst, src0, src1 1441 v_cmp_lt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1442 v_cmp_lt_u64 dst, src0, src1 1443 v_cmp_ne_i16 dst, src0, src1 1444 v_cmp_ne_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1445 v_cmp_ne_i32 dst, src0, src1 1446 v_cmp_ne_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1447 v_cmp_ne_i64 dst, src0, src1 1448 v_cmp_ne_u16 dst, src0, src1 1449 v_cmp_ne_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1450 v_cmp_ne_u32 dst, src0, src1 1451 v_cmp_ne_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1452 v_cmp_ne_u64 dst, src0, src1 1453 v_cmp_neq_f16 dst, src0, src1 1454 v_cmp_neq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1455 v_cmp_neq_f32 dst, src0, src1 1456 v_cmp_neq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1457 v_cmp_neq_f64 dst, src0, src1 1458 v_cmp_nge_f16 dst, src0, src1 1459 v_cmp_nge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1460 v_cmp_nge_f32 dst, src0, src1 1461 v_cmp_nge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1462 v_cmp_nge_f64 dst, src0, src1 1463 v_cmp_ngt_f16 dst, src0, src1 1464 v_cmp_ngt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1465 v_cmp_ngt_f32 dst, src0, src1 1466 v_cmp_ngt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1467 v_cmp_ngt_f64 dst, src0, src1 1468 v_cmp_nle_f16 dst, src0, src1 1469 v_cmp_nle_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1470 v_cmp_nle_f32 dst, src0, src1 1471 v_cmp_nle_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1472 v_cmp_nle_f64 dst, src0, src1 1473 v_cmp_nlg_f16 dst, src0, src1 1474 v_cmp_nlg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1475 v_cmp_nlg_f32 dst, src0, src1 1476 v_cmp_nlg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1477 v_cmp_nlg_f64 dst, src0, src1 1478 v_cmp_nlt_f16 dst, src0, src1 1479 v_cmp_nlt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1480 v_cmp_nlt_f32 dst, src0, src1 1481 v_cmp_nlt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1482 v_cmp_nlt_f64 dst, src0, src1 1483 v_cmp_o_f16 dst, src0, src1 1484 v_cmp_o_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1485 v_cmp_o_f32 dst, src0, src1 1486 v_cmp_o_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1487 v_cmp_o_f64 dst, src0, src1 1488 v_cmp_t_i16 dst, src0, src1 1489 v_cmp_t_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1490 v_cmp_t_i32 dst, src0, src1 1491 v_cmp_t_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1492 v_cmp_t_i64 dst, src0, src1 1493 v_cmp_t_u16 dst, src0, src1 1494 v_cmp_t_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1495 v_cmp_t_u32 dst, src0, src1 1496 v_cmp_t_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1497 v_cmp_t_u64 dst, src0, src1 1498 v_cmp_tru_f16 dst, src0, src1 1499 v_cmp_tru_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1500 v_cmp_tru_f32 dst, src0, src1 1501 v_cmp_tru_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1502 v_cmp_tru_f64 dst, src0, src1 1503 v_cmp_u_f16 dst, src0, src1 1504 v_cmp_u_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1505 v_cmp_u_f32 dst, src0, src1 1506 v_cmp_u_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1507 v_cmp_u_f64 dst, src0, src1 1508 v_cmpx_class_f16 dst, src0, src1 1509 v_cmpx_class_f16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1510 v_cmpx_class_f32 dst, src0, src1 1511 v_cmpx_class_f32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1512 v_cmpx_class_f64 dst, src0, src1 1513 v_cmpx_eq_f16 dst, src0, src1 1514 v_cmpx_eq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1515 v_cmpx_eq_f32 dst, src0, src1 1516 v_cmpx_eq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1517 v_cmpx_eq_f64 dst, src0, src1 1518 v_cmpx_eq_i16 dst, src0, src1 1519 v_cmpx_eq_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1520 v_cmpx_eq_i32 dst, src0, src1 1521 v_cmpx_eq_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1522 v_cmpx_eq_i64 dst, src0, src1 1523 v_cmpx_eq_u16 dst, src0, src1 1524 v_cmpx_eq_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1525 v_cmpx_eq_u32 dst, src0, src1 1526 v_cmpx_eq_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1527 v_cmpx_eq_u64 dst, src0, src1 1528 v_cmpx_f_f16 dst, src0, src1 1529 v_cmpx_f_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1530 v_cmpx_f_f32 dst, src0, src1 1531 v_cmpx_f_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1532 v_cmpx_f_f64 dst, src0, src1 1533 v_cmpx_f_i16 dst, src0, src1 1534 v_cmpx_f_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1535 v_cmpx_f_i32 dst, src0, src1 1536 v_cmpx_f_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1537 v_cmpx_f_i64 dst, src0, src1 1538 v_cmpx_f_u16 dst, src0, src1 1539 v_cmpx_f_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1540 v_cmpx_f_u32 dst, src0, src1 1541 v_cmpx_f_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1542 v_cmpx_f_u64 dst, src0, src1 1543 v_cmpx_ge_f16 dst, src0, src1 1544 v_cmpx_ge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1545 v_cmpx_ge_f32 dst, src0, src1 1546 v_cmpx_ge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1547 v_cmpx_ge_f64 dst, src0, src1 1548 v_cmpx_ge_i16 dst, src0, src1 1549 v_cmpx_ge_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1550 v_cmpx_ge_i32 dst, src0, src1 1551 v_cmpx_ge_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1552 v_cmpx_ge_i64 dst, src0, src1 1553 v_cmpx_ge_u16 dst, src0, src1 1554 v_cmpx_ge_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1555 v_cmpx_ge_u32 dst, src0, src1 1556 v_cmpx_ge_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1557 v_cmpx_ge_u64 dst, src0, src1 1558 v_cmpx_gt_f16 dst, src0, src1 1559 v_cmpx_gt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1560 v_cmpx_gt_f32 dst, src0, src1 1561 v_cmpx_gt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1562 v_cmpx_gt_f64 dst, src0, src1 1563 v_cmpx_gt_i16 dst, src0, src1 1564 v_cmpx_gt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1565 v_cmpx_gt_i32 dst, src0, src1 1566 v_cmpx_gt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1567 v_cmpx_gt_i64 dst, src0, src1 1568 v_cmpx_gt_u16 dst, src0, src1 1569 v_cmpx_gt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1570 v_cmpx_gt_u32 dst, src0, src1 1571 v_cmpx_gt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1572 v_cmpx_gt_u64 dst, src0, src1 1573 v_cmpx_le_f16 dst, src0, src1 1574 v_cmpx_le_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1575 v_cmpx_le_f32 dst, src0, src1 1576 v_cmpx_le_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1577 v_cmpx_le_f64 dst, src0, src1 1578 v_cmpx_le_i16 dst, src0, src1 1579 v_cmpx_le_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1580 v_cmpx_le_i32 dst, src0, src1 1581 v_cmpx_le_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1582 v_cmpx_le_i64 dst, src0, src1 1583 v_cmpx_le_u16 dst, src0, src1 1584 v_cmpx_le_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1585 v_cmpx_le_u32 dst, src0, src1 1586 v_cmpx_le_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1587 v_cmpx_le_u64 dst, src0, src1 1588 v_cmpx_lg_f16 dst, src0, src1 1589 v_cmpx_lg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1590 v_cmpx_lg_f32 dst, src0, src1 1591 v_cmpx_lg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1592 v_cmpx_lg_f64 dst, src0, src1 1593 v_cmpx_lt_f16 dst, src0, src1 1594 v_cmpx_lt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1595 v_cmpx_lt_f32 dst, src0, src1 1596 v_cmpx_lt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1597 v_cmpx_lt_f64 dst, src0, src1 1598 v_cmpx_lt_i16 dst, src0, src1 1599 v_cmpx_lt_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1600 v_cmpx_lt_i32 dst, src0, src1 1601 v_cmpx_lt_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1602 v_cmpx_lt_i64 dst, src0, src1 1603 v_cmpx_lt_u16 dst, src0, src1 1604 v_cmpx_lt_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1605 v_cmpx_lt_u32 dst, src0, src1 1606 v_cmpx_lt_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1607 v_cmpx_lt_u64 dst, src0, src1 1608 v_cmpx_ne_i16 dst, src0, src1 1609 v_cmpx_ne_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1610 v_cmpx_ne_i32 dst, src0, src1 1611 v_cmpx_ne_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1612 v_cmpx_ne_i64 dst, src0, src1 1613 v_cmpx_ne_u16 dst, src0, src1 1614 v_cmpx_ne_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1615 v_cmpx_ne_u32 dst, src0, src1 1616 v_cmpx_ne_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1617 v_cmpx_ne_u64 dst, src0, src1 1618 v_cmpx_neq_f16 dst, src0, src1 1619 v_cmpx_neq_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1620 v_cmpx_neq_f32 dst, src0, src1 1621 v_cmpx_neq_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1622 v_cmpx_neq_f64 dst, src0, src1 1623 v_cmpx_nge_f16 dst, src0, src1 1624 v_cmpx_nge_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1625 v_cmpx_nge_f32 dst, src0, src1 1626 v_cmpx_nge_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1627 v_cmpx_nge_f64 dst, src0, src1 1628 v_cmpx_ngt_f16 dst, src0, src1 1629 v_cmpx_ngt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1630 v_cmpx_ngt_f32 dst, src0, src1 1631 v_cmpx_ngt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1632 v_cmpx_ngt_f64 dst, src0, src1 1633 v_cmpx_nle_f16 dst, src0, src1 1634 v_cmpx_nle_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1635 v_cmpx_nle_f32 dst, src0, src1 1636 v_cmpx_nle_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1637 v_cmpx_nle_f64 dst, src0, src1 1638 v_cmpx_nlg_f16 dst, src0, src1 1639 v_cmpx_nlg_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1640 v_cmpx_nlg_f32 dst, src0, src1 1641 v_cmpx_nlg_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1642 v_cmpx_nlg_f64 dst, src0, src1 1643 v_cmpx_nlt_f16 dst, src0, src1 1644 v_cmpx_nlt_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1645 v_cmpx_nlt_f32 dst, src0, src1 1646 v_cmpx_nlt_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1647 v_cmpx_nlt_f64 dst, src0, src1 1648 v_cmpx_o_f16 dst, src0, src1 1649 v_cmpx_o_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1650 v_cmpx_o_f32 dst, src0, src1 1651 v_cmpx_o_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1652 v_cmpx_o_f64 dst, src0, src1 1653 v_cmpx_t_i16 dst, src0, src1 1654 v_cmpx_t_i16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1655 v_cmpx_t_i32 dst, src0, src1 1656 v_cmpx_t_i32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1657 v_cmpx_t_i64 dst, src0, src1 1658 v_cmpx_t_u16 dst, src0, src1 1659 v_cmpx_t_u16_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1660 v_cmpx_t_u32 dst, src0, src1 1661 v_cmpx_t_u32_sdwa dst, src0, src1 :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1662 v_cmpx_t_u64 dst, src0, src1 1663 v_cmpx_tru_f16 dst, src0, src1 1664 v_cmpx_tru_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1665 v_cmpx_tru_f32 dst, src0, src1 1666 v_cmpx_tru_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1667 v_cmpx_tru_f64 dst, src0, src1 1668 v_cmpx_u_f16 dst, src0, src1 1669 v_cmpx_u_f16_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1670 v_cmpx_u_f32 dst, src0, src1 1671 v_cmpx_u_f32_sdwa dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`src0_sel<amdgpu_synid_src0_sel>` :ref:`src1_sel<amdgpu_synid_src1_sel>` 1672 v_cmpx_u_f64 dst, src0, src1 1673