Searched refs:SOP2 (Results 1 – 14 of 14) sorted by relevance
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 67 SOP2 Instructions
69 All SOP2 instructions are supported.
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 26 field bits<1> SOP2 = 0;
62 let TSFlags{6} = SOP2;
292 class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> :
300 let SOP2 = 1;
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| D | SIDefines.h | 23 SOP2 = 1 << 6, enumerator
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| D | SIInstrInfo.h | 216 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
220 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
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| D | SIInstrInfo.td | 808 SOP2<outs, ins, "", pattern>,
822 SOP2<outs, ins, asm, []>,
831 SOP2<outs, ins, asm, []>,
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| D | SIInstructions.td | 192 // SOP2 Instructions
2437 // SOP2 Patterns
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrFormats.td | 33 field bit SOP2 = 0;
129 let TSFlags{3} = SOP2;
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| D | SIDefines.h | 27 SOP2 = 1 << 3, enumerator
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| D | SIInstrInfo.h | 333 return MI.getDesc().TSFlags & SIInstrFlags::SOP2; in isSOP2()
337 return get(Opcode).TSFlags & SIInstrFlags::SOP2; in isSOP2()
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| D | SOPInstructions.td | 270 // SOP2 Instructions
281 let SOP2 = 1;
1030 // SOP2 Patterns
1369 // SOP2 - GFX9.
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| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUUsage.rst | 4200 SOP2 subsubsection
4215 For full list of supported instructions, refer to "SOP2 Instructions" in ISA Manual.
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| D | AMDGPUAsmGFX7.rst | 419 SOP2 chapter
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| D | AMDGPUAsmGFX8.rst | 437 SOP2 chapter
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| D | AMDGPUAsmGFX9.rst | 580 SOP2 chapter
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