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Searched refs:ShiftType (Results 1 – 25 of 47) sorted by relevance

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/external/pdfium/third_party/base/numerics/
Dsafe_math_impl.h309 using ShiftType = typename std::make_unsigned<T>::type;
310 static const ShiftType kBitWidth = IntegerBitsPlusSign<T>::value;
311 const auto real_shift = static_cast<ShiftType>(shift);
339 using ShiftType = typename std::make_unsigned<T>::type;
340 if (static_cast<ShiftType>(shift) < IntegerBitsPlusSign<T>::value) {
/external/vixl/src/aarch32/
Dinstructions-aarch32.h1051 enum ShiftType { LSL = 0x0, LSR = 0x1, ASR = 0x2, ROR = 0x3, RRX = 0x4 }; enum
1056 Shift(ShiftType shift) : shift_(shift) {} // NOLINT(runtime/explicit) in Shift()
1057 explicit Shift(uint32_t shift) : shift_(static_cast<ShiftType>(shift)) {} in Shift()
1059 ShiftType GetType() const { return shift_; } in GetType()
1073 void SetType(ShiftType s) { shift_ = s; } in SetType()
1076 ShiftType shift_;
1132 RegisterShiftOperand(ShiftType shift, Register shift_register) in RegisterShiftOperand()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
333 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg member
708 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
740 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
746 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
761 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
763 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
771 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
1176 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
1326 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
[all …]
/external/vixl/test/aarch32/
Dtest-simulator-cond-rd-operand-rn-ror-amount-a32.cc139 ShiftType ror;
597 ShiftType ror = kTests[i].operands.ror; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-ror-amount-t32.cc139 ShiftType ror;
597 ShiftType ror = kTests[i].operands.ror; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-a32.cc141 ShiftType shift;
901 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-t32.cc141 ShiftType shift;
891 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to32-t32.cc141 ShiftType shift;
901 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-amount-1to31-a32.cc141 ShiftType shift;
891 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-a32.cc140 ShiftType ror;
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper()
Dtest-assembler-cond-rd-operand-rn-shift-rs-narrow-out-it-block-t32.cc68 ShiftType shift;
378 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-rn-operand-rm-ror-amount-t32.cc140 ShiftType ror;
1131 ShiftType ror = kTests[i].operands.ror; in TestHelper()
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc154 ShiftType shift;
1449 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc154 ShiftType shift;
1449 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc154 ShiftType shift;
1459 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc154 ShiftType shift;
1459 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-rs-t32.cc135 ShiftType shift;
1086 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-simulator-cond-rd-operand-rn-shift-rs-a32.cc141 ShiftType shift;
1098 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-in-it-block-t32.cc68 ShiftType shift;
622 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-t32.cc76 ShiftType shift;
841 ShiftType shift = kTests[i].operands.shift; in TestHelper()
Dtest-assembler-cond-rd-operand-rn-shift-amount-1to32-a32.cc76 ShiftType shift;
813 ShiftType shift = kTests[i].operands.shift; in TestHelper()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp213 AArch64_AM::ShiftExtendType ShiftType,
247 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
1246 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend; in emitAddSub() local
1249 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break; in emitAddSub()
1250 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break; in emitAddSub()
1251 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break; in emitAddSub()
1254 if (ShiftType != AArch64_AM::InvalidShiftExtend) { in emitAddSub()
1260 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1367 AArch64_AM::ShiftExtendType ShiftType, in emitAddSub_rs() argument
1403 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp169 AArch64_AM::ShiftExtendType ShiftType,
201 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
1200 AArch64_AM::ShiftExtendType ShiftType = AArch64_AM::InvalidShiftExtend; in emitAddSub() local
1203 case Instruction::Shl: ShiftType = AArch64_AM::LSL; break; in emitAddSub()
1204 case Instruction::LShr: ShiftType = AArch64_AM::LSR; break; in emitAddSub()
1205 case Instruction::AShr: ShiftType = AArch64_AM::ASR; break; in emitAddSub()
1208 if (ShiftType != AArch64_AM::InvalidShiftExtend) { in emitAddSub()
1214 RHSIsKill, ShiftType, ShiftVal, SetFlags, in emitAddSub()
1317 AArch64_AM::ShiftExtendType ShiftType, in emitAddSub_rs() argument
1351 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
[all …]
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
515 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg member
1195 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1248 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1254 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1269 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1271 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1279 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2131 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
2340 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp389 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
749 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg member
1364 if (Memory.ShiftType != ARM_AM::no_shift) return false; in isAddrMode3()
1424 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemTBB()
1431 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 || in isMemTBH()
1448 if (Memory.ShiftType == ARM_AM::no_shift) in isT2MemRegOffset()
1450 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3) in isT2MemRegOffset()
1459 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0) in isMemThumbRR()
2403 Memory.ShiftImm, Memory.ShiftType); in addAddrMode2Operands()
2612 Memory.ShiftImm, Memory.ShiftType); in addMemRegOffsetOperands()
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