1 // Copyright 2016, VIXL authors
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are met:
6 //
7 // * Redistributions of source code must retain the above copyright notice,
8 // this list of conditions and the following disclaimer.
9 // * Redistributions in binary form must reproduce the above copyright notice,
10 // this list of conditions and the following disclaimer in the documentation
11 // and/or other materials provided with the distribution.
12 // * Neither the name of ARM Limited nor the names of its contributors may be
13 // used to endorse or promote products derived from this software without
14 // specific prior written permission.
15 //
16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
27
28 // -----------------------------------------------------------------------------
29 // This file is auto generated from the
30 // test/aarch32/config/template-simulator-aarch32.cc.in template file using
31 // tools/generate_tests.py.
32 //
33 // PLEASE DO NOT EDIT.
34 // -----------------------------------------------------------------------------
35
36
37 #include "test-runner.h"
38
39 #include "test-utils.h"
40 #include "test-utils-aarch32.h"
41
42 #include "aarch32/assembler-aarch32.h"
43 #include "aarch32/disasm-aarch32.h"
44 #include "aarch32/macro-assembler-aarch32.h"
45
46 #define __ masm.
47 #define BUF_SIZE (4096)
48
49 #ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
50 // Run tests with the simulator.
51
52 #define SETUP() MacroAssembler masm(BUF_SIZE)
53
54 #define START() masm.GetBuffer()->Reset()
55
56 #define END() \
57 __ Hlt(0); \
58 __ FinalizeCode();
59
60 // TODO: Run the tests in the simulator.
61 #define RUN()
62
63 #else // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32.
64
65 #define SETUP() \
66 MacroAssembler masm(BUF_SIZE); \
67 UseScratchRegisterScope harness_scratch;
68
69 #define START() \
70 harness_scratch.Open(&masm); \
71 harness_scratch.ExcludeAll(); \
72 masm.GetBuffer()->Reset(); \
73 __ Push(r4); \
74 __ Push(r5); \
75 __ Push(r6); \
76 __ Push(r7); \
77 __ Push(r8); \
78 __ Push(r9); \
79 __ Push(r10); \
80 __ Push(r11); \
81 __ Push(lr); \
82 harness_scratch.Include(ip);
83
84 #define END() \
85 harness_scratch.Exclude(ip); \
86 __ Pop(lr); \
87 __ Pop(r11); \
88 __ Pop(r10); \
89 __ Pop(r9); \
90 __ Pop(r8); \
91 __ Pop(r7); \
92 __ Pop(r6); \
93 __ Pop(r5); \
94 __ Pop(r4); \
95 __ Bx(lr); \
96 __ FinalizeCode(); \
97 harness_scratch.Close();
98
99 #define RUN() \
100 { \
101 int pcs_offset = masm.IsUsingT32() ? 1 : 0; \
102 masm.GetBuffer()->SetExecutable(); \
103 ExecuteMemory(masm.GetBuffer()->GetStartAddress<byte*>(), \
104 masm.GetSizeOfCodeGenerated(), \
105 pcs_offset); \
106 masm.GetBuffer()->SetWritable(); \
107 }
108
109 #endif // ifdef VIXL_INCLUDE_SIMULATOR_AARCH32
110
111 namespace vixl {
112 namespace aarch32 {
113
114 // List of instruction encodings:
115 #define FOREACH_INSTRUCTION(M) \
116 M(Cmn) \
117 M(Cmp) \
118 M(Mov) \
119 M(Movs) \
120 M(Mvn) \
121 M(Mvns) \
122 M(Teq) \
123 M(Tst)
124
125
126 // The following definitions are defined again in each generated test, therefore
127 // we need to place them in an anomymous namespace. It expresses that they are
128 // local to this file only, and the compiler is not allowed to share these types
129 // across test files during template instantiation. Specifically, `Operands` and
130 // `Inputs` have various layouts across generated tests so they absolutely
131 // cannot be shared.
132
133 #ifdef VIXL_INCLUDE_TARGET_T32
134 namespace {
135
136 // Values to be passed to the assembler to produce the instruction under test.
137 struct Operands {
138 Condition cond;
139 Register rd;
140 Register rn;
141 ShiftType shift;
142 uint32_t amount;
143 };
144
145 // Input data to feed to the instruction.
146 struct Inputs {
147 uint32_t apsr;
148 uint32_t rd;
149 uint32_t rn;
150 };
151
152 // This structure contains all input data needed to test one specific encoding.
153 // It used to generate a loop over an instruction.
154 struct TestLoopData {
155 // The `operands` fields represents the values to pass to the assembler to
156 // produce the instruction.
157 Operands operands;
158 // Description of the operands, used for error reporting.
159 const char* operands_description;
160 // Unique identifier, used for generating traces.
161 const char* identifier;
162 // Array of values to be fed to the instruction.
163 size_t input_size;
164 const Inputs* inputs;
165 };
166
167 static const Inputs kCondition[] = {{NFlag, 0xabababab, 0xabababab},
168 {ZFlag, 0xabababab, 0xabababab},
169 {CFlag, 0xabababab, 0xabababab},
170 {VFlag, 0xabababab, 0xabababab},
171 {NZFlag, 0xabababab, 0xabababab},
172 {NCFlag, 0xabababab, 0xabababab},
173 {NVFlag, 0xabababab, 0xabababab},
174 {ZCFlag, 0xabababab, 0xabababab},
175 {ZVFlag, 0xabababab, 0xabababab},
176 {CVFlag, 0xabababab, 0xabababab},
177 {NZCFlag, 0xabababab, 0xabababab},
178 {NZVFlag, 0xabababab, 0xabababab},
179 {NCVFlag, 0xabababab, 0xabababab},
180 {ZCVFlag, 0xabababab, 0xabababab},
181 {NZCVFlag, 0xabababab, 0xabababab}};
182
183 static const Inputs kRdIsRn[] =
184 {{NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x00000001, 0x00000001},
185 {NoFlag, 0x00000002, 0x00000002}, {NoFlag, 0x00000020, 0x00000020},
186 {NoFlag, 0x0000007d, 0x0000007d}, {NoFlag, 0x0000007e, 0x0000007e},
187 {NoFlag, 0x0000007f, 0x0000007f}, {NoFlag, 0x00007ffd, 0x00007ffd},
188 {NoFlag, 0x00007ffe, 0x00007ffe}, {NoFlag, 0x00007fff, 0x00007fff},
189 {NoFlag, 0x33333333, 0x33333333}, {NoFlag, 0x55555555, 0x55555555},
190 {NoFlag, 0x7ffffffd, 0x7ffffffd}, {NoFlag, 0x7ffffffe, 0x7ffffffe},
191 {NoFlag, 0x7fffffff, 0x7fffffff}, {NoFlag, 0x80000000, 0x80000000},
192 {NoFlag, 0x80000001, 0x80000001}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
193 {NoFlag, 0xcccccccc, 0xcccccccc}, {NoFlag, 0xffff8000, 0xffff8000},
194 {NoFlag, 0xffff8001, 0xffff8001}, {NoFlag, 0xffff8002, 0xffff8002},
195 {NoFlag, 0xffff8003, 0xffff8003}, {NoFlag, 0xffffff80, 0xffffff80},
196 {NoFlag, 0xffffff81, 0xffffff81}, {NoFlag, 0xffffff82, 0xffffff82},
197 {NoFlag, 0xffffff83, 0xffffff83}, {NoFlag, 0xffffffe0, 0xffffffe0},
198 {NoFlag, 0xfffffffd, 0xfffffffd}, {NoFlag, 0xfffffffe, 0xfffffffe},
199 {NoFlag, 0xffffffff, 0xffffffff}};
200
201 static const Inputs kRdIsNotRn[] =
202 {{NoFlag, 0x00000002, 0xcccccccc}, {NoFlag, 0x7ffffffd, 0x00007ffe},
203 {NoFlag, 0xffffff80, 0x00000020}, {NoFlag, 0xaaaaaaaa, 0xaaaaaaaa},
204 {NoFlag, 0x33333333, 0xffffff82}, {NoFlag, 0xffff8001, 0x7ffffffe},
205 {NoFlag, 0xfffffffd, 0x00007ffe}, {NoFlag, 0xffffff80, 0x80000000},
206 {NoFlag, 0x00000001, 0x33333333}, {NoFlag, 0xcccccccc, 0x7ffffffe},
207 {NoFlag, 0x00000000, 0xcccccccc}, {NoFlag, 0x00000000, 0x55555555},
208 {NoFlag, 0xffffffff, 0xffffffff}, {NoFlag, 0x0000007e, 0xffff8002},
209 {NoFlag, 0x80000000, 0x7ffffffd}, {NoFlag, 0xffffff81, 0x0000007e},
210 {NoFlag, 0x0000007f, 0xffff8001}, {NoFlag, 0xffffffe0, 0x00007ffd},
211 {NoFlag, 0xffff8003, 0x00000002}, {NoFlag, 0xffffff83, 0x55555555},
212 {NoFlag, 0xffffff83, 0xffffff80}, {NoFlag, 0xffffff81, 0xffff8000},
213 {NoFlag, 0x00000020, 0x7ffffffe}, {NoFlag, 0xffffffe0, 0x00000000},
214 {NoFlag, 0x7fffffff, 0x0000007e}, {NoFlag, 0x80000001, 0xffffffff},
215 {NoFlag, 0x00000001, 0x80000001}, {NoFlag, 0x00000002, 0x0000007f},
216 {NoFlag, 0x7fffffff, 0xcccccccc}, {NoFlag, 0x80000001, 0x00007ffe},
217 {NoFlag, 0xffff8002, 0x0000007e}, {NoFlag, 0x00007ffe, 0xcccccccc},
218 {NoFlag, 0x80000000, 0xffff8002}, {NoFlag, 0xffffff83, 0x7ffffffe},
219 {NoFlag, 0xffff8001, 0x00000001}, {NoFlag, 0xffffff81, 0x00000020},
220 {NoFlag, 0xfffffffe, 0xffff8001}, {NoFlag, 0xffffffff, 0xfffffffe},
221 {NoFlag, 0xcccccccc, 0x55555555}, {NoFlag, 0x00000020, 0xffffff83},
222 {NoFlag, 0xffffff83, 0xffff8001}, {NoFlag, 0xffffff83, 0xffff8000},
223 {NoFlag, 0x00007fff, 0x00000002}, {NoFlag, 0x55555555, 0xffff8000},
224 {NoFlag, 0x80000001, 0xffffff81}, {NoFlag, 0x00000002, 0x00000000},
225 {NoFlag, 0x33333333, 0xffffff81}, {NoFlag, 0xffff8001, 0xffffff82},
226 {NoFlag, 0xcccccccc, 0xffff8003}, {NoFlag, 0xffff8003, 0x7ffffffd},
227 {NoFlag, 0x0000007d, 0x00007ffe}, {NoFlag, 0xffffff80, 0x0000007d},
228 {NoFlag, 0xaaaaaaaa, 0x00007ffd}, {NoFlag, 0x80000000, 0xffffff82},
229 {NoFlag, 0x00000002, 0x7ffffffe}, {NoFlag, 0x00000002, 0xffffff83},
230 {NoFlag, 0x55555555, 0x00000002}, {NoFlag, 0xffffffff, 0xffffff82},
231 {NoFlag, 0xaaaaaaaa, 0x00000020}, {NoFlag, 0x00000001, 0xffffff82},
232 {NoFlag, 0x0000007f, 0xffffff82}, {NoFlag, 0x7ffffffd, 0xaaaaaaaa},
233 {NoFlag, 0x00007ffe, 0x00000001}, {NoFlag, 0xfffffffd, 0xffffffe0},
234 {NoFlag, 0xffffff81, 0xffffff83}, {NoFlag, 0x0000007d, 0x00000000},
235 {NoFlag, 0x0000007d, 0xffff8000}, {NoFlag, 0xffffff81, 0x7fffffff},
236 {NoFlag, 0xffffffff, 0x80000000}, {NoFlag, 0x00000000, 0x00000001},
237 {NoFlag, 0x55555555, 0xffffff82}, {NoFlag, 0x00007ffe, 0x00007ffe},
238 {NoFlag, 0x80000001, 0xfffffffd}, {NoFlag, 0x00007fff, 0x33333333},
239 {NoFlag, 0x00007fff, 0x80000000}, {NoFlag, 0xcccccccc, 0x00007fff},
240 {NoFlag, 0xfffffffe, 0xffffffe0}, {NoFlag, 0x7ffffffe, 0x0000007f},
241 {NoFlag, 0x00007ffd, 0xffff8001}, {NoFlag, 0x00000002, 0x00000001},
242 {NoFlag, 0x80000000, 0xffffffff}, {NoFlag, 0xffffff83, 0xcccccccc},
243 {NoFlag, 0xffff8002, 0x7ffffffe}, {NoFlag, 0xaaaaaaaa, 0x00000000},
244 {NoFlag, 0xffffff80, 0xcccccccc}, {NoFlag, 0x33333333, 0xffffff83},
245 {NoFlag, 0x0000007e, 0xffffffe0}, {NoFlag, 0x0000007e, 0x00007fff},
246 {NoFlag, 0x0000007f, 0x00000002}, {NoFlag, 0x7ffffffe, 0xcccccccc},
247 {NoFlag, 0x0000007d, 0xffffff80}, {NoFlag, 0x00007fff, 0x00000020},
248 {NoFlag, 0x7ffffffe, 0xfffffffe}, {NoFlag, 0xfffffffe, 0xffffff81},
249 {NoFlag, 0xffffffff, 0x0000007f}, {NoFlag, 0xffff8002, 0x7ffffffd},
250 {NoFlag, 0xffff8001, 0xfffffffe}, {NoFlag, 0x33333333, 0xffff8002},
251 {NoFlag, 0x00000000, 0xffffffff}, {NoFlag, 0x33333333, 0xffffff80},
252 {NoFlag, 0x0000007f, 0x00007fff}, {NoFlag, 0xffffffff, 0xffff8001},
253 {NoFlag, 0x7fffffff, 0xffff8002}, {NoFlag, 0x7ffffffd, 0xffffff83},
254 {NoFlag, 0x7fffffff, 0x0000007f}, {NoFlag, 0xffffff83, 0xfffffffe},
255 {NoFlag, 0x7ffffffe, 0xffff8003}, {NoFlag, 0xffff8002, 0xffff8002},
256 {NoFlag, 0x80000001, 0x0000007f}, {NoFlag, 0x00000020, 0x00000002},
257 {NoFlag, 0xffffff82, 0xffff8001}, {NoFlag, 0xffffffff, 0x00000001},
258 {NoFlag, 0xffffff80, 0xffff8002}, {NoFlag, 0xffff8003, 0x7fffffff},
259 {NoFlag, 0xffffffff, 0xffff8000}, {NoFlag, 0xffff8002, 0x00007ffd},
260 {NoFlag, 0x00000020, 0xffffff81}, {NoFlag, 0x00000001, 0x55555555},
261 {NoFlag, 0x7ffffffe, 0x00000020}, {NoFlag, 0x80000000, 0x00000001},
262 {NoFlag, 0x00007ffd, 0xffff8002}, {NoFlag, 0x7fffffff, 0xfffffffe},
263 {NoFlag, 0xcccccccc, 0x00007ffd}, {NoFlag, 0x00000000, 0xfffffffd},
264 {NoFlag, 0xffff8003, 0xffffff80}, {NoFlag, 0x80000001, 0xffffff80},
265 {NoFlag, 0xffffffff, 0xffff8002}, {NoFlag, 0x00007ffe, 0xffff8002},
266 {NoFlag, 0xffffff80, 0x00007ffe}, {NoFlag, 0x80000001, 0xffff8001},
267 {NoFlag, 0x0000007f, 0xffffff80}, {NoFlag, 0xffffff81, 0x80000000},
268 {NoFlag, 0x00007fff, 0x00007ffe}, {NoFlag, 0x33333333, 0xffff8000},
269 {NoFlag, 0x33333333, 0x00007fff}, {NoFlag, 0x00000000, 0x0000007d},
270 {NoFlag, 0x80000001, 0x00000000}, {NoFlag, 0xffffffff, 0x55555555},
271 {NoFlag, 0x80000001, 0x80000000}, {NoFlag, 0xffffffff, 0xffffff80},
272 {NoFlag, 0xffffff81, 0xffff8003}, {NoFlag, 0x55555555, 0x80000001},
273 {NoFlag, 0x7fffffff, 0xffff8001}, {NoFlag, 0xffffff83, 0x00000002},
274 {NoFlag, 0x0000007e, 0xffffff81}, {NoFlag, 0x80000000, 0xffff8001},
275 {NoFlag, 0xffffff80, 0xfffffffe}, {NoFlag, 0x0000007e, 0xfffffffd},
276 {NoFlag, 0xffffffe0, 0xffffffff}, {NoFlag, 0x55555555, 0x80000000},
277 {NoFlag, 0x0000007d, 0x80000001}, {NoFlag, 0xffffffe0, 0x7ffffffd},
278 {NoFlag, 0x00000000, 0x00000000}, {NoFlag, 0x55555555, 0x00000001},
279 {NoFlag, 0x00007ffd, 0x7fffffff}, {NoFlag, 0x55555555, 0xffffffff},
280 {NoFlag, 0xffff8003, 0x00007fff}, {NoFlag, 0xffffff82, 0x00007fff},
281 {NoFlag, 0x33333333, 0x55555555}, {NoFlag, 0x00000020, 0x33333333},
282 {NoFlag, 0x7ffffffe, 0xfffffffd}, {NoFlag, 0x7ffffffe, 0x00000001},
283 {NoFlag, 0xffffff83, 0xffffffe0}, {NoFlag, 0xfffffffe, 0xaaaaaaaa},
284 {NoFlag, 0xffff8002, 0x33333333}, {NoFlag, 0xffff8002, 0xffff8003},
285 {NoFlag, 0x33333333, 0x7fffffff}, {NoFlag, 0xfffffffd, 0xffffff83},
286 {NoFlag, 0x00000000, 0xffff8000}, {NoFlag, 0xffffff82, 0x55555555},
287 {NoFlag, 0xffffff82, 0xffffff81}, {NoFlag, 0xcccccccc, 0xfffffffe},
288 {NoFlag, 0xfffffffd, 0x7fffffff}, {NoFlag, 0x00007fff, 0x7fffffff},
289 {NoFlag, 0xffffff83, 0xffff8003}, {NoFlag, 0xfffffffe, 0xffffffff},
290 {NoFlag, 0x7ffffffd, 0x00007ffd}, {NoFlag, 0x7ffffffd, 0x00007fff},
291 {NoFlag, 0x00007ffd, 0xffffffff}, {NoFlag, 0x00000001, 0xffff8003},
292 {NoFlag, 0xffffff80, 0xfffffffd}, {NoFlag, 0x33333333, 0x80000000},
293 {NoFlag, 0xffff8001, 0x00000020}, {NoFlag, 0xcccccccc, 0x00000002},
294 {NoFlag, 0x00000000, 0x00000002}, {NoFlag, 0x0000007d, 0x00007fff},
295 {NoFlag, 0xcccccccc, 0x00000001}, {NoFlag, 0xffffff83, 0x00007fff},
296 {NoFlag, 0x80000001, 0x00000020}, {NoFlag, 0xffff8003, 0xffffffe0},
297 {NoFlag, 0x00007ffd, 0xaaaaaaaa}, {NoFlag, 0x33333333, 0xffff8001},
298 {NoFlag, 0xffffff83, 0x80000001}, {NoFlag, 0xffff8000, 0xffff8000},
299 {NoFlag, 0x00007ffe, 0xffff8001}, {NoFlag, 0x7ffffffd, 0x00000000},
300 {NoFlag, 0x00007ffe, 0x33333333}, {NoFlag, 0xffff8001, 0xffffff80},
301 {NoFlag, 0xfffffffe, 0x55555555}, {NoFlag, 0xffffff82, 0xffffffff}};
302
303 static const Inputs kShiftTypes[] =
304 {{NoFlag, 0xabababab, 0x00000000}, {NoFlag, 0xabababab, 0x00000001},
305 {NoFlag, 0xabababab, 0x00000002}, {NoFlag, 0xabababab, 0x00000020},
306 {NoFlag, 0xabababab, 0x0000007d}, {NoFlag, 0xabababab, 0x0000007e},
307 {NoFlag, 0xabababab, 0x0000007f}, {NoFlag, 0xabababab, 0x00007ffd},
308 {NoFlag, 0xabababab, 0x00007ffe}, {NoFlag, 0xabababab, 0x00007fff},
309 {NoFlag, 0xabababab, 0x33333333}, {NoFlag, 0xabababab, 0x55555555},
310 {NoFlag, 0xabababab, 0x7ffffffd}, {NoFlag, 0xabababab, 0x7ffffffe},
311 {NoFlag, 0xabababab, 0x7fffffff}, {NoFlag, 0xabababab, 0x80000000},
312 {NoFlag, 0xabababab, 0x80000001}, {NoFlag, 0xabababab, 0xaaaaaaaa},
313 {NoFlag, 0xabababab, 0xcccccccc}, {NoFlag, 0xabababab, 0xffff8000},
314 {NoFlag, 0xabababab, 0xffff8001}, {NoFlag, 0xabababab, 0xffff8002},
315 {NoFlag, 0xabababab, 0xffff8003}, {NoFlag, 0xabababab, 0xffffff80},
316 {NoFlag, 0xabababab, 0xffffff81}, {NoFlag, 0xabababab, 0xffffff82},
317 {NoFlag, 0xabababab, 0xffffff83}, {NoFlag, 0xabababab, 0xffffffe0},
318 {NoFlag, 0xabababab, 0xfffffffd}, {NoFlag, 0xabababab, 0xfffffffe},
319 {NoFlag, 0xabababab, 0xffffffff}};
320
321
322 // A loop will be generated for each element of this array.
323 const TestLoopData kTests[] = {{{eq, r0, r0, LSR, 1},
324 "eq r0 r0 LSR 1",
325 "Condition_eq_r0_r0_LSR_1",
326 ARRAY_SIZE(kCondition),
327 kCondition},
328 {{ne, r0, r0, LSR, 1},
329 "ne r0 r0 LSR 1",
330 "Condition_ne_r0_r0_LSR_1",
331 ARRAY_SIZE(kCondition),
332 kCondition},
333 {{cs, r0, r0, LSR, 1},
334 "cs r0 r0 LSR 1",
335 "Condition_cs_r0_r0_LSR_1",
336 ARRAY_SIZE(kCondition),
337 kCondition},
338 {{cc, r0, r0, LSR, 1},
339 "cc r0 r0 LSR 1",
340 "Condition_cc_r0_r0_LSR_1",
341 ARRAY_SIZE(kCondition),
342 kCondition},
343 {{mi, r0, r0, LSR, 1},
344 "mi r0 r0 LSR 1",
345 "Condition_mi_r0_r0_LSR_1",
346 ARRAY_SIZE(kCondition),
347 kCondition},
348 {{pl, r0, r0, LSR, 1},
349 "pl r0 r0 LSR 1",
350 "Condition_pl_r0_r0_LSR_1",
351 ARRAY_SIZE(kCondition),
352 kCondition},
353 {{vs, r0, r0, LSR, 1},
354 "vs r0 r0 LSR 1",
355 "Condition_vs_r0_r0_LSR_1",
356 ARRAY_SIZE(kCondition),
357 kCondition},
358 {{vc, r0, r0, LSR, 1},
359 "vc r0 r0 LSR 1",
360 "Condition_vc_r0_r0_LSR_1",
361 ARRAY_SIZE(kCondition),
362 kCondition},
363 {{hi, r0, r0, LSR, 1},
364 "hi r0 r0 LSR 1",
365 "Condition_hi_r0_r0_LSR_1",
366 ARRAY_SIZE(kCondition),
367 kCondition},
368 {{ls, r0, r0, LSR, 1},
369 "ls r0 r0 LSR 1",
370 "Condition_ls_r0_r0_LSR_1",
371 ARRAY_SIZE(kCondition),
372 kCondition},
373 {{ge, r0, r0, LSR, 1},
374 "ge r0 r0 LSR 1",
375 "Condition_ge_r0_r0_LSR_1",
376 ARRAY_SIZE(kCondition),
377 kCondition},
378 {{lt, r0, r0, LSR, 1},
379 "lt r0 r0 LSR 1",
380 "Condition_lt_r0_r0_LSR_1",
381 ARRAY_SIZE(kCondition),
382 kCondition},
383 {{gt, r0, r0, LSR, 1},
384 "gt r0 r0 LSR 1",
385 "Condition_gt_r0_r0_LSR_1",
386 ARRAY_SIZE(kCondition),
387 kCondition},
388 {{le, r0, r0, LSR, 1},
389 "le r0 r0 LSR 1",
390 "Condition_le_r0_r0_LSR_1",
391 ARRAY_SIZE(kCondition),
392 kCondition},
393 {{al, r0, r0, LSR, 1},
394 "al r0 r0 LSR 1",
395 "Condition_al_r0_r0_LSR_1",
396 ARRAY_SIZE(kCondition),
397 kCondition},
398 {{al, r0, r0, LSR, 1},
399 "al r0 r0 LSR 1",
400 "RdIsRn_al_r0_r0_LSR_1",
401 ARRAY_SIZE(kRdIsRn),
402 kRdIsRn},
403 {{al, r1, r1, LSR, 1},
404 "al r1 r1 LSR 1",
405 "RdIsRn_al_r1_r1_LSR_1",
406 ARRAY_SIZE(kRdIsRn),
407 kRdIsRn},
408 {{al, r2, r2, LSR, 1},
409 "al r2 r2 LSR 1",
410 "RdIsRn_al_r2_r2_LSR_1",
411 ARRAY_SIZE(kRdIsRn),
412 kRdIsRn},
413 {{al, r3, r3, LSR, 1},
414 "al r3 r3 LSR 1",
415 "RdIsRn_al_r3_r3_LSR_1",
416 ARRAY_SIZE(kRdIsRn),
417 kRdIsRn},
418 {{al, r4, r4, LSR, 1},
419 "al r4 r4 LSR 1",
420 "RdIsRn_al_r4_r4_LSR_1",
421 ARRAY_SIZE(kRdIsRn),
422 kRdIsRn},
423 {{al, r5, r5, LSR, 1},
424 "al r5 r5 LSR 1",
425 "RdIsRn_al_r5_r5_LSR_1",
426 ARRAY_SIZE(kRdIsRn),
427 kRdIsRn},
428 {{al, r6, r6, LSR, 1},
429 "al r6 r6 LSR 1",
430 "RdIsRn_al_r6_r6_LSR_1",
431 ARRAY_SIZE(kRdIsRn),
432 kRdIsRn},
433 {{al, r7, r7, LSR, 1},
434 "al r7 r7 LSR 1",
435 "RdIsRn_al_r7_r7_LSR_1",
436 ARRAY_SIZE(kRdIsRn),
437 kRdIsRn},
438 {{al, r8, r8, LSR, 1},
439 "al r8 r8 LSR 1",
440 "RdIsRn_al_r8_r8_LSR_1",
441 ARRAY_SIZE(kRdIsRn),
442 kRdIsRn},
443 {{al, r9, r9, LSR, 1},
444 "al r9 r9 LSR 1",
445 "RdIsRn_al_r9_r9_LSR_1",
446 ARRAY_SIZE(kRdIsRn),
447 kRdIsRn},
448 {{al, r10, r10, LSR, 1},
449 "al r10 r10 LSR 1",
450 "RdIsRn_al_r10_r10_LSR_1",
451 ARRAY_SIZE(kRdIsRn),
452 kRdIsRn},
453 {{al, r11, r11, LSR, 1},
454 "al r11 r11 LSR 1",
455 "RdIsRn_al_r11_r11_LSR_1",
456 ARRAY_SIZE(kRdIsRn),
457 kRdIsRn},
458 {{al, r12, r12, LSR, 1},
459 "al r12 r12 LSR 1",
460 "RdIsRn_al_r12_r12_LSR_1",
461 ARRAY_SIZE(kRdIsRn),
462 kRdIsRn},
463 {{al, r14, r14, LSR, 1},
464 "al r14 r14 LSR 1",
465 "RdIsRn_al_r14_r14_LSR_1",
466 ARRAY_SIZE(kRdIsRn),
467 kRdIsRn},
468 {{al, r1, r8, LSR, 1},
469 "al r1 r8 LSR 1",
470 "RdIsNotRn_al_r1_r8_LSR_1",
471 ARRAY_SIZE(kRdIsNotRn),
472 kRdIsNotRn},
473 {{al, r7, r4, LSR, 1},
474 "al r7 r4 LSR 1",
475 "RdIsNotRn_al_r7_r4_LSR_1",
476 ARRAY_SIZE(kRdIsNotRn),
477 kRdIsNotRn},
478 {{al, r14, r10, LSR, 1},
479 "al r14 r10 LSR 1",
480 "RdIsNotRn_al_r14_r10_LSR_1",
481 ARRAY_SIZE(kRdIsNotRn),
482 kRdIsNotRn},
483 {{al, r10, r6, LSR, 1},
484 "al r10 r6 LSR 1",
485 "RdIsNotRn_al_r10_r6_LSR_1",
486 ARRAY_SIZE(kRdIsNotRn),
487 kRdIsNotRn},
488 {{al, r6, r5, LSR, 1},
489 "al r6 r5 LSR 1",
490 "RdIsNotRn_al_r6_r5_LSR_1",
491 ARRAY_SIZE(kRdIsNotRn),
492 kRdIsNotRn},
493 {{al, r12, r2, LSR, 1},
494 "al r12 r2 LSR 1",
495 "RdIsNotRn_al_r12_r2_LSR_1",
496 ARRAY_SIZE(kRdIsNotRn),
497 kRdIsNotRn},
498 {{al, r0, r11, LSR, 1},
499 "al r0 r11 LSR 1",
500 "RdIsNotRn_al_r0_r11_LSR_1",
501 ARRAY_SIZE(kRdIsNotRn),
502 kRdIsNotRn},
503 {{al, r10, r14, LSR, 1},
504 "al r10 r14 LSR 1",
505 "RdIsNotRn_al_r10_r14_LSR_1",
506 ARRAY_SIZE(kRdIsNotRn),
507 kRdIsNotRn},
508 {{al, r0, r5, LSR, 1},
509 "al r0 r5 LSR 1",
510 "RdIsNotRn_al_r0_r5_LSR_1",
511 ARRAY_SIZE(kRdIsNotRn),
512 kRdIsNotRn},
513 {{al, r0, r3, LSR, 1},
514 "al r0 r3 LSR 1",
515 "RdIsNotRn_al_r0_r3_LSR_1",
516 ARRAY_SIZE(kRdIsNotRn),
517 kRdIsNotRn},
518 {{al, r0, r1, LSR, 1},
519 "al r0 r1 LSR 1",
520 "ShiftTypes_al_r0_r1_LSR_1",
521 ARRAY_SIZE(kShiftTypes),
522 kShiftTypes},
523 {{al, r0, r1, LSR, 2},
524 "al r0 r1 LSR 2",
525 "ShiftTypes_al_r0_r1_LSR_2",
526 ARRAY_SIZE(kShiftTypes),
527 kShiftTypes},
528 {{al, r0, r1, LSR, 3},
529 "al r0 r1 LSR 3",
530 "ShiftTypes_al_r0_r1_LSR_3",
531 ARRAY_SIZE(kShiftTypes),
532 kShiftTypes},
533 {{al, r0, r1, LSR, 4},
534 "al r0 r1 LSR 4",
535 "ShiftTypes_al_r0_r1_LSR_4",
536 ARRAY_SIZE(kShiftTypes),
537 kShiftTypes},
538 {{al, r0, r1, LSR, 5},
539 "al r0 r1 LSR 5",
540 "ShiftTypes_al_r0_r1_LSR_5",
541 ARRAY_SIZE(kShiftTypes),
542 kShiftTypes},
543 {{al, r0, r1, LSR, 6},
544 "al r0 r1 LSR 6",
545 "ShiftTypes_al_r0_r1_LSR_6",
546 ARRAY_SIZE(kShiftTypes),
547 kShiftTypes},
548 {{al, r0, r1, LSR, 7},
549 "al r0 r1 LSR 7",
550 "ShiftTypes_al_r0_r1_LSR_7",
551 ARRAY_SIZE(kShiftTypes),
552 kShiftTypes},
553 {{al, r0, r1, LSR, 8},
554 "al r0 r1 LSR 8",
555 "ShiftTypes_al_r0_r1_LSR_8",
556 ARRAY_SIZE(kShiftTypes),
557 kShiftTypes},
558 {{al, r0, r1, LSR, 9},
559 "al r0 r1 LSR 9",
560 "ShiftTypes_al_r0_r1_LSR_9",
561 ARRAY_SIZE(kShiftTypes),
562 kShiftTypes},
563 {{al, r0, r1, LSR, 10},
564 "al r0 r1 LSR 10",
565 "ShiftTypes_al_r0_r1_LSR_10",
566 ARRAY_SIZE(kShiftTypes),
567 kShiftTypes},
568 {{al, r0, r1, LSR, 11},
569 "al r0 r1 LSR 11",
570 "ShiftTypes_al_r0_r1_LSR_11",
571 ARRAY_SIZE(kShiftTypes),
572 kShiftTypes},
573 {{al, r0, r1, LSR, 12},
574 "al r0 r1 LSR 12",
575 "ShiftTypes_al_r0_r1_LSR_12",
576 ARRAY_SIZE(kShiftTypes),
577 kShiftTypes},
578 {{al, r0, r1, LSR, 13},
579 "al r0 r1 LSR 13",
580 "ShiftTypes_al_r0_r1_LSR_13",
581 ARRAY_SIZE(kShiftTypes),
582 kShiftTypes},
583 {{al, r0, r1, LSR, 14},
584 "al r0 r1 LSR 14",
585 "ShiftTypes_al_r0_r1_LSR_14",
586 ARRAY_SIZE(kShiftTypes),
587 kShiftTypes},
588 {{al, r0, r1, LSR, 15},
589 "al r0 r1 LSR 15",
590 "ShiftTypes_al_r0_r1_LSR_15",
591 ARRAY_SIZE(kShiftTypes),
592 kShiftTypes},
593 {{al, r0, r1, LSR, 16},
594 "al r0 r1 LSR 16",
595 "ShiftTypes_al_r0_r1_LSR_16",
596 ARRAY_SIZE(kShiftTypes),
597 kShiftTypes},
598 {{al, r0, r1, LSR, 17},
599 "al r0 r1 LSR 17",
600 "ShiftTypes_al_r0_r1_LSR_17",
601 ARRAY_SIZE(kShiftTypes),
602 kShiftTypes},
603 {{al, r0, r1, LSR, 18},
604 "al r0 r1 LSR 18",
605 "ShiftTypes_al_r0_r1_LSR_18",
606 ARRAY_SIZE(kShiftTypes),
607 kShiftTypes},
608 {{al, r0, r1, LSR, 19},
609 "al r0 r1 LSR 19",
610 "ShiftTypes_al_r0_r1_LSR_19",
611 ARRAY_SIZE(kShiftTypes),
612 kShiftTypes},
613 {{al, r0, r1, LSR, 20},
614 "al r0 r1 LSR 20",
615 "ShiftTypes_al_r0_r1_LSR_20",
616 ARRAY_SIZE(kShiftTypes),
617 kShiftTypes},
618 {{al, r0, r1, LSR, 21},
619 "al r0 r1 LSR 21",
620 "ShiftTypes_al_r0_r1_LSR_21",
621 ARRAY_SIZE(kShiftTypes),
622 kShiftTypes},
623 {{al, r0, r1, LSR, 22},
624 "al r0 r1 LSR 22",
625 "ShiftTypes_al_r0_r1_LSR_22",
626 ARRAY_SIZE(kShiftTypes),
627 kShiftTypes},
628 {{al, r0, r1, LSR, 23},
629 "al r0 r1 LSR 23",
630 "ShiftTypes_al_r0_r1_LSR_23",
631 ARRAY_SIZE(kShiftTypes),
632 kShiftTypes},
633 {{al, r0, r1, LSR, 24},
634 "al r0 r1 LSR 24",
635 "ShiftTypes_al_r0_r1_LSR_24",
636 ARRAY_SIZE(kShiftTypes),
637 kShiftTypes},
638 {{al, r0, r1, LSR, 25},
639 "al r0 r1 LSR 25",
640 "ShiftTypes_al_r0_r1_LSR_25",
641 ARRAY_SIZE(kShiftTypes),
642 kShiftTypes},
643 {{al, r0, r1, LSR, 26},
644 "al r0 r1 LSR 26",
645 "ShiftTypes_al_r0_r1_LSR_26",
646 ARRAY_SIZE(kShiftTypes),
647 kShiftTypes},
648 {{al, r0, r1, LSR, 27},
649 "al r0 r1 LSR 27",
650 "ShiftTypes_al_r0_r1_LSR_27",
651 ARRAY_SIZE(kShiftTypes),
652 kShiftTypes},
653 {{al, r0, r1, LSR, 28},
654 "al r0 r1 LSR 28",
655 "ShiftTypes_al_r0_r1_LSR_28",
656 ARRAY_SIZE(kShiftTypes),
657 kShiftTypes},
658 {{al, r0, r1, LSR, 29},
659 "al r0 r1 LSR 29",
660 "ShiftTypes_al_r0_r1_LSR_29",
661 ARRAY_SIZE(kShiftTypes),
662 kShiftTypes},
663 {{al, r0, r1, LSR, 30},
664 "al r0 r1 LSR 30",
665 "ShiftTypes_al_r0_r1_LSR_30",
666 ARRAY_SIZE(kShiftTypes),
667 kShiftTypes},
668 {{al, r0, r1, LSR, 31},
669 "al r0 r1 LSR 31",
670 "ShiftTypes_al_r0_r1_LSR_31",
671 ARRAY_SIZE(kShiftTypes),
672 kShiftTypes},
673 {{al, r0, r1, LSR, 32},
674 "al r0 r1 LSR 32",
675 "ShiftTypes_al_r0_r1_LSR_32",
676 ARRAY_SIZE(kShiftTypes),
677 kShiftTypes},
678 {{al, r0, r1, ASR, 1},
679 "al r0 r1 ASR 1",
680 "ShiftTypes_al_r0_r1_ASR_1",
681 ARRAY_SIZE(kShiftTypes),
682 kShiftTypes},
683 {{al, r0, r1, ASR, 2},
684 "al r0 r1 ASR 2",
685 "ShiftTypes_al_r0_r1_ASR_2",
686 ARRAY_SIZE(kShiftTypes),
687 kShiftTypes},
688 {{al, r0, r1, ASR, 3},
689 "al r0 r1 ASR 3",
690 "ShiftTypes_al_r0_r1_ASR_3",
691 ARRAY_SIZE(kShiftTypes),
692 kShiftTypes},
693 {{al, r0, r1, ASR, 4},
694 "al r0 r1 ASR 4",
695 "ShiftTypes_al_r0_r1_ASR_4",
696 ARRAY_SIZE(kShiftTypes),
697 kShiftTypes},
698 {{al, r0, r1, ASR, 5},
699 "al r0 r1 ASR 5",
700 "ShiftTypes_al_r0_r1_ASR_5",
701 ARRAY_SIZE(kShiftTypes),
702 kShiftTypes},
703 {{al, r0, r1, ASR, 6},
704 "al r0 r1 ASR 6",
705 "ShiftTypes_al_r0_r1_ASR_6",
706 ARRAY_SIZE(kShiftTypes),
707 kShiftTypes},
708 {{al, r0, r1, ASR, 7},
709 "al r0 r1 ASR 7",
710 "ShiftTypes_al_r0_r1_ASR_7",
711 ARRAY_SIZE(kShiftTypes),
712 kShiftTypes},
713 {{al, r0, r1, ASR, 8},
714 "al r0 r1 ASR 8",
715 "ShiftTypes_al_r0_r1_ASR_8",
716 ARRAY_SIZE(kShiftTypes),
717 kShiftTypes},
718 {{al, r0, r1, ASR, 9},
719 "al r0 r1 ASR 9",
720 "ShiftTypes_al_r0_r1_ASR_9",
721 ARRAY_SIZE(kShiftTypes),
722 kShiftTypes},
723 {{al, r0, r1, ASR, 10},
724 "al r0 r1 ASR 10",
725 "ShiftTypes_al_r0_r1_ASR_10",
726 ARRAY_SIZE(kShiftTypes),
727 kShiftTypes},
728 {{al, r0, r1, ASR, 11},
729 "al r0 r1 ASR 11",
730 "ShiftTypes_al_r0_r1_ASR_11",
731 ARRAY_SIZE(kShiftTypes),
732 kShiftTypes},
733 {{al, r0, r1, ASR, 12},
734 "al r0 r1 ASR 12",
735 "ShiftTypes_al_r0_r1_ASR_12",
736 ARRAY_SIZE(kShiftTypes),
737 kShiftTypes},
738 {{al, r0, r1, ASR, 13},
739 "al r0 r1 ASR 13",
740 "ShiftTypes_al_r0_r1_ASR_13",
741 ARRAY_SIZE(kShiftTypes),
742 kShiftTypes},
743 {{al, r0, r1, ASR, 14},
744 "al r0 r1 ASR 14",
745 "ShiftTypes_al_r0_r1_ASR_14",
746 ARRAY_SIZE(kShiftTypes),
747 kShiftTypes},
748 {{al, r0, r1, ASR, 15},
749 "al r0 r1 ASR 15",
750 "ShiftTypes_al_r0_r1_ASR_15",
751 ARRAY_SIZE(kShiftTypes),
752 kShiftTypes},
753 {{al, r0, r1, ASR, 16},
754 "al r0 r1 ASR 16",
755 "ShiftTypes_al_r0_r1_ASR_16",
756 ARRAY_SIZE(kShiftTypes),
757 kShiftTypes},
758 {{al, r0, r1, ASR, 17},
759 "al r0 r1 ASR 17",
760 "ShiftTypes_al_r0_r1_ASR_17",
761 ARRAY_SIZE(kShiftTypes),
762 kShiftTypes},
763 {{al, r0, r1, ASR, 18},
764 "al r0 r1 ASR 18",
765 "ShiftTypes_al_r0_r1_ASR_18",
766 ARRAY_SIZE(kShiftTypes),
767 kShiftTypes},
768 {{al, r0, r1, ASR, 19},
769 "al r0 r1 ASR 19",
770 "ShiftTypes_al_r0_r1_ASR_19",
771 ARRAY_SIZE(kShiftTypes),
772 kShiftTypes},
773 {{al, r0, r1, ASR, 20},
774 "al r0 r1 ASR 20",
775 "ShiftTypes_al_r0_r1_ASR_20",
776 ARRAY_SIZE(kShiftTypes),
777 kShiftTypes},
778 {{al, r0, r1, ASR, 21},
779 "al r0 r1 ASR 21",
780 "ShiftTypes_al_r0_r1_ASR_21",
781 ARRAY_SIZE(kShiftTypes),
782 kShiftTypes},
783 {{al, r0, r1, ASR, 22},
784 "al r0 r1 ASR 22",
785 "ShiftTypes_al_r0_r1_ASR_22",
786 ARRAY_SIZE(kShiftTypes),
787 kShiftTypes},
788 {{al, r0, r1, ASR, 23},
789 "al r0 r1 ASR 23",
790 "ShiftTypes_al_r0_r1_ASR_23",
791 ARRAY_SIZE(kShiftTypes),
792 kShiftTypes},
793 {{al, r0, r1, ASR, 24},
794 "al r0 r1 ASR 24",
795 "ShiftTypes_al_r0_r1_ASR_24",
796 ARRAY_SIZE(kShiftTypes),
797 kShiftTypes},
798 {{al, r0, r1, ASR, 25},
799 "al r0 r1 ASR 25",
800 "ShiftTypes_al_r0_r1_ASR_25",
801 ARRAY_SIZE(kShiftTypes),
802 kShiftTypes},
803 {{al, r0, r1, ASR, 26},
804 "al r0 r1 ASR 26",
805 "ShiftTypes_al_r0_r1_ASR_26",
806 ARRAY_SIZE(kShiftTypes),
807 kShiftTypes},
808 {{al, r0, r1, ASR, 27},
809 "al r0 r1 ASR 27",
810 "ShiftTypes_al_r0_r1_ASR_27",
811 ARRAY_SIZE(kShiftTypes),
812 kShiftTypes},
813 {{al, r0, r1, ASR, 28},
814 "al r0 r1 ASR 28",
815 "ShiftTypes_al_r0_r1_ASR_28",
816 ARRAY_SIZE(kShiftTypes),
817 kShiftTypes},
818 {{al, r0, r1, ASR, 29},
819 "al r0 r1 ASR 29",
820 "ShiftTypes_al_r0_r1_ASR_29",
821 ARRAY_SIZE(kShiftTypes),
822 kShiftTypes},
823 {{al, r0, r1, ASR, 30},
824 "al r0 r1 ASR 30",
825 "ShiftTypes_al_r0_r1_ASR_30",
826 ARRAY_SIZE(kShiftTypes),
827 kShiftTypes},
828 {{al, r0, r1, ASR, 31},
829 "al r0 r1 ASR 31",
830 "ShiftTypes_al_r0_r1_ASR_31",
831 ARRAY_SIZE(kShiftTypes),
832 kShiftTypes},
833 {{al, r0, r1, ASR, 32},
834 "al r0 r1 ASR 32",
835 "ShiftTypes_al_r0_r1_ASR_32",
836 ARRAY_SIZE(kShiftTypes),
837 kShiftTypes}};
838
839 // We record all inputs to the instructions as outputs. This way, we also check
840 // that what shouldn't change didn't change.
841 struct TestResult {
842 size_t output_size;
843 const Inputs* outputs;
844 };
845
846 // These headers each contain an array of `TestResult` with the reference output
847 // values. The reference arrays are names `kReference{mnemonic}`.
848 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-cmn-t32.h"
849 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-cmp-t32.h"
850 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-mov-t32.h"
851 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-movs-t32.h"
852 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-mvn-t32.h"
853 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-mvns-t32.h"
854 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-teq-t32.h"
855 #include "aarch32/traces/simulator-cond-rd-operand-rn-shift-amount-1to32-tst-t32.h"
856
857
858 // The maximum number of errors to report in detail for each test.
859 const unsigned kErrorReportLimit = 8;
860
861 typedef void (MacroAssembler::*Fn)(Condition cond,
862 Register rd,
863 const Operand& op);
864
TestHelper(Fn instruction,const char * mnemonic,const TestResult reference[])865 void TestHelper(Fn instruction,
866 const char* mnemonic,
867 const TestResult reference[]) {
868 SETUP();
869 masm.UseT32();
870 START();
871
872 // Data to compare to `reference`.
873 TestResult* results[ARRAY_SIZE(kTests)];
874
875 // Test cases for memory bound instructions may allocate a buffer and save its
876 // address in this array.
877 byte* scratch_memory_buffers[ARRAY_SIZE(kTests)];
878
879 // Generate a loop for each element in `kTests`. Each loop tests one specific
880 // instruction.
881 for (unsigned i = 0; i < ARRAY_SIZE(kTests); i++) {
882 // Allocate results on the heap for this test.
883 results[i] = new TestResult;
884 results[i]->outputs = new Inputs[kTests[i].input_size];
885 results[i]->output_size = kTests[i].input_size;
886
887 size_t input_stride = sizeof(kTests[i].inputs[0]) * kTests[i].input_size;
888 VIXL_ASSERT(IsUint32(input_stride));
889
890 scratch_memory_buffers[i] = NULL;
891
892 Label loop;
893 UseScratchRegisterScope scratch_registers(&masm);
894 // Include all registers from r0 ro r12.
895 scratch_registers.Include(RegisterList(0x1fff));
896
897 // Values to pass to the macro-assembler.
898 Condition cond = kTests[i].operands.cond;
899 Register rd = kTests[i].operands.rd;
900 Register rn = kTests[i].operands.rn;
901 ShiftType shift = kTests[i].operands.shift;
902 uint32_t amount = kTests[i].operands.amount;
903 Operand op(rn, shift, amount);
904 scratch_registers.Exclude(rd);
905 scratch_registers.Exclude(rn);
906
907 // Allocate reserved registers for our own use.
908 Register input_ptr = scratch_registers.Acquire();
909 Register input_end = scratch_registers.Acquire();
910 Register result_ptr = scratch_registers.Acquire();
911
912 // Initialize `input_ptr` to the first element and `input_end` the address
913 // after the array.
914 __ Mov(input_ptr, Operand::From(kTests[i].inputs));
915 __ Add(input_end, input_ptr, static_cast<uint32_t>(input_stride));
916 __ Mov(result_ptr, Operand::From(results[i]->outputs));
917 __ Bind(&loop);
918
919 {
920 UseScratchRegisterScope temp_registers(&masm);
921 Register nzcv_bits = temp_registers.Acquire();
922 Register saved_q_bit = temp_registers.Acquire();
923 // Save the `Q` bit flag.
924 __ Mrs(saved_q_bit, APSR);
925 __ And(saved_q_bit, saved_q_bit, QFlag);
926 // Set the `NZCV` and `Q` flags together.
927 __ Ldr(nzcv_bits, MemOperand(input_ptr, offsetof(Inputs, apsr)));
928 __ Orr(nzcv_bits, nzcv_bits, saved_q_bit);
929 __ Msr(APSR_nzcvq, nzcv_bits);
930 }
931 __ Ldr(rd, MemOperand(input_ptr, offsetof(Inputs, rd)));
932 __ Ldr(rn, MemOperand(input_ptr, offsetof(Inputs, rn)));
933
934 (masm.*instruction)(cond, rd, op);
935
936 {
937 UseScratchRegisterScope temp_registers(&masm);
938 Register nzcv_bits = temp_registers.Acquire();
939 __ Mrs(nzcv_bits, APSR);
940 // Only record the NZCV bits.
941 __ And(nzcv_bits, nzcv_bits, NZCVFlag);
942 __ Str(nzcv_bits, MemOperand(result_ptr, offsetof(Inputs, apsr)));
943 }
944 __ Str(rd, MemOperand(result_ptr, offsetof(Inputs, rd)));
945 __ Str(rn, MemOperand(result_ptr, offsetof(Inputs, rn)));
946
947 // Advance the result pointer.
948 __ Add(result_ptr, result_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
949 // Loop back until `input_ptr` is lower than `input_base`.
950 __ Add(input_ptr, input_ptr, Operand::From(sizeof(kTests[i].inputs[0])));
951 __ Cmp(input_ptr, input_end);
952 __ B(ne, &loop);
953 }
954
955 END();
956
957 RUN();
958
959 if (Test::generate_test_trace()) {
960 // Print the results.
961 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
962 printf("const Inputs kOutputs_%s_%s[] = {\n",
963 mnemonic,
964 kTests[i].identifier);
965 for (size_t j = 0; j < results[i]->output_size; j++) {
966 printf(" { ");
967 printf("0x%08" PRIx32, results[i]->outputs[j].apsr);
968 printf(", ");
969 printf("0x%08" PRIx32, results[i]->outputs[j].rd);
970 printf(", ");
971 printf("0x%08" PRIx32, results[i]->outputs[j].rn);
972 printf(" },\n");
973 }
974 printf("};\n");
975 }
976 printf("const TestResult kReference%s[] = {\n", mnemonic);
977 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
978 printf(" {\n");
979 printf(" ARRAY_SIZE(kOutputs_%s_%s),\n",
980 mnemonic,
981 kTests[i].identifier);
982 printf(" kOutputs_%s_%s,\n", mnemonic, kTests[i].identifier);
983 printf(" },\n");
984 }
985 printf("};\n");
986 } else if (kCheckSimulatorTestResults) {
987 // Check the results.
988 unsigned total_error_count = 0;
989 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
990 bool instruction_has_errors = false;
991 for (size_t j = 0; j < kTests[i].input_size; j++) {
992 uint32_t apsr = results[i]->outputs[j].apsr;
993 uint32_t rd = results[i]->outputs[j].rd;
994 uint32_t rn = results[i]->outputs[j].rn;
995 uint32_t apsr_input = kTests[i].inputs[j].apsr;
996 uint32_t rd_input = kTests[i].inputs[j].rd;
997 uint32_t rn_input = kTests[i].inputs[j].rn;
998 uint32_t apsr_ref = reference[i].outputs[j].apsr;
999 uint32_t rd_ref = reference[i].outputs[j].rd;
1000 uint32_t rn_ref = reference[i].outputs[j].rn;
1001
1002 if (((apsr != apsr_ref) || (rd != rd_ref) || (rn != rn_ref)) &&
1003 (++total_error_count <= kErrorReportLimit)) {
1004 // Print the instruction once even if it triggered multiple failures.
1005 if (!instruction_has_errors) {
1006 printf("Error(s) when testing \"%s %s\":\n",
1007 mnemonic,
1008 kTests[i].operands_description);
1009 instruction_has_errors = true;
1010 }
1011 // Print subsequent errors.
1012 printf(" Input: ");
1013 printf("0x%08" PRIx32, apsr_input);
1014 printf(", ");
1015 printf("0x%08" PRIx32, rd_input);
1016 printf(", ");
1017 printf("0x%08" PRIx32, rn_input);
1018 printf("\n");
1019 printf(" Expected: ");
1020 printf("0x%08" PRIx32, apsr_ref);
1021 printf(", ");
1022 printf("0x%08" PRIx32, rd_ref);
1023 printf(", ");
1024 printf("0x%08" PRIx32, rn_ref);
1025 printf("\n");
1026 printf(" Found: ");
1027 printf("0x%08" PRIx32, apsr);
1028 printf(", ");
1029 printf("0x%08" PRIx32, rd);
1030 printf(", ");
1031 printf("0x%08" PRIx32, rn);
1032 printf("\n\n");
1033 }
1034 }
1035 }
1036
1037 if (total_error_count > kErrorReportLimit) {
1038 printf("%u other errors follow.\n",
1039 total_error_count - kErrorReportLimit);
1040 }
1041 VIXL_CHECK(total_error_count == 0);
1042 } else {
1043 VIXL_WARNING("Assembled the code, but did not run anything.\n");
1044 }
1045
1046 for (size_t i = 0; i < ARRAY_SIZE(kTests); i++) {
1047 delete[] results[i]->outputs;
1048 delete results[i];
1049 delete[] scratch_memory_buffers[i];
1050 }
1051 }
1052
1053 // Instantiate tests for each instruction in the list.
1054 // TODO: Remove this limitation by having a sandboxing mechanism.
1055 #if defined(VIXL_HOST_POINTER_32)
1056 #define TEST(mnemonic) \
1057 void Test_##mnemonic() { \
1058 TestHelper(&MacroAssembler::mnemonic, #mnemonic, kReference##mnemonic); \
1059 } \
1060 Test test_##mnemonic( \
1061 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" #mnemonic \
1062 "_T32", \
1063 &Test_##mnemonic);
1064 #else
1065 #define TEST(mnemonic) \
1066 void Test_##mnemonic() { \
1067 VIXL_WARNING("This test can only run on a 32-bit host.\n"); \
1068 USE(TestHelper); \
1069 } \
1070 Test test_##mnemonic( \
1071 "AARCH32_SIMULATOR_COND_RD_OPERAND_RN_SHIFT_AMOUNT_1TO32_" #mnemonic \
1072 "_T32", \
1073 &Test_##mnemonic);
1074 #endif
1075
1076 FOREACH_INSTRUCTION(TEST)
1077 #undef TEST
1078
1079 } // namespace
1080 #endif
1081
1082 } // namespace aarch32
1083 } // namespace vixl
1084