| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-shrink-v1i64.ll | 4 ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-shrink-v1i64.ll | 4 ; Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1183 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
1184 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && in ShrinkDemandedOp()
1185 TLI.isZExtFree(SmallVT, Op.getValueType())) { in ShrinkDemandedOp()
1187 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
1188 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
1190 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
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| D | DAGCombiner.cpp | 3581 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
3582 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) in visitSRL()
3585 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
3587 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, in visitSRL()
3589 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); in visitSRL()
7044 EVT SmallVT = V->getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
7045 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) in visitEXTRACT_SUBVECTOR()
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| D | LegalizeIntegerTypes.cpp | 642 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
662 DAG.getIntPtrConstant(SmallVT.getSizeInBits())); in PromoteIntRes_XMULO()
668 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 403 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
404 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && in ShrinkDemandedOp()
405 TLI.isZExtFree(SmallVT, Op.getValueType())) { in ShrinkDemandedOp()
407 SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
408 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
410 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, in ShrinkDemandedOp()
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| D | LegalizeIntegerTypes.cpp | 766 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
789 DAG.getIntPtrConstant(SmallVT.getSizeInBits(), in PromoteIntRes_XMULO()
797 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
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| D | DAGCombiner.cpp | 4843 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
4844 unsigned BitSize = SmallVT.getScalarSizeInBits(); in visitSRL()
4848 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
4851 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
4854 getShiftAmountTy(SmallVT))); in visitSRL()
13222 EVT SmallVT = V->getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
13223 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) in visitEXTRACT_SUBVECTOR()
13238 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() == in visitEXTRACT_SUBVECTOR()
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| D | SelectionDAGBuilder.cpp | 7158 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); in lowerRangeToAssertZExt() local
7163 Op, DAG.getValueType(SmallVT)); in lowerRangeToAssertZExt()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 416 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits); in ShrinkDemandedOp() local
417 if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && in ShrinkDemandedOp()
418 TLI.isZExtFree(SmallVT, Op.getValueType())) { in ShrinkDemandedOp()
421 Op.getOpcode(), dl, SmallVT, in ShrinkDemandedOp()
422 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), in ShrinkDemandedOp()
423 DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1))); in ShrinkDemandedOp()
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| D | LegalizeIntegerTypes.cpp | 802 EVT SmallVT = LHS.getValueType(); in PromoteIntRes_XMULO() local
825 DAG.getIntPtrConstant(SmallVT.getSizeInBits(), in PromoteIntRes_XMULO()
833 Mul, DAG.getValueType(SmallVT)); in PromoteIntRes_XMULO()
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| D | DAGCombiner.cpp | 6791 EVT SmallVT = N0.getOperand(0).getValueType(); in visitSRL() local
6792 unsigned BitSize = SmallVT.getScalarSizeInBits(); in visitSRL()
6796 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { in visitSRL()
6799 SDValue SmallShift = DAG.getNode(ISD::SRL, DL0, SmallVT, in visitSRL()
6802 getShiftAmountTy(SmallVT))); in visitSRL()
16495 EVT SmallVT = V->getOperand(1).getValueType(); in visitEXTRACT_SUBVECTOR() local
16496 if (!NVT.bitsEq(SmallVT)) in visitEXTRACT_SUBVECTOR()
16509 if (InsIdx->getZExtValue() * SmallVT.getScalarSizeInBits() == in visitEXTRACT_SUBVECTOR()
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| D | SelectionDAGBuilder.cpp | 7927 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), Bits); in lowerRangeToAssertZExt() local
7932 DAG.getValueType(SmallVT)); in lowerRangeToAssertZExt()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 2666 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal); in PerformDAGCombine() local
2675 DAG.getValueType(SmallVT)); in PerformDAGCombine()
2678 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 3832 EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), WidthVal); in PerformDAGCombine() local
3841 DAG.getValueType(SmallVT)); in PerformDAGCombine()
3844 return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT); in PerformDAGCombine()
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