1; RUN: llc -march=arm64 < %s
2
3; The DAGCombiner tries to do following shrink:
4;     Convert x+y to (VT)((SmallVT)x+(SmallVT)y)
5; But currently it can't handle vector type and will trigger an assertion failure
6; when it tries to generate an add mixed using vector type and scaler type.
7; This test checks that such assertion failur should not happen.
8define <1 x i64> @dotest(<1 x i64> %in0) {
9entry:
10  %0 = add <1 x i64> %in0, %in0
11  %vshl_n = shl <1 x i64> %0, <i64 32>
12  %vsra_n = ashr <1 x i64> %vshl_n, <i64 32>
13  ret <1 x i64> %vsra_n
14}
15