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Searched refs:Src1 (Results 1 – 25 of 83) sorted by relevance

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/external/swiftshader/third_party/subzero/src/
DIceTargetLoweringMIPS32.h166 void _add(Variable *Dest, Variable *Src0, Variable *Src1) { in _add() argument
167 Context.insert<InstMIPS32Add>(Dest, Src0, Src1); in _add()
170 void _addu(Variable *Dest, Variable *Src0, Variable *Src1) { in _addu() argument
171 Context.insert<InstMIPS32Addu>(Dest, Src0, Src1); in _addu()
174 void _and(Variable *Dest, Variable *Src0, Variable *Src1) { in _and() argument
175 Context.insert<InstMIPS32And>(Dest, Src0, Src1); in _and()
189 Operand *Src1, CondMIPS32::Cond Condition) { in _br() argument
190 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, in _br()
200 Operand *Src1, const InstMIPS32Label *Label, in _br() argument
202 Context.insert<InstMIPS32Br>(TargetTrue, TargetFalse, Src0, Src1, Label, in _br()
[all …]
DIceTargetLoweringARM32.h213 Operand *Src0, Operand *Src1);
253 Operand *Src0, Operand *Src1);
255 Operand *Src1);
257 Operand *Src1);
259 Operand *Src1);
326 void lowerIDivRem(Variable *Dest, Variable *T, Variable *Src0R, Operand *Src1,
334 void _add(Variable *Dest, Variable *Src0, Operand *Src1,
336 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred);
338 void _adds(Variable *Dest, Variable *Src0, Operand *Src1,
341 Context.insert<InstARM32Add>(Dest, Src0, Src1, Pred, SetFlags);
[all …]
DIceTargetLoweringX86Base.h419 Operand *legalizeSrc0ForCmp(Operand *Src0, Operand *Src1);
520 void _adc_rmw(X86OperandMem *DestSrc0, Operand *Src1) { in _adc_rmw() argument
521 AutoMemorySandboxer<> _(this, &DestSrc0, &Src1); in _adc_rmw()
522 Context.insert<typename Traits::Insts::AdcRMW>(DestSrc0, Src1); in _adc_rmw()
528 void _add_rmw(X86OperandMem *DestSrc0, Operand *Src1) { in _add_rmw() argument
529 AutoMemorySandboxer<> _(this, &DestSrc0, &Src1); in _add_rmw()
530 Context.insert<typename Traits::Insts::AddRMW>(DestSrc0, Src1); in _add_rmw()
555 void _and_rmw(X86OperandMem *DestSrc0, Operand *Src1) { in _and_rmw() argument
556 AutoMemorySandboxer<> _(this, &DestSrc0, &Src1); in _and_rmw()
557 Context.insert<typename Traits::Insts::AndRMW>(DestSrc0, Src1); in _and_rmw()
[all …]
DIceTargetLoweringX86BaseImpl.h804 Operand *&Src0, Operand *&Src1) {
805 if (Src0 == LoadDest && Src1 != LoadDest) {
809 if (Src0 != LoadDest && Src1 == LoadDest) {
810 Src1 = LoadSrc;
856 Operand *Src1 = Arith->getSrc(1);
857 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
859 Arith->getDest(), Src0, Src1);
863 Operand *Src1 = Icmp->getSrc(1);
864 if (canFoldLoadIntoBinaryInst(LoadSrc, LoadDest, Src0, Src1)) {
866 Icmp->getDest(), Src0, Src1);
[all …]
DIceInstARM32.h746 Variable *Src0, Operand *Src1,
750 InstARM32ThreeAddrGPR(Func, Dest, Src0, Src1, Predicate, SetFlags);
772 Operand *Src1, CondARM32::Cond Predicate, bool SetFlags) in InstARM32ThreeAddrGPR() argument
776 addSource(Src1); in InstARM32ThreeAddrGPR()
797 Variable *Src1) { in create() argument
799 InstARM32ThreeAddrFP(Func, Dest, Src0, Src1); in create()
822 InstARM32ThreeAddrFP(Cfg *Func, Variable *Dest, Variable *Src0, Operand *Src1) in InstARM32ThreeAddrFP() argument
825 addSource(Src1); in InstARM32ThreeAddrFP()
847 Variable *Src0, Variable *Src1) { in create() argument
849 InstARM32ThreeAddrSignAwareFP(Func, Dest, Src0, Src1); in create()
[all …]
DIceTargetLoweringARM32.cpp542 Operand *Src1 = Instr->getSrc(1); in genTargetHelperCallFor() local
554 if (auto *C = llvm::dyn_cast<ConstantInteger32>(Src1)) { in genTargetHelperCallFor()
562 Src1 = Ctx->getConstantInt32(NewC); in genTargetHelperCallFor()
565 Context.insert<InstCast>(CastKind, Src1_32, Src1); in genTargetHelperCallFor()
566 Src1 = Src1_32; in genTargetHelperCallFor()
576 assert(Src1->getType() == IceType_i32); in genTargetHelperCallFor()
577 Call->addArg(Src1); in genTargetHelperCallFor()
2323 Operand *Src1, ExtInstr ExtFunc, in lowerIDivRem() argument
2325 div0Check(Dest->getType(), Src1, nullptr); in lowerIDivRem()
2326 Variable *Src1R = legalizeToReg(Src1); in lowerIDivRem()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
66 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
77 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
88 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
99 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
/external/llvm/lib/ExecutionEngine/Interpreter/
DExecution.cpp52 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
55 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
66 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
77 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
88 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
99 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
103 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
106 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
116 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
121 assert(Src1.AggregateVal.size() == Src2.AggregateVal.size()); \
[all …]
/external/swiftshader/third_party/LLVM/lib/ExecutionEngine/Interpreter/
DExecution.cpp50 Dest.TY##Val = Src1.TY##Val OP Src2.TY##Val; \
53 static void executeFAddInst(GenericValue &Dest, GenericValue Src1, in executeFAddInst() argument
64 static void executeFSubInst(GenericValue &Dest, GenericValue Src1, in executeFSubInst() argument
75 static void executeFMulInst(GenericValue &Dest, GenericValue Src1, in executeFMulInst() argument
86 static void executeFDivInst(GenericValue &Dest, GenericValue Src1, in executeFDivInst() argument
97 static void executeFRemInst(GenericValue &Dest, GenericValue Src1, in executeFRemInst() argument
101 Dest.FloatVal = fmod(Src1.FloatVal, Src2.FloatVal); in executeFRemInst()
104 Dest.DoubleVal = fmod(Src1.DoubleVal, Src2.DoubleVal); in executeFRemInst()
114 Dest.IntVal = APInt(1,Src1.IntVal.OP(Src2.IntVal)); \
123 Dest.IntVal = APInt(1,(void*)(intptr_t)Src1.PointerVal OP \
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/external/swiftshader/third_party/subzero/unittest/AssemblerX8664/
DControlFlow.cpp17 #define TestJ(C, Near, Dest, Src0, Value0, Src1, Value1) \ in TEST_F() argument
20 "(" #C ", " #Near ", " #Dest ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
25 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \ in TEST_F()
27 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
34 ASSERT_EQ(Value1, test.Src1()) << TestString; \ in TEST_F()
39 #define TestImpl(Dst, Src0, Src1) \ in TEST_F() argument
41 TestJ(o, Near, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \ in TEST_F()
42 TestJ(o, Far, Dst, Src0, 0x80000000ul, Src1, 0x1ul); \ in TEST_F()
43 TestJ(no, Near, Dst, Src0, 0x1ul, Src1, 0x1ul); \ in TEST_F()
44 TestJ(no, Far, Dst, Src0, 0x1ul, Src1, 0x1ul); \ in TEST_F()
[all …]
DDataMov.cpp422 #define TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
425 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
428 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \ in TEST_F()
430 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
432 Encoded_GPR_##Src1()); \ in TEST_F()
462 #define TestValue(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
464 TestRegReg(C, Dest, IsTrue, Src0, Value0, Src1, Value1); \ in TEST_F()
468 #define TestImpl(Dest, Src0, Src1) \ in TEST_F() argument
470 TestValue(o, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
471 TestValue(o, Dest, 0u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
[all …]
DGPRArith.cpp33 #define TestSetCC(C, Dest, IsTrue, Src0, Value0, Src1, Value1) \ in TEST_F() argument
36 "(" #C ", " #Dest ", " #IsTrue ", " #Src0 ", " #Value0 ", " #Src1 \ in TEST_F()
41 __ mov(IceType_i32, Encoded_GPR_##Src1(), Immediate(Value1)); \ in TEST_F()
42 __ cmp(IceType_i32, Encoded_GPR_##Src0(), Encoded_GPR_##Src1()); \ in TEST_F()
57 #define TestImpl(Dest, Src0, Src1) \ in TEST_F() argument
59 TestSetCC(o, Dest, 1u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
60 TestSetCC(o, Dest, 0u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
61 TestSetCC(no, Dest, 1u, Src0, 0x1u, Src1, 0x10000000u); \ in TEST_F()
62 TestSetCC(no, Dest, 0u, Src0, 0x80000000u, Src1, 0x1u); \ in TEST_F()
63 TestSetCC(b, Dest, 1u, Src0, 0x1, Src1, 0x80000000u); \ in TEST_F()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp85 const MachineOperand *Src1 in canShrink() local
87 if (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg())) in canShrink()
105 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink() local
106 if (Src1 && (!Src1->isReg() || !TRI.isVGPR(MRI, Src1->getReg()) || in canShrink()
249 const MachineOperand &Src1 = MI.getOperand(1); in shrinkScalarCompare() local
250 if (!Src1.isImm()) in shrinkScalarCompare()
261 if (isKImmOrKUImmOperand(TII, Src1, HasUImm)) { in shrinkScalarCompare()
275 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(TII, Src1)) || in shrinkScalarCompare()
276 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(TII, Src1))) { in shrinkScalarCompare()
358 MachineOperand *Src1 = &MI.getOperand(2); in runOnMachineFunction() local
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DR600ExpandSpecialInstrs.cpp162 unsigned Src1 = BMI->getOperand( in runOnMachineFunction() local
166 (void) Src1; in runOnMachineFunction()
168 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
169 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
213 unsigned Src1 = 0; in runOnMachineFunction() local
219 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction()
225 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
230 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
265 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
DSIFoldOperands.cpp548 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx)); in tryConstantFoldOp() local
550 if (!Src0->isImm() && !Src1->isImm()) in tryConstantFoldOp()
556 if (Src0->isImm() && Src1->isImm()) { in tryConstantFoldOp()
558 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm())) in tryConstantFoldOp()
575 if (Src0->isImm() && !Src1->isImm()) { in tryConstantFoldOp()
576 std::swap(Src0, Src1); in tryConstantFoldOp()
580 int32_t Src1Val = static_cast<int32_t>(Src1->getImm()); in tryConstantFoldOp()
639 const MachineOperand *Src1 = TII->getNamedOperand(*MI, AMDGPU::OpName::src1); in tryFoldInst() local
640 if (Src1->isIdenticalTo(*Src0)) { in tryFoldInst()
781 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp() local
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DSIOptimizeExecMasking.cpp103 const MachineOperand &Src1 = MI.getOperand(1); in isLogicalOpOnExec() local
104 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC) in isLogicalOpOnExec()
329 MachineOperand &Src1 = SaveExecInst->getOperand(2); in runOnMachineFunction() local
334 OtherOp = &Src1; in runOnMachineFunction()
335 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) { in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/
DConstantFoldingMIRBuilder.h83 unsigned Src0, unsigned Src1) { in buildBinaryOp() argument
84 validateBinaryOp(Dst, Src0, Src1); in buildBinaryOp()
85 auto MaybeCst = ConstantFoldBinOp(Opcode, Src0, Src1, getMF().getRegInfo()); in buildBinaryOp()
88 return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1); in buildBinaryOp()
102 unsigned Src1) { in buildInstr() argument
119 return buildBinaryOp(Opc, Dst, Src0, Src1); in buildInstr()
122 return buildInstr(Opc).addDef(Dst).addUse(Src0).addUse(Src1); in buildInstr()
DMachineIRBuilder.h979 MachineInstrBuilder buildAdd(unsigned Dst, unsigned Src0, unsigned Src1) { in buildAdd() argument
980 return base().buildBinaryOp(TargetOpcode::G_ADD, Dst, Src0, Src1); in buildAdd()
999 MachineInstrBuilder buildSub(unsigned Dst, unsigned Src0, unsigned Src1) { in buildSub() argument
1000 return base().buildBinaryOp(TargetOpcode::G_SUB, Dst, Src0, Src1); in buildSub()
1018 MachineInstrBuilder buildMul(unsigned Dst, unsigned Src0, unsigned Src1) { in buildMul() argument
1019 return base().buildBinaryOp(TargetOpcode::G_MUL, Dst, Src0, Src1); in buildMul()
1038 MachineInstrBuilder buildAnd(unsigned Dst, unsigned Src0, unsigned Src1) { in buildAnd() argument
1039 return base().buildBinaryOp(TargetOpcode::G_AND, Dst, Src0, Src1); in buildAnd()
1057 MachineInstrBuilder buildOr(unsigned Dst, unsigned Src0, unsigned Src1) { in buildOr() argument
1058 return base().buildBinaryOp(TargetOpcode::G_OR, Dst, Src0, Src1); in buildOr()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ExpandSpecialInstrs.cpp225 unsigned Src1 = BMI->getOperand( in runOnMachineFunction() local
229 (void) Src1; in runOnMachineFunction()
231 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
232 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1)); in runOnMachineFunction()
276 unsigned Src1 = 0; in runOnMachineFunction() local
282 Src1 = MI.getOperand(Src1Idx).getReg(); in runOnMachineFunction()
288 Src1 = TRI.getSubReg(Src1, SubRegIndex); in runOnMachineFunction()
293 Src1 = TRI.getSubReg(Src0, SubRegIndex1); in runOnMachineFunction()
328 TII->buildDefaultInstruction(MBB, I, Opcode, DstReg, Src0, Src1); in runOnMachineFunction()
DSIShrinkInstructions.cpp106 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in canShrink() local
110 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0))) in canShrink()
277 const MachineOperand &Src1 = MI.getOperand(2); in runOnMachineFunction() local
289 if (Src1.isImm() && isKImmOperand(TII, Src1)) { in runOnMachineFunction()
381 const MachineOperand *Src1 = in runOnMachineFunction() local
383 if (Src1) in runOnMachineFunction()
384 Inst32.addOperand(*Src1); in runOnMachineFunction()
/external/swiftshader/third_party/llvm-7.0/llvm/unittests/CodeGen/GlobalISel/
DPatternMatchTest.cpp164 unsigned Src0, Src1, Src2; in TEST() local
166 m_GAdd(m_Reg(Src0), m_Reg(Src1))); in TEST()
169 ASSERT_EQ(Src1, Copies[1]); in TEST()
176 m_GMul(m_Reg(Src0), m_Reg(Src1))); in TEST()
179 ASSERT_EQ(Src1, Copies[2]); in TEST()
183 m_GMul(m_GAdd(m_Reg(Src0), m_Reg(Src1)), m_Reg(Src2))); in TEST()
186 ASSERT_EQ(Src1, Copies[1]); in TEST()
227 m_GAnd(m_Reg(Src0), m_Reg(Src1))); in TEST()
230 ASSERT_EQ(Src1, Copies[1]); in TEST()
236 m_GOr(m_Reg(Src0), m_Reg(Src1))); in TEST()
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp96 unsigned getMuxOpcode(const MachineOperand &Src1,
175 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, in getMuxOpcode() argument
177 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
266 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
267 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0; in genMuxInBlock()
284 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
285 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonGenMux.cpp135 unsigned getMuxOpcode(const MachineOperand &Src1,
209 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1, in getMuxOpcode() argument
211 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg(); in getMuxOpcode()
306 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2); in genMuxInBlock() local
307 unsigned SR1 = Src1->isReg() ? Src1->getReg() : 0; in genMuxInBlock()
324 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2; in genMuxInBlock()
325 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2; in genMuxInBlock()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp147 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
149 EVT PtrVT = Src1.getValueType(); in emitCLC()
159 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
162 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
181 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForMemcmp() argument
187 SDValue CCReg = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
231 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForStrcmp() argument
234 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::i32, MVT::Other); in EmitTargetCodeForStrcmp()
235 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()
/external/llvm/lib/Target/SystemZ/
DSystemZSelectionDAGInfo.cpp150 SDValue Src1, SDValue Src2, uint64_t Size) { in emitCLC() argument
152 EVT PtrVT = Src1.getValueType(); in emitCLC()
162 return DAG.getNode(SystemZISD::CLC_LOOP, DL, VTs, Chain, Src1, Src2, in emitCLC()
165 return DAG.getNode(SystemZISD::CLC, DL, VTs, Chain, Src1, Src2, in emitCLC()
184 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForMemcmp() argument
190 Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes); in EmitTargetCodeForMemcmp()
235 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1, in EmitTargetCodeForStrcmp() argument
238 SDVTList VTs = DAG.getVTList(Src1.getValueType(), MVT::Other, MVT::Glue); in EmitTargetCodeForStrcmp()
239 SDValue Unused = DAG.getNode(SystemZISD::STRCMP, DL, VTs, Chain, Src1, Src2, in EmitTargetCodeForStrcmp()

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