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Searched refs:SubRegClasses (Results 1 – 11 of 11) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td300 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi)];
306 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
315 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
340 let SubRegClasses = [(GR8_ABCD_L sub_8bit), (GR8_ABCD_H sub_8bit_hi)];
343 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
348 let SubRegClasses = [(GR8_ABCD_L sub_8bit),
354 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi), (GR16 sub_16bit)];
358 let SubRegClasses = [(GR8 sub_8bit, sub_8bit_hi),
377 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi)];
382 let SubRegClasses = [(GR8_NOREX sub_8bit, sub_8bit_hi),
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZRegisterInfo.td175 let SubRegClasses = [(GR32 subreg_32bit)];
179 let SubRegClasses = [(ADDR32 subreg_32bit)];
186 let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32)];
192 let SubRegClasses = [(GR32 subreg_32bit, subreg_odd32),
199 let SubRegClasses = [(FP32 subreg_32bit)];
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMRegisterInfo.td286 let SubRegClasses = [(SPR ssub_0, ssub_1)];
293 let SubRegClasses = [(SPR_8 ssub_0, ssub_1)];
299 let SubRegClasses = [(DPR dsub_0, dsub_1)];
308 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
315 let SubRegClasses = [(SPR_8 ssub_0, ssub_1, ssub_2, ssub_3),
322 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3),
331 let SubRegClasses = [(SPR ssub_0, ssub_1, ssub_2, ssub_3),
340 let SubRegClasses = [(DPR dsub_0, dsub_1, dsub_2, dsub_3,
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsRegisterInfo.td267 let SubRegClasses = [(CPURegs sub_32)];
286 let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)];
290 let SubRegClasses = [(FGR32 sub_32)];
299 let SubRegClasses = [(HILO sub_32)];
/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinRegisterInfo.td226 let SubRegClasses = [(D16L lo16), (D16H hi16)];
230 let SubRegClasses = [(P16L lo16), (P16H hi16)];
234 let SubRegClasses = [(DP16L lo16), (DP16H hi16)];
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/
DMSP430RegisterInfo.td83 let SubRegClasses = [(GR8 subreg_8bit)];
/external/swiftshader/third_party/LLVM/utils/TableGen/
DCodeGenRegisters.h116 DenseMap<Record*,Record*> SubRegClasses; variable
DRegisterInfoEmitter.cpp550 i = RC.SubRegClasses.begin(), in runTargetDesc()
551 e = RC.SubRegClasses.end(); i != e; ++i) { in runTargetDesc()
DCodeGenRegisters.cpp320 if (!SubRegClasses.insert(std::make_pair(IdxRec, RCRec)).second) in CodeGenRegisterClass()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.td318 let SubRegClasses = [(CRBITRC sub_lt, sub_gt, sub_eq, sub_un)];
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td144 // SubRegClasses - Specify the register class of subregisters as a list of
146 list<dag> SubRegClasses = [];