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Searched refs:TmpReg (Results 1 – 25 of 53) sorted by relevance

123

/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp959 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
960 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg()
962 SrcReg = TmpReg; in PPCMoveToFPReg()
1038 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1039 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP()
1042 SrcReg = TmpReg; in SelectIToFP()
1137 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local
1139 TII.get(TargetOpcode::COPY), TmpReg) in SelectFPToI()
1141 SrcReg = TmpReg; in SelectFPToI()
1348 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2673 unsigned TmpReg = DstReg; in loadImmediate() local
2681 TmpReg = ATReg; in loadImmediate()
2701 unsigned TmpReg = DstReg; in loadImmediate() local
2703 TmpReg = getATReg(IDLoc); in loadImmediate()
2704 if (!TmpReg) in loadImmediate()
2708 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2710 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2723 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2724 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2726 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
[all …]
/external/llvm/lib/Target/Mips/AsmParser/
DMipsAsmParser.cpp2176 unsigned TmpReg = DstReg; in loadImmediate() local
2184 TmpReg = ATReg; in loadImmediate()
2204 unsigned TmpReg = DstReg; in loadImmediate() local
2206 TmpReg = getATReg(IDLoc); in loadImmediate()
2207 if (!TmpReg) in loadImmediate()
2211 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2213 TOut.emitRRR(ABI.GetPtrAdduOp(), DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
2227 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI); in loadImmediate()
2228 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI); in loadImmediate()
2230 TOut.emitRRR(AdduOp, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadImmediate()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp1018 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in PPCMoveToFPReg() local
1019 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned)) in PPCMoveToFPReg()
1021 SrcReg = TmpReg; in PPCMoveToFPReg()
1113 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass); in SelectIToFP() local
1114 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned)) in SelectIToFP()
1117 SrcReg = TmpReg; in SelectIToFP()
1213 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass); in SelectFPToI() local
1215 TII.get(TargetOpcode::COPY), TmpReg) in SelectFPToI()
1217 SrcReg = TmpReg; in SelectFPToI()
1435 unsigned TmpReg = createResultReg(RC); in processCallArgs() local
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp583 unsigned TmpReg = 0; // 0 for no temporary register in expand() local
592 TmpReg = scavengeGPR8(MI); in expand()
594 unsigned CurDstLoReg = (DstReg == SrcReg) ? TmpReg : DstLoReg; in expand()
595 unsigned CurDstHiReg = (DstReg == SrcReg) ? TmpReg : DstHiReg; in expand()
604 if (TmpReg) in expand()
605 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg); in expand()
612 if (TmpReg) { in expand()
614 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg); in expand()
694 unsigned TmpReg = 0; // 0 for no temporary register in expand() local
708 TmpReg = scavengeGPR8(MI); in expand()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DMLxExpansionPass.cpp223 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI)); in ExpandFPMLxInstruction() local
225 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
237 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DThumb1RegisterInfo.cpp655 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
659 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
662 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
666 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
671 MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp518 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
545 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
567 .addReg(TmpReg, RegState::Kill) // src in eliminateFrameIndex()
587 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
615 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) in eliminateFrameIndex()
623 .addReg(TmpReg, RegState::Kill) in eliminateFrameIndex()
668 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
670 TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
672 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DSIFixSGPRCopies.cpp227 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
229 BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(), TII->get(AMDGPU::COPY), TmpReg) in foldVGPRCopyIntoRegSequence()
232 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp286 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument
309 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
311 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
313 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
325 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithSymOffset() argument
333 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in emitLoadWithSymOffset()
335 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithSymOffset()
337 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI); in emitLoadWithSymOffset()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsTargetStreamer.cpp318 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithImmOffset() argument
341 emitRI(Mips::LUi, TmpReg, HiOffset, IDLoc, STI); in emitLoadWithImmOffset()
343 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
345 emitRRI(Opcode, DstReg, TmpReg, LoOffset, IDLoc, STI); in emitLoadWithImmOffset()
357 unsigned TmpReg, SMLoc IDLoc, in emitLoadWithSymOffset() argument
365 emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI); in emitLoadWithSymOffset()
367 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithSymOffset()
369 emitRRX(Opcode, DstReg, TmpReg, LoOperand, IDLoc, STI); in emitLoadWithSymOffset()
/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local
293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DThumbRegisterInfo.cpp570 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
574 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
577 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
581 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
586 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp290 unsigned TmpReg = MRI->createVirtualRegister( in ExpandFPMLxInstruction() local
293 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DThumbRegisterInfo.cpp570 unsigned TmpReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
574 emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, in eliminateFrameIndex()
577 emitLoadConstPool(MBB, II, dl, TmpReg, 0, Offset); in eliminateFrameIndex()
581 emitThumbRegPlusImmediate(MBB, II, dl, TmpReg, FrameReg, Offset, TII, in eliminateFrameIndex()
586 MI.getOperand(FIOperandNum).ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DThumb1FrameLowering.cpp518 unsigned &TmpReg) { in findTemporariesForLR() argument
519 PopReg = TmpReg = 0; in findTemporariesForLR()
525 TmpReg = 0; in findTemporariesForLR()
530 TmpReg = Reg; in findTemporariesForLR()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86SpeculativeLoadHardening.cpp1645 unsigned TmpReg = MRI->createVirtualRegister(PS->RC); in mergePredStateIntoSP() local
1649 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg) in mergePredStateIntoSP()
1656 .addReg(TmpReg, RegState::Kill); in mergePredStateIntoSP()
1666 unsigned TmpReg = MRI->createVirtualRegister(PS->RC); in extractPredStateFromSP() local
1671 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg) in extractPredStateFromSP()
1675 .addReg(TmpReg, RegState::Kill) in extractPredStateFromSP()
1765 unsigned TmpReg = MRI->createVirtualRegister(OpRC); in hardenLoadAddr() local
1800 TII->get(Is128Bit ? X86::VPORrr : X86::VPORYrr), TmpReg) in hardenLoadAddr()
1831 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg) in hardenLoadAddr()
1844 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg) in hardenLoadAddr()
[all …]
DX86CmovConversion.cpp765 unsigned TmpReg = MRI->createVirtualRegister(RC); in convertCmovInstsToBranches() local
768 bool Unfolded = TII->unfoldMemoryOperand(*MBB->getParent(), MI, TmpReg, in convertCmovInstsToBranches()
810 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg; in convertCmovInstsToBranches()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp773 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in spillSGPR() local
777 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in spillSGPR()
798 .addReg(TmpReg, RegState::Kill) // src in spillSGPR()
925 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in restoreSGPR() local
935 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpReg) in restoreSGPR()
944 .addReg(TmpReg, RegState::Kill); in restoreSGPR()
1153 unsigned TmpReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in eliminateFrameIndex() local
1154 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg) in eliminateFrameIndex()
1156 FIOp.ChangeToRegister(TmpReg, false, false, true); in eliminateFrameIndex()
DSIFixSGPRCopies.cpp291 unsigned TmpReg = MRI.createVirtualRegister(NewSrcRC); in foldVGPRCopyIntoRegSequence() local
294 TmpReg) in foldVGPRCopyIntoRegSequence()
297 MI.getOperand(I).setReg(TmpReg); in foldVGPRCopyIntoRegSequence()
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCRegisterInfo.cpp289 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; in eliminateCallFramePseudoInstr() local
302 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in eliminateCallFramePseudoInstr()
304 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in eliminateCallFramePseudoInstr()
305 .addReg(TmpReg, RegState::Kill) in eliminateCallFramePseudoInstr()
310 .addReg(TmpReg); in eliminateCallFramePseudoInstr()
DPPCFrameLowering.cpp664 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; in emitEpilogue() local
674 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) in emitEpilogue()
676 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) in emitEpilogue()
677 .addReg(TmpReg, RegState::Kill) in emitEpilogue()
682 .addReg(TmpReg); in emitEpilogue()
/external/llvm/lib/Target/X86/AsmParser/
DX86AsmParser.cpp264 unsigned BaseReg, IndexReg, TmpReg, Scale; member in __anon720aab8e0111::X86AsmParser::IntelExprStateMachine
274 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0), in IntelExprStateMachine()
385 BaseReg = TmpReg; in onPlus()
388 IndexReg = TmpReg; in onPlus()
422 BaseReg = TmpReg; in onMinus()
425 IndexReg = TmpReg; in onMinus()
455 TmpReg = Reg; in onRegister()
512 IndexReg = TmpReg; in onInteger()
601 BaseReg = TmpReg; in onRBrac()
604 IndexReg = TmpReg; in onRBrac()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DLegalizerHelper.cpp965 unsigned TmpReg = MRI.createGenericVirtualRegister( in lower() local
967 MIRBuilder.buildLoad(TmpReg, PtrReg, MMO); in lower()
972 MIRBuilder.buildAnyExt(DstReg, TmpReg); in lower()
975 MIRBuilder.buildSExt(DstReg, TmpReg); in lower()
978 MIRBuilder.buildZExt(DstReg, TmpReg); in lower()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp590 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; in expandCvtFPInt() local
599 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt()
604 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); in expandCvtFPInt()
605 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); in expandCvtFPInt()

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