| /external/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 209 unsigned UseReg = UseOp.getReg(); in foldOperand() local
211 = TargetRegisterInfo::isVirtualRegister(UseReg) ? in foldOperand()
212 MRI.getRegClass(UseReg) : in foldOperand()
213 TRI.getPhysRegClass(UseReg); in foldOperand()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 235 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, in isUnsafeToMoveAcross() argument
238 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
243 static unsigned UseReg(const MachineOperand& MO) { in UseReg() function
254 unsigned I2UseReg = UseReg(I2.getOperand(1)); in isSafeToMoveTogether()
321 unsigned I1UseReg = UseReg(I1.getOperand(1)); in isSafeToMoveTogether()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonCopyToCombine.cpp | 249 static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, in isUnsafeToMoveAcross() argument
252 return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || in isUnsafeToMoveAcross()
258 static unsigned UseReg(const MachineOperand& MO) { in UseReg() function
269 unsigned I2UseReg = UseReg(I2.getOperand(1)); in isSafeToMoveTogether()
336 unsigned I1UseReg = UseReg(I1.getOperand(1)); in isSafeToMoveTogether()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 693 unsigned UseReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
694 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs()
769 unsigned UseReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
770 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCVSXSwapRemoval.cpp | 702 unsigned UseReg = MI->getOperand(0).getReg(); in recordUnoptimizableWebs() local
703 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs()
779 unsigned UseReg = MI->getOperand(0).getReg(); in markSwapsForRemoval() local
780 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | InlineSpiller.cpp | 474 MachineInstr *InlineSpiller::traceSiblingValue(unsigned UseReg, VNInfo *UseVNI, in traceSiblingValue() argument
480 SibValues.insert(std::make_pair(UseVNI, SibValueInfo(UseReg, UseVNI))); in traceSiblingValue()
482 DEBUG(dbgs() << "Cached value " << PrintReg(UseReg) << ':' in traceSiblingValue()
487 DEBUG(dbgs() << "Tracing value " << PrintReg(UseReg) << ':' in traceSiblingValue()
493 WorkList.push_back(std::make_pair(UseReg, UseVNI)); in traceSiblingValue()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFoldOperands.cpp | 408 unsigned UseReg = UseOp.getReg(); in foldOperand() local
410 = TargetRegisterInfo::isVirtualRegister(UseReg) ? in foldOperand()
411 MRI->getRegClass(UseReg) : in foldOperand()
412 TRI->getPhysRegClass(UseReg); in foldOperand()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCodeEmitter.cpp | 739 unsigned UseReg = MO.getReg(); in getMachineOpValue() local
761 if (!RegisterMatches(UseReg, DefReg1, DefReg2)) { in getMachineOpValue()
780 Offset |= HexagonMCInstrInfo::SubregisterBit(UseReg, DefReg1, DefReg2); in getMachineOpValue()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 181 unsigned ARMSelectCallOp(bool UseReg);
2160 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { in ARMSelectCallOp() argument
2161 if (UseReg) in ARMSelectCallOp()
2376 bool UseReg = false; in SelectCall() local
2378 if (!GV || Subtarget->genLongCalls()) UseReg = true; in SelectCall()
2381 if (UseReg) { in SelectCall()
2391 unsigned CallOpc = ARMSelectCallOp(UseReg); in SelectCall()
2398 if (UseReg) in SelectCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 212 unsigned ARMSelectCallOp(bool UseReg);
2186 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { in ARMSelectCallOp() argument
2187 if (UseReg) in ARMSelectCallOp()
2401 bool UseReg = false; in SelectCall() local
2403 if (!GV || Subtarget->genLongCalls()) UseReg = true; in SelectCall()
2406 if (UseReg) { in SelectCall()
2416 unsigned CallOpc = ARMSelectCallOp(UseReg); in SelectCall()
2423 if (UseReg) in SelectCall()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2734 unsigned UseReg = lookUpRegForValue(SI); in selectSelect() local
2735 if (UseReg) in selectSelect()
2736 MRI.clearKillFlags(UseReg); in selectSelect()
4529 unsigned UseReg = lookUpRegForValue(I); in selectIntExt() local
4530 if (UseReg) in selectIntExt()
4531 MRI.clearKillFlags(UseReg); in selectIntExt()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 2645 unsigned UseReg = lookUpRegForValue(SI); in selectSelect() local
2646 if (UseReg) in selectSelect()
2647 MRI.clearKillFlags(UseReg); in selectSelect()
4443 unsigned UseReg = lookUpRegForValue(I); in selectIntExt() local
4444 if (UseReg) in selectIntExt()
4445 MRI.clearKillFlags(UseReg); in selectIntExt()
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 406 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
409 let Uses = [UseReg];
|
| D | MipsInstrInfo.td | 1477 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1480 let Uses = [UseReg];
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 414 class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> :
417 let Uses = [UseReg];
|
| D | MipsInstrInfo.td | 1764 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1767 let Uses = [UseReg];
|